blob: 9b2f0539a8d41c367b0284905f5dc89634a66780 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#ifndef X86_CF9_RESET_H
#define X86_CF9_RESET_H
/* Reset control port */
#define RST_CNT 0xcf9
#define FULL_RST (1 << 3)
#define RST_CPU (1 << 2)
#define SYS_RST (1 << 1)
/* Implement the bare reset, i.e. write to cf9. */
void do_system_reset(void);
void do_full_reset(void);
/* Called by functions below before reset. */
#if CONFIG(HAVE_CF9_RESET_PREPARE)
void cf9_reset_prepare(void);
#else
static inline void cf9_reset_prepare(void) {}
#endif
/* Prepare for reset, run do_*_reset(), halt. */
__noreturn void system_reset(void);
__noreturn void full_reset(void);
#endif /* X86_CF9_RESET_H */
|
