1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
|
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* cache.h: Cache maintenance API for ARMv7
*/
#ifndef ARMV7_CACHE_H
#define ARMV7_CACHE_H
/* SCTLR bits */
#define SCTLR_M (1 << 0) /* MMU enable */
#define SCTLR_A (1 << 1) /* Alignment check enable */
#define SCTLR_C (1 << 2) /* Data/unified cache enable */
/* Bits 4:3 are reserved */
#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
/* Bit 6 is reserved */
#define SCTLR_B (1 << 7) /* Endianness */
/* Bits 9:8 */
#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
#define SCTLR_Z (1 << 11) /* Branch prediction enable */
#define SCTLR_I (1 << 12) /* Instruction cache enable */
#define SCTLR_V (1 << 13) /* Low/high exception vectors */
#define SCTLR_RR (1 << 14) /* Round Robin select */
/* Bits 16:15 are reserved */
#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
/* Bit 18 is reserved */
/* Bits 20:19 reserved virtualization not supported */
#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission
implies PL1 XN */
#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */
#define SCTLR_U (1 << 22) /* Unaligned access behavior */
#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */
#define SCTLR_EE (1 << 25) /* Exception endianness */
/* Bit 26 is reserved */
#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */
#define SCTLR_TRE (1 << 28) /* TEX remap enable */
#define SCTLR_AFE (1 << 29) /* Access flag enable */
#define SCTLR_TE (1 << 30) /* Thumb exception enable */
/* Bit 31 is reserved */
/*
* Sync primitives
*/
/* data memory barrier */
static inline void dmb(void)
{
asm volatile ("dmb" : : : "memory");
}
/* data sync barrier */
static inline void dsb(void)
{
asm volatile ("dsb" : : : "memory");
}
/* instruction sync barrier */
static inline void isb(void)
{
asm volatile ("isb" : : : "memory");
}
/*
* Low-level TLB maintenance operations
*/
/* invalidate entire data TLB */
static inline void dtlbiall(void)
{
asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
}
/* invalidate entire instruction TLB */
static inline void itlbiall(void)
{
asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
}
/* invalidate entire unified TLB */
static inline void tlbiall(void)
{
asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
}
/* write data access control register (DACR) */
static inline void write_dacr(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val));
}
/* write translation table base register 0 (TTBR0) */
static inline void write_ttbr0(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
}
/* read translation table base control register (TTBCR) */
static inline uint32_t read_ttbcr(void)
{
uint32_t val = 0;
asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val));
return val;
}
/* write translation table base control register (TTBCR) */
static inline void write_ttbcr(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory");
}
/*
* Low-level cache maintenance operations
*/
/* branch predictor invalidate all */
static inline void bpiall(void)
{
asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
}
/* data cache clean and invalidate by MVA to PoC */
static inline void dccimvac(unsigned long mva)
{
asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva) : "memory");
}
/* data cache invalidate by set/way */
static inline void dccisw(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val) : "memory");
}
/* data cache clean by MVA to PoC */
static inline void dccmvac(unsigned long mva)
{
asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
}
/* data cache invalidate by MVA to PoC */
static inline void dcimvac(unsigned long mva)
{
asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva) : "memory");
}
/* data cache invalidate by set/way */
static inline void dcisw(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val) : "memory");
}
/* instruction cache invalidate all by PoU */
static inline void iciallu(void)
{
asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
}
/*
* Cache co-processor (CP15) access functions
*/
/* read cache level ID register (CLIDR) */
static inline uint32_t read_clidr(void)
{
uint32_t val = 0;
asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val));
return val;
}
/* read cache size ID register register (CCSIDR) */
static inline uint32_t read_ccsidr(void)
{
uint32_t val = 0;
asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
return val;
}
/* read cache size selection register (CSSELR) */
static inline uint32_t read_csselr(void)
{
uint32_t val = 0;
asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val));
return val;
}
/* write to cache size selection register (CSSELR) */
static inline void write_csselr(uint32_t val)
{
/*
* Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
* Bit 0 - 0 = data or unified cache, 1 = instruction cache
*/
asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val));
isb(); /* ISB to sync the change to CCSIDR */
}
/* read system control register (SCTLR) */
static inline unsigned int read_sctlr(void)
{
unsigned int val;
asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
return val;
}
/* write system control register (SCTLR) */
static inline void write_sctlr(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
isb();
}
/*
* Cache maintenance API
*/
/* dcache clean and invalidate all (on current level given by CCSELR) */
void dcache_clean_invalidate_all(void);
/* dcache clean by modified virtual address to PoC */
void dcache_clean_by_mva(unsigned long addr, unsigned long len);
/* dcache clean and invalidate by modified virtual address to PoC */
void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
/* dcache invalidate all (on current level given by CCSELR) */
void dcache_invalidate_all(void);
/* dcache and MMU disable */
void dcache_mmu_disable(void);
/* dcache and MMU enable */
void dcache_mmu_enable(void);
/* icache invalidate all (on current level given by CSSELR) */
void icache_invalidate_all(void);
/* tlb invalidate all */
void tlb_invalidate_all(void);
/*
* Generalized setup/init functions
*/
/* invalidate all caches on ARMv7 */
void armv7_invalidate_caches(void);
/* mmu initialization (set page table address, set permissions, etc) */
void mmu_init(void);
enum dcache_policy {
DCACHE_OFF,
DCACHE_WRITEBACK,
DCACHE_WRITETHROUGH,
};
/* mmu range configuration (set dcache policy) */
void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
enum dcache_policy policy);
#endif /* ARMV7_CACHE_H */
|
