1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
|
/*
*
* Copyright 2013 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* cache.h: Cache maintenance API for ARM64
*/
#ifndef ARM64_CACHE_H
#define ARM64_CACHE_H
#include <stddef.h>
#include <stdint.h>
/*
* Cache maintenance API
*/
/* dcache clean and invalidate all (on current level given by CCSELR) */
void dcache_clean_invalidate_all(void);
/* dcache clean by virtual address to PoC */
void dcache_clean_by_mva(void const *addr, size_t len);
/* dcache clean and invalidate by virtual address to PoC */
void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
/* dcache invalidate by virtual address to PoC */
void dcache_invalidate_by_mva(void const *addr, size_t len);
void dcache_clean_all(void);
/* dcache invalidate all (on current level given by CCSELR) */
void dcache_invalidate_all(void);
/* returns number of bytes per cache line */
unsigned int dcache_line_bytes(void);
/* dcache and MMU disable */
void dcache_mmu_disable(void);
/* dcache and MMU enable */
void dcache_mmu_enable(void);
/* perform all icache/dcache maintenance needed after loading new code */
void cache_sync_instructions(void);
/* Ensure that loaded program segment is synced back from cache to PoC */
void arch_program_segment_loaded(void const *addr, size_t len);
/* tlb invalidate all */
void tlb_invalidate_all(void);
/* Invalidate all of the instruction cache for PE to PoU. */
static inline void icache_invalidate_all(void)
{
__asm__ __volatile__(
"dsb sy\n\t"
"ic iallu\n\t"
"dsb sy\n\t"
"isb\n\t"
: : : "memory");
}
#endif /* ARM64_CACHE_H */
|
