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|
List of upstream coreboot maintainers
and how to submit coreboot changes
This represents the list of maintainers that work on the upstream coreboot
code base (on coreboot.org). Maintainers are assigned to topics and when
applicable to subtrees of the source tree. You'll find some subtrees that
don't have a maintainer. If you are looking for reviewers for such a sub-
tree, it's often a good choice to look at the git history to see who worked
on it last.
Please try to follow the guidelines below. This will make things
easier on the maintainers. Not all of these guidelines matter for every
trivial patch so apply some common sense.
1. Always _test_ your changes, however small, on at least 1 or
2 people, preferably many more.
2. Try to release a few ALPHA test versions to gerrit. Announce
them onto the coreboot mailing list and IRC channel and await
results. This is especially important on coreboot core changes,
but also for device drivers, because often that's the only way
you will find things like the fact revision 3 chipset needs
a magic fix you didn't know about, or some clown changed the
chips on a board and not its name. (Don't laugh!)
3. Make sure your changes compile correctly in multiple
configurations. In particular check that changes work for all
boards in the tree (use abuild!)
4. When you are happy with a change make it generally available for
testing in gerrit and await feedback.
5. Make your patch available through coreboot's gerrit code review
system, and add the relevant maintainer from this list as a code
reviewer. Be prepared to get your changes sent back with seemingly
silly requests about formatting and variable names. These aren't
as silly as they seem. One job the maintainers do is to keep
things looking the same. Sometimes this means that the clever
hack in your mainboard or chipset to get around a problem actually
needs to become a generalized coreboot feature ready for next time.
PLEASE check your patch with the automated style checker
(util/lint/checkpatch.pl) to catch trival style violations.
See https://www.coreboot.org/Coding_Style for guidance here.
PLEASE add the maintainers that are generated by
util/scripts/get_maintainer.pl as reviewers. The results returned
by the script will be best if you have git installed and are
making your changes in a branch derived from coreboot.org's latest
git tree.
PLEASE try to include any credit lines you want added with the
patch. It avoids people being missed off by mistake and makes
it easier to know who wants adding and who doesn't.
PLEASE document known bugs. If it doesn't work for everything
or does something very odd once a month document it.
PLEASE remember that submissions must be made under the terms
of the OSDL certificate of contribution and should include a
Signed-off-by: line. The current version of this "Developer's
Certificate of Origin" (DCO) is listed at
https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure.
6. Make sure you have the right to send any changes you make. If you
do changes at work you may find your employer owns the patch
not you.
7. Happy hacking.
Descriptions of section entries:
M: Maintainer: FullName <address@domain>
Must be registered to Gerrit (https://review.coreboot.org/).
Should have experience with upstream coreboot development.
R: Designated reviewer: FullName <address@domain>
These reviewers should be CCed on patches.
L: Mailing list that is relevant to this area
W: Web-page with status/info
Q: Patchwork web based patch tracking system site
T: SCM tree type and location.
Type is one of: git, hg, quilt, stgit, topgit
S: Status, one of the following:
Supported: Someone is continuously paid to look after this and
a reaction to review requests can be expected
within a few days, a month at most.
Maintained: Someone actually looks after it and a reaction to
review requests can usually be expected within a
few weeks.
Odd Fixes: It has a maintainer but they don't have time to do
much other than throw the odd patch in. See below..
Orphan: No current maintainer [but maybe you could take the
role as you write your new code].
Obsolete: Old code. Something tagged obsolete generally means
it has been replaced by a better system and you
should be using that.
F: Files and directories with wildcard patterns.
A trailing slash includes all files and subdirectory files.
F: drivers/net/ all files in and below drivers/net
F: drivers/net/* all files in drivers/net, but not below
F: */net/* all files in "any top level directory"/net
One pattern per line. Multiple F: lines acceptable.
N: Files and directories with regex patterns.
N: [^a-z]tegra all files whose path contains the word tegra
One pattern per line. Multiple N: lines acceptable.
scripts/get_maintainer.pl has different behavior for files that
match F: pattern and matches of N: patterns. By default,
get_maintainer will not look at git log history when an F: pattern
match occurs. When an N: match occurs, git log history is used
to also notify the people that have git commit signatures.
X: Files and directories that are NOT maintained, same rules as F:
Files exclusions are tested before file matches.
Can be useful for excluding a specific subdirectory, for instance:
F: net/
X: net/ipv6/
matches all files in and below net excluding net/ipv6/
K: Keyword perl extended regex pattern to match content in a
patch or file. For instance:
K: of_get_profile
matches patches or files that contain "of_get_profile"
K: \b(printk|pr_(info|err))\b
matches patches or files that contain one or more of the words
printk, pr_info or pr_err
One regex pattern per line. Multiple K: lines acceptable.
Note: For the hard of thinking, this list is meant to remain in alphabetical
order. If you could add yourselves to it in alphabetical order that would be
so much easier [Ed]
Maintainers List (try to look for most precise areas first)
-----------------------------------
RISC-V ARCHITECTURE
M: Ronald Minnich <rminnich@gmail.com>
M: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
S: Maintained
F: src/arch/riscv/
F: src/soc/sifive/
F: src/soc/ucb/
F: src/mainboard/emulation/*-riscv/
F: src/mainboard/sifive/
F: util/riscv/
POWER8 ARCHITECTURE
M: Ronald Minnich <rminnich@gmail.com>
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
S: Maintained
F: src/arch/power8/
F: src/cpu/qemu-power8/
F: src/mainboard/emulation/qemu-power8/
LENOVO EC
M: Alexander Couzens <lynxis@fe80.eu>
S: Maintained
F: src/ec/lenovo/
LENOVO MAINBOARDS
M: Alexander Couzens <lynxis@fe80.eu>
M: Patrick Rudolph <siro@das-labor.org>
S: Maintained
F: src/mainboard/lenovo/
GETAC P470 MAINBOARD
M: Patrick Georgi <patrick@georgi.software>
S: Maintained
F: src/mainboard/getac/p470
INTEL PINEVIEW CHIPSET
M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/northbridge/intel/pineview/
INTEL D510MO MAINBOARD
M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/mainboard/intel/d510mo
INTEL X4X CHIPSET
M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/northbridge/intel/x4x/
GIGABYTE GA-G41M-ES2L MAINBOARD
M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/mainboard/gigabyte/ga-g41m-es2l
GOOGLE PANTHER MAINBOARD
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
S: Supported
F: src/mainboard/google/panther/
INTEL MINNOWBOARD MAX MAINBOARD
M: Huang Jin <huang.jin@intel.com>
M: York Yang <york.yang@intel.com>
S: Supported
F: src/mainboard/intel/minnowmax/
INTEL FSP BAYTRAIL CHIP & CRBs
M: Huang Jin <huang.jin@intel.com>
M: York Yang <york.yang@intel.com>
S: Supported
F: src/soc/intel/fsp_baytrail/
F: src/vendorcode/intel/fsp1_0/baytrail/
F: src/mainboard/intel/bakersport_fsp/
F: src/mainboard/intel/bayleybay_fsp/
INTEL FSP BROADWELL-DE SOC & CRB
M: York Yang <york.yang@intel.com>
S: Supported
F: src/soc/intel/fsp_broadwell_de/
F: src/vendorcode/intel/fsp1_0/broadwell_de/
F: src/mainboard/intel/camelbackmountain_fsp/
INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
M: SweeHeng Wong <swee.heng.wong@intel.com>
M: Jeff Daly <jeffrey.daly@intel.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
M: David Guckian <david.guckian@intel.com>
M: Shine Liu <shine.liu@intel.com>
S: Supported
F: src/mainboard/intel/harcuvar/
F: src/soc/intel/denverton_ns/
F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/
FSP 1.0 RANGELEY & CRB
M: David Guckian <david.guckian@intel.com>
M: Fei Wang <fei.z.wang@intel.com>
S: Supported
F: src/cpu/intel/fsp_model_406dx/
F: src/northbridge/intel/fsp_rangeley/
F: src/southbridge/intel/fsp_rangeley/
F: src/vendorcode/intel/fsp1_0/rangeley/
F: src/mainboard/intel/mohonpeak/
INTEL FSP 1.0
M: Huang Jin <huang.jin@intel.com>
M: York Yang <york.yang@intel.com>
S: Supported
F: src/drivers/intel/fsp1_0/
INTEL FSP 1.1
M: Lee Leahy <leroy.p.leahy@intel.com>
M: Huang Jin <huang.jin@intel.com>
M: York Yang <york.yang@intel.com>
S: Supported
F: src/drivers/intel/fsp1_1/
INTEL FSP 2.0
M: Andrey Petrov <andrey.petrov@gmail.com>
S: Maintained
F: src/drivers/intel/fsp2_0/
INTEL STRAGO MAINBOARD
M: Hannah Williams <hannah.williams@intel.com>
S: Supported
F: /src/mainboard/intel/strago/
INTEL BRASWELL SOC
M: Hannah Williams <hannah.williams@intel.com>
S: Supported
F: /src/soc/intel/braswell
F: /src/vendorcode/intel/fsp/fsp1_1/braswell
INTEL APOLLOLAKE_SOC
M: Andrey Petrov <andrey.petrov@gmail.com>
S: Maintained
F: src/soc/intel/apollolake/
ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
S: Supported
F: src/mainboard/asus/kfsn4-dre/
F: src/mainboard/asus/kfsn4-dre_k8/
ASUS KCMA-D8 MAINBOARD
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
S: Supported
F: src/mainboard/asus/kcma-d8/
ASUS KGPE-D16 MAINBOARD
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
S: Supported
F: src/mainboard/asus/kgpe-d16/
PC ENGINES ALL MAINBOARDS
M: Piotr Król <piotr.krol@3mdeb.com>
M: Michał Żygowski <michal.zygowski@3mdeb.com>
S: Supported
F: src/mainboard/pcengines/
AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
S: Supported
F: src/cpu/amd/family_10h-family_15h/
F: src/northbridge/amd/amdfam10/
F: src/northbridge/amd/amdmct/
F: src/northbridge/amd/amdht/
AMD SB700 (NON-CIMX) SOUTHBRIDGE
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
S: Supported
F: src/southbridge/amd/sb700/
AMD SR5650 SOUTHBRIDGE
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
S: Supported
F: src/southbridge/amd/sr5650/
ASPEED AST2050 DRIVER & COMMON CODE
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
S: Supported
F: src/drivers/aspeed/common/
F: src/drivers/aspeed/ast2050/
ATI MACH64 Driver
S: Orphan
F: src/drivers/ati/mach64/
ABUILD
M: Patrick Georgi <patrick@georgi-clan.de>
M: Martin Roth <gaumless@gmail.com>
S: Supported
F: util/abuild/
ACPI
F: src/acpi/
F: src/arch/x86/acpi/
F: util/acpi/
LZ4 COMPRESSION
M: Julius Werner <jwerner@chromium.org>
S: Supported
F: src/commonlib/lz4*
F: payloads/libpayload/liblz4/
F: util/cbfstool/lz4/
ARM ARCHITECTURE
M: Julius Werner <jwerner@chromium.org>
S: Supported
F: src/arch/arm/
F: src/arch/arm64/
F: src/soc/mediatek/
F: src/soc/nvidia/
F: src/soc/rockchip/
F: util/nvidia/
F: util/rockchip/
ORPHANED ARM SOCS
S: Orphaned
F: src/cpu/allwinner/
F: src/cpu/armltd/
F: src/cpu/ti/
F: src/soc/broadcom/
F: src/soc/marvell/
F: src/soc/qualcomm/
F: src/soc/samsung/
F: util/arm_boot_tools/
F: util/broadcom/
F: util/exynos/
F: util/ipqheader/
MIPS ARCHITECTURE
F: src/arch/mips/
F: src/cpu/mips/
F: src/soc/imgtec/
F: util/bimgtool/
X86 ARCHITECTURE
F: src/arch/x86/
F: src/cpu/x86/
F: src/drivers/pc80/
F: src/include/pc80/
F: src/include/cpu/x86/
INTEL SUPPORT
M: Patrick Rudolph <siro@das-labor.org>
S: Maintained
F: src/vendorcode/intel/
F: src/cpu/intel/
F: src/northbridge/intel/
F: src/southbridge/intel/
F: src/soc/intel/
F: src/drivers/intel/
F: src/include/cpu/intel/
AMD SUPPORT
F: src/vendorcode/amd/
F: src/cpu/amd/
F: src/northbridge/amd/
F: src/southbridge/amd/
F: src/include/cpu/amd/
VIA SUPPORT
F: src/cpu/via/
F: src/northbridge/via/
F: src/southbridge/via/
LINT SCRIPTS
M: Patrick Georgi <patrick@georgi-clan.de>
M: Martin Roth <gaumless@gmail.com>
S: Supported
F: util/lint/
INTELTOOL
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
F: util/inteltool/
INTELMETOOL
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
F: util/intelmetool/
ME_CLEANER
M: Nicola Corna <nicola@corna.info>
W: https://github.com/corna/me_cleaner
S: Maintained
F: util/me_cleaner/
IFDTOOL
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
F: util/ifdtool/
BUILD SYSTEM
M: Patrick Georgi <patrick@georgi-clan.de>
M: Martin Roth <gaumless@gmail.com>
S: Supported
F: Makefile
F: *.inc
F: src/include/kconfig.h
F: util/kconfig/
F: util/sconfig/
F: util/xcompile/
F: util/genbuild_h/
BOARD STATUS
F: util/board_status/
BINARY OBJECTS
F: 3rdparty/blobs/
VERIFIED BOOT
F: 3rdparty/vboot/
F: src/vendorcode/google/chromeos/
F: src/include/tpm.h
F: src/include/tpm_lite/
RESOURCE ALLOCATOR
F: src/device/*
F: src/include/device/
F: src/include/cpu/cpu.h
OPTION ROM EXECUTION & X86EMU
F: src/device/oprom/
CBFS
F: src/include/cbfs.h
F: src/include/cbfs_serialized.h
F: util/cbfstool/
CBMEM
F: src/include/cbmem.h
F: src/include/cbmem_id.h
F: util/cbmem/
CONSOLE
F: src/console/
F: src/include/console/
F: src/drivers/uart/
NVRAM
F: util/nvramtool/
F: util/optionlist/
F: payloads/nvramcui/
LIBPAYLOAD
F: payloads/libpayload/
BAYOU PAYLOAD
F: payloads/bayou/
COREINFO PAYLOAD
F: payloads/coreinfo/
EXTERNAL PAYLOADS INTEGRATION
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
M: Martin Roth <gaumless@gmail.com>
F: payloads/external
VERIFIED BOOT 2
M: Aaron Durbin <adurbin@chromium.org>
F: src/vendorcode/google/chromeos/vboot2/
TPM SUPPORT
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
F: src/drivers/*/tpm/
F: src/security/tpm12/
F: src/security/tpm20/
F: util/tss-generator/
DOCKER
M: Martin Roth <gaumless@gmail.com>
S: Supported
F: util/docker/
TOOLCHAIN
F: util/crossgcc/
GIT
F: .git*
F: /util/gitconfig
SUPERIOS & SUPERIOTOOL
M: Felix Held <felix-coreboot@felixheld.de>
S: Maintained
F: src/superio/
F: util/superiotool/
MEMLAYOUT
M: Julius Werner <jwerner@chromium.org>
S: Supported
F: */memlayout.h
F: *.ld
MISSING: TIMERS / DELAYS
MISSING: TIMESTAMPS
MISSING: FMAP
MISSING: GPIO
MISSING: SMP
MISSING: DMP / QEMU-X86
MISSING: ELOG
MISSING: SPI
THE REST
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
T: git https://review.coreboot.org/coreboot
S: Buried alive in mainboards
F: *
F: */
# *** Infrastructure Owners***
# This is intended to let people know who they should contact for issues with various infrastructure pieces.
# Hardware
# Owners: Stefan, Patrick
# Backups:
# Web Server
# Owners: Stefan, Patrick
# Backups:
# Website
# Owners: Martin, Philipp
# Backups: Patrick, Stefan
# Documentation Website
# Owners: Patrick, Philipp
# Backups:
# Wiki
# Owners: Stefan, Patrick
# Backups:
# Gerrit
# Owners: Stefan, Patrick
# Backups: Martin
# Jenkins
# Owners: Patrick, Martin
# Backups:
# Bug Tracker
# Owners: Lynxis,
# Backups: Martin,
# Mailing List
# Owners: Stefan, Patrick
# Backups: Martin,
# Software Freedom Conservancy
# Main contact: Martin
# “Official” contact: Stefan
|