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2021-09-26Revert "Revert "util/abuild: Regenerate xcompile on every abuild run""Reka Norman
This reverts commit d94f8bbe9da290e120df20bf244920436e9510e7. This is a reland of https://review.coreboot.org/57651. The original change broke parallel abuild runs since the xcompile file was deleted by every recursive call to abuild. This issue was fixed by rebasing on top of a change which only regenerates the xcompile on non-recursive calls. BUG=None TEST=Parallel abuild run succeeds. Change-Id: I086ba7b2ae1b8b14459838bd18ce962a84aa306d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-24elogtool: Fix off-by-one error in month in timestampRicardo Quesada
elogtool was setting the timestamp with the wrong value in the month. This CL fixes that by incrementing the month by one. This is needed since gmtime() returns the month value starting at 0. TEST=pytest elogtool_test.py (see next CL in relation chain) Change-Id: I00f89ed99b049caafba2e47feae3c068245f9021 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-09-24util/abuild: Run `make .xcompile` only onceNico Huber
If abuild called itself recursively, the file already exists and we can spare us one evaluation of all the makefiles per recursive abuild run. Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-09-23kconfig_lint: restrict definition of defaults for choice elementsMichael Niewöhner
Defining defaults for symbols used inside choices is not allowed. Add a check for this, so we can drop the existent, overly restrictive checks in the follow-up change. Change-Id: I45bce2633dbd168fceb81ceae9b68621b28526e8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-23util/crossgcc: Update gcc to 11.2Patrick Georgi
Various fixes to gnat and the improved nds32 backend have been merged into gcc by now, so we don't need to carry those patches anymore. Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-23util/spd_tools: Remove old lp4x and ddr4 versions of spd_toolsReka Norman
The migration to the new unified version of spd_tools is complete, so the old lp4x and ddr4 versions can be removed. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6b1fc297739efc8dc7d7eec64956bf3343984604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23util/spd_tools: Sort platforms_manifest entries by set numberReka Norman
Ensure that the order of entries in each platform manifest is consistent every time spd_gen is run. BUG=b:191776301 TEST=Run spd_gen for lp4x and ddr4, check that the manifests are unchanged. Change-Id: I7bfea65c8fc781df80a8725c0cf20c7547c857e8 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23util/mb/google: Update templates to refer to the new spd_toolsReka Norman
Update the new variant templates to refer to the new unified version of spd_tools: - Update the comments in mem_parts_used.txt - Change the placeholder SPD in Makefile.inc to 'placeholder' BUG=b:191776301 TEST=None Change-Id: I03265de0d1182da81dd25a2fe6f940a0b82e5fa4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23amdfwtool: Add an optional column of levelZheng Bao
The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23util/spd_tools: Remove PLK platformReka Norman
Currently spd_tools treats PCO and PLK as separate platforms. This is unnecessary since they have the same SPD requirements. Remove PLK, and use PCO as the platform for all zork variants. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7eeeab53fb3e0d92c3675fb80b4747297d4257ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/57771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-23util/spd_tools: Add README for unified spd_toolsReka Norman
Combine the existing lp4x and ddr4 READMEs into a single file, and update it to reflect the new unified version of the tools. BUG=b:191776301 TEST=None Change-Id: I866932a1d0b5b6b47b0daff893b37de7a302b4e6 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21util/spd_tools: Add 'Generated by' string to part_id_gen output filesReka Norman
Add a 'Generated by' string to the generated Makefile.inc and dram_id.generated.txt, showing the command used to generate the files. BUG=b:191776301 TEST=Run part_id_gen, check that the generated files contain the string Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ic9a7826212a732288f36f111b7bc20365a1f702d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21util/spd_tools: Automatically determine the SPD dir in part_id_genReka Norman
Currently, one of the arguments to part_id_gen is the directory containing the SPD files, e.g. spd/lp4x/set-0. This requires the user of the tool to understand the spd/ directory structure, and manually look up the set number corresponding to their platform. Change part_id_gen to take the platform and memory technology as arguments instead of the SPD directory, and automatically determine the SPD directory by reading the platforms manifest file generated by spd_gen.go. BUG=b:191776301 TEST=Run part_id_gen and check that the generated Makefile.inc and dram_id.generated.txt are the same as before. Example: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: I7cd7243d76b5769e8a15daa56b8438274bdd8e96 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21util/spd_tools: Add max ID check for auto-generated IDs to part_id_genReka Norman
Currently, the maximum part ID of 15 is enforced only for manually assigned IDs. Also enforce it for automatically assigned IDs. BUG=b:191776301 TEST=part_id_gen fails when the number of part IDs which would be assigned is greater than MaxMemoryId. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I802190a13b68439ccbcdb28300ccc5fd1b38a9c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21util: Add DDR4 generic SPD for 4JQA-0622ADFrank Wu
Add SPD support for DDR4 memory part BUG=b:199469240 TEST=none Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ie67cf6b90304f0bcf80838866c7461c0cea86dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-21Revert "util/abuild: Regenerate xcompile on every abuild run"Reka Norman
This reverts commit a2c009bd94aa3c9694158f9e28184ccbd94df42b. Reason for revert: Breaks parallel abuilds. Change-Id: I368b189050d519769f4852fea8e255e9b31b27b6 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-21elogtool: compile in 32-bit platformsRicardo Quesada
This CL fixes a compilation error that happens in 32-bit platforms. This error happens because printf() was using %ld instead of %zu to print size_t variables. This CL fixes it. BUG=b:200608182 TEST=emerge-kevin (ARM 32-bit) TEST=emerge-eve (Intel 64-bit) Change-Id: I340e108361c052601f2b126db45caf2e35ee7ace Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-09-20util/spd_tools: Implement a unified version of the part_id_gen toolReka Norman
Currently there are two versions of gen_part_id.go, one for LP4x and one DDR4. This change implements a unified version of this tool. The new part_id_gen.go is almost identical to the existing ddr4/gen_part_id.go. The new version was based on the ddr4 version and not the lp4x version, since the ddr4 version contains extra logic to support fixed IDs in the mem_parts_used files. The only non-trivial change from ddr4/gen_part_id.go is to include the full paths of SPD files in the generated Makefile.inc. E.g. instead of SPD_SOURCES += lp4x-spd-1.hex the full path relative to the coreboot root directory is included: SPD_SOURCES += spd/lp4x/set-0/spd-1.hex BUG=b:191776301 TEST=For each variant of brya/volteer/dedede/guybrush/zork, run part_id_gen and verify that the generated Makefile.inc and dram_id.generated.txt are identical to those currently in the src tree, except for the modified SPD file paths in Makefile.inc. Example: util/spd_tools/bin/part_id_gen \ spd/lp4x/set-0 \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: Ib33d09076f340f688519dae7956a2b27af090c0b Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-20util/abuild: Regenerate xcompile on every abuild runReka Norman
Currently, running abuild in a fresh checkout without having built the toolchain results in the following confusing behaviour: 1. Run abuild. It fails due to the missing coreboot toolchain, and the error message suggests running `make crossgcc`. 2. Run `make crossgcc`. It succeeds. 3. Re-run abuild. It still fails due to a missing coreboot toolchain. This happens because the first abuild run generates an xcompile file which uses the system toolchain. The second abuild run doesn't regenerate the xcompile, so it still fails due to the non-coreboot toolchain. To avoid this confusing behaviour, regenerate the xcompile file every time abuild is run. BUG=None TEST=Perform the steps above in a clean checkout. The second abuild run now succeeds. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I78a7702c45cecbfe8460ec55df03741e5ced94b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-20sconfig: Emit device structure pointers if alias names are providedFurquan Shaikh
This change uses _dev_${ALIAS_NAME} as the name for `struct device` if the device has an alias. In addition to that, it emits _dev_${ALIAS_NAME}_ptr which points to the device structure. This allows developers to directly reference a particular device in the tree using alias name without having to walk the entire path. In later CLs, mainboards are transitioned to use this newly emitted device structure pointers. Change-Id: I8306d9efba8e5ca5c0bda41baac9c90ad8b73ece Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-19util/crossgcc: Update binutils to 2.37Patrick Georgi
Change-Id: Ia68d4d9f836ad23fb8f6a7203a78b4ea40c7c43b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-17util/spd_tools: Implement a unified version of the spd_gen toolReka Norman
Currently there are two versions of spd_tools: one for LP4x and one for DDR4. This change is the first step in unifying these into a single tool. This change implements a unified version of the spd_gen tool, by combining the functionality currently in lp4x/gen_spd.go and ddr4/gen_spd.go. The unified version takes the memory technology as an argument, and generates SPD files for all platforms supporting that technology. BUG=b:191776301 TEST=Compare the SPDs generated by the old and new versions of the tool for all supported platforms. For reference, the test script used is here: https://review.coreboot.org/c/coreboot/+/57511 Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7fc036996dbafbb54e075da0c3ac2ea0886a6db2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-17amdfwtool: Detect the flag multilevel to decide the actual valueZheng Bao
To save the space for FW, some of the FWs are going to be defined as LVL2 entries. To be compatible to "flattened" layout, we still drop the LVL2 entry to level1 if there is only one level. Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-16util/liveiso: Make neovim the default editorFelix Singer
Make neovim the default editor and create an alias for vim. The NixOS module for neovim is currently broken. Thus, add a note to `description.md` to switch to that later. Change-Id: I9345a6e32f3035565e55e50579c97121b4987d83 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57393 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16util/nixshell: Add Nix shell for toolchain compilationFelix Singer
Add a Nix shell file which provides an environment for compilation of the coreboot toolchain. The Nix shell can be used by running the following command: $ nix-shell --pure util/nixshell/toolchain.nix The `--pure` parameter is optional, but it makes sure that the environment is as minimal as possible and does not contain any unrelated or unneeded software or configuration. Once compiled, the coreboot toolchain can be used without loading the shell environment. If `--pure` is used, SSL connections won't work since the `SSL_CERT_FILE` environment variable is not configured, which makes the build tool unable to download the source files. Thus, let it point to the system certificate store. Change-Id: I341ee28c5451d2c6cb4ff22de67161d99f4ca77a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-16elogtool: add "add" commandRicardo Quesada
Adds "add" command to elogtool. This command allows adding elog events manually. It supports event type and, optionally, event data. If the free buffer space is < 1/4 of the total space, it shrinks the buffer, making sure that ~1/4 of the free space is available. BUG=b:172210863 TEST=./elogtool add 0x17 0101 ./elogtool add 0x18 Repeated the same tests on buffers that needed to be shrunk. Change-Id: Ia6fdf4f951565f842d1bff52173811b52f617f66 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16elogtool: add next_available_event_offset functionRicardo Quesada
This function is "extracted" from cmd_clear(). This new function will be called from cmd_add(), and new command that will be added in a future CL (see CL chain). Additional minor fixes: - calls usage() if no valid commands are passed. - Slightly improves usage() output. Needed for cmd_clear() BUG=b:172210863 TEST=elogtool clear Change-Id: I0d8ecc893675758d7f90845282a588d367b55567 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16util/sconfig: Update static.c to include boot/coreboot_tables.hTim Wawrzynczak
This allows the devicetree to directly access names defined in the coreboot tables API. BUG=b:194967458 BRANCH=dedede Change-Id: Ieb2d00095f54b2363a21f9c5ef8205110a36f746 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-15amdfwtool: Add new SOC mendocinoZheng Bao
Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-15util/liveiso: Install UEFITool packagesFelix Singer
Install both versions of UEFITool, the one with the old engine and the new one. It's not possible to use both packages in the same environment, since there is a collision between the names of the binary files. To make sure a specific package is used, a new environment needs to be spawned with the following command: $ nix-shell -p <package_name> The UEFITool binaries can be executed from the shell then. Change-Id: Ia5d679c6e7cd01c2ab819bd6c085596a926c494d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-13util/kconfig: Add pre-built parserPatrick Georgi
It avoids the dependency on bison/flex, minimally speeds up the build and also works around weird race conditions in some versions of bison that need more investigation. The issue this avoids manifests as a build error when creating parser.tab.c: input in flex scanner failed make: *** [util/kconfig/Makefile.inc:66: build/util/kconfig/parser.tab.c] Error 2 Since the error happens within bison the alternative would be to make bison part of our crossgcc environment to ensure that no broken OS build is used. BUG=b:197515860 TEST=things build with bison not installed Change-Id: Ib35dfb7beafc0a09dc333e962b1e3f33df46a854 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-13util/kconfig: Simplify dependencies for parser.tab.*Patrick Georgi
With parser.tab.h depending on parser.tab.c it's possible for make to initiate the creation of parser.tab.c, then try to compile it, even though parser.tab.h is still missing. This isn't normally an issue yet because bison creates them both at a time but with pre-compiled files this will become a problem. Pattern rules support (until recently as a special case that no other type of rule could implement) multiple targets that are actually treated as "one command creates multiple output files" so use that to state the relationship properly. Change-Id: I4aa7eca9d3123808e0665a15a99c04fac7384940 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-13util/sconfig: Extract handling of SMBIOS dataAngel Pons
Move the code that handles devices' SMBIOS data into a helper function. Change-Id: I4f36d6c6f26e79558d360d319d09b0b8426def0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57369 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-13util/sconfig: Always generate SMBIOS CPP guardsAngel Pons
Manually maintaining a list of fields just to avoid printing some unnecessary CPP guards isn't worth the maintenance burden. Instead, always generate these guards, even if they guard nothing. Change-Id: I6c84180d83ac39a895e02d196acb7074eb052d7f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57459 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10elogtool: add "clear" commandRicardo Quesada
Adds "clear" command to cbfsutil/elogtool tool. "clear" clears the RW_ELOG region by using either: * flashrom if no file is provided * or using file write if an input file is provided. The region is filled with ELOG_TYPE_EOL. And a ELOG_TYPE_LOG_CLEAR event is inserted. Additionally, it does a minor cleanup to command "list", like: * use buffer_end() * add "list" to the cmds struct * and make elog_read() very similar to elog_write() Usage: $ elogtool clear BUG=b:172210863 TEST=elogtool clear && elogtool list elogtool clear -f invalid.raw elogtool clear -f valid.raw Change-Id: Ia28a6eb34c82103ab078a0841b022e2e5e430585 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2021-09-10util/liveiso/console.nix: Remove unneeded argument bodyFelix Singer
Change-Id: Iebd994a46e870e42431d0fc71dd14b1c2b01f9aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57536 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-10util/liveiso: Disable strict checking of access to MMIO memoryFelix Singer
Change-Id: Ie859490d3cb3b8c56437cbd6c3e46525c580d3f4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57535 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-09util/cbmem: Add -2/--2ndtolast option to print second-to-last boot logJulius Werner
On some platforms, runtime firmware crashes write logs to the CBMEM console. For those, since a crash reboots the system, by the time we have a chance to run `cbmem` again the boot where the crash happened will be the one before the "last" (current) boot. So cbmem -1 doesn't show the interesting part, and cbmem -c potentially shows a lot that is cumbersome to dig through. This patch introduces a new option cbmem -2 to explicitly show only the boot cycle before the last one. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6725698f4c9ae07011cbacf0928544cebb4ad6f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-09-08util/amdtools: Add script to update the SPI speed in the EFS headerMartin Roth
The update_efs_spi_speed allows changing the SPI speed manually in a binary that has already been built. This will allow binaries not built for the EM100 SPI ROM emulator to be updated so that they will work. There is a corresponding change that will check to see if the EFS value has been modified from the original speed and will prevent coreboot from updating the SPI speed and mode. BUG=b:177233017 TEST=Update SPI speed in existing binary. See that SPI speed has changed. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I905a9fd8bd93a28aab927dffecbbcf24934b9e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56644 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08sconfig: Ensure at least one `device` node below each `chip`Nico Huber
Even though `device` entries are children of `chip` entries in the devicetree source format, the chips in the translated C structures are only hooked up to device nodes. Hence, any chip with all its settings will be silently dropped by sconfig if there is no device node below it. Let's adapt the parser to ensure that there is at least one `device` entry. The intermediate `chipchildren_dev` rule applies until the first `device` entry is found, then everything continues as before with the `chipchildren` rule. Change-Id: I54830bc1fc7d00a0605f3fe4d36a83ef57ef3312 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51119 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06autoport: search for the HDA device on PCHIru Cai
Haswell has its Mini-HD device and is at card0, so we need to search for the PCH HD Audio device instead of using card0. Change-Id: I2bc420fdbe9731ae835f63add85db79f04201da4 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06inteltool: Support dumping IOBP register valuesIru Cai
This patch also adds LynxPoint and WildcatPoint-LP IOBP registers, which is used to get the USB and SATA configuration values for autoport. Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41473 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-05utils/abuild: select FSP_USE_REPO instead of ADD_FSP_BINARIESFelix Held
Like USE_AMD_BLOBS and USE_QC_BLOBS in the case of the AMD and Qualcomm repos, FSP_USE_REPO controls if the Intel FSP repo will get checked out and will be available during the Jenkins runs. ADD_FSP_BINARIES will get selected in drivers/intel/fsp2_0/Kconfig when FSP_USE_REPO is selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I72faa6f9e5f2b06ab7cd43595ae0b49bf4d39630 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-03util/liveiso: Add NixOS configs for bootable live systemsFelix Singer
Add NixOS configurations for bootable live systems containing a set of tools which might be useful for firmware development in general and for working on coreboot. There are two configurations provided. One for console-only and a graphical one, which is mostly the same as the console image but it comes with Gnome Shell as window manager and some graphical tools in addition. An image can be built using `build-console.sh`, respectively `build-graphical.sh`. The resulting iso image can be found in `result/iso/`. The console image results in ~700MB, while the graphical one results in ~2GB. Change-Id: Iaf49d198e99781434bd89d2a8a125a4988b77e1c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-09-02util/cbftool: Fix the bug in parsing Uefipayload with extended headerDun Tan
The patch is to fix "Not a usable UEFI firmware volume" issue when creating CBFS/flash image. This issue is caused by adding FvNameGuid in UefiPayloadEntry.fdf in EDKII. There is an ext header between header of Fv and header of PayloadEntry in Fv with FvNameGuid. The ext header causes the UefiPayloadEntry to be found incorrectly when parsing Fv. Commit in EDKII: 4bac086e8e007c7143e33f87bb96238326d1d6ba Bugzila: https://bugzilla.tianocore.org/show_bug.cgi?id=3585 Signed-off-by: Dun Tan <dun.tan@intel.com> Change-Id: Id063efb1c8e6c7a96ec2182e87b71c7e8b7b6423 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57296 Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01util/sconfig: Compare probe conditions for override device matchFurquan Shaikh
When the override functionality looks for device match, check that the probe list for both the devices matches exactly if probe list exists for the base device. This ensures that if there are two devices with same identity (e.g. I2C address or USB port #) but using different properties (registers) controlled by different probe statements, then the two devices are not incorrectly matched as the same device. The check for base device having a probe list is performed before comparing the probe lists because a base device might not really have any probe requirements at all. So, when overriding such a device, there is no need to check for the probe list match. BUG=b:187193527 TEST=Verified by adding two I2C devices in the override tree with the same I2C address and chip but different probe statements and confirmed that both the devices are present in generated static.c file. Change-Id: Ib18868b336cf4ffc9aa38aee7c6f333a35d32fce Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-31cbfstool: add buffer_end() to common.hRicardo Quesada
Add buffer_end() function to common.h. This function returns a pointer to the end of the buffer (exclusive). This is needed by elogtool util. (See the next CL in the chain). BUG=b:172210863 Change-Id: I380eecbc89c13f5fe5ab4c31d7a4fef97690a791 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-31amdfwtool: Add flag for multi FW level to the struct amd_cb_configZheng Bao
This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-31amdfwtool: Copy string in a safer wayZheng Bao
The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-17inteltool: Allow to set cores range for MSRs dumpMaxim Polyakov
Adds the ability to output MSRs dump for the specified range of CPU cores. This makes it easier to reverse engineer server multicore processors using the inteltool utility. The range is set using --cpu-range <start>[-<end>] command line option: $ sudo ./inteltool -M --cpu-range 0-7 $ sudo ./inteltool -M --cpu-range 7-15 $ sudo ./inteltool -M --cpu-range 32 $ sudo ./inteltool -M will print a register dump for all cores, just as before. Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35919 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16crossgcc: upgrade Expat from 2.2.9 to 2.4.1Mackenzie May
Versions of expat before 2.4.0 have been renamed to prevent their use, due to some kind of vulnerability. without updating this dependency it is currently not possible to build crossgcc with GDB. Change-Id: Iec2cf560902dc556a41206d7dcd65c22cf3e1215 Signed-off-by: Mackenzie May <ky0ko@disroot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56868 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13util/mb/google: add template files for guybrushBhanu Prakash Maiya
Create template for guyrbsuh variant creation. BRANCH=none BUG=b:194031783 TEST=n/a Change-Id: If62c1a63d0890539d4b43f840f75ee9d7ceab4f8 Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-08-09util/spd_tools/lp4x: Update READMETim Wawrzynczak
The lp4x spd_tools also support Alder Lake (ADL), so update the the README to reflect this fact. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iedb1ea1c3558e5f179feac2c725667db5b327b2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-09elogtool: add to gitignoreJack Rosenthal
Add the binary output of the new elogtool to the .gitignore, so that running "make -C util/cbfstool" keeps the tree clean. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I806338a4b33abbc3d55e4edef2736c19d56fa005 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Quesada <ricardoq@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-06util/kconfig: detect ncurses on FreeBSDIdwer Vollering
Even though pkg-config might be installed, it might or will not return true in the checks whether 'PKG' or 'PKG2' is installed. Extend the script to look in another location for ncurses.h Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-05util/elogtool: add tool to print elog eventsRicardo Quesada
Add a new tool that that prints elog events. The tool, as input, accepts either a file with the RW_ELOG contents, or if the file is not provided it reads the contents of RW_ELOG by calling the "flashrom" tool. The tool is based on "mosys eventlog list"[1]. For the moment it only supports "list", but future commits will add additional functionality. This commit also adds missing ELOG defines needed for the tool. These defines are added with the rest of the ELOG defines, in include/commonlib/bsd/elog.h The tool is placed inside util/cbfstool. The rationale behind the decision, is that this tool shares a lot in common with the other tools located in cbfstool: vboot dependency, shared files like common.o and valstr.o, and in spirit is similar to some of the tools located in cbfstool/. As an example, you call the tool like the following: $ elogtool list -f rw_elog_dump.bin [1]: https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/lib/eventlog/elog.c BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ia1fe1c9ed3c4c6bda846055d4b10943b54463935 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2021-08-05util/kconfig: Provide default for DEFCONFIGPatrick Georgi
Our documentation claims that the DEFCONFIG make variable, used for targets such as savedefconfig, defaults to 'defconfig'. With the update to kconfig 5.13 we lost this default, so bring it back. Fixes: 53ea1d44f0 ("util/kconfig: Uprev to Linux 5.13's kconfig") Resolves: https://ticket.coreboot.org/issues/317 Change-Id: Idb88b69ffa855fa97df8c821601308e717575550 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56718 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28util/xcompile: Allow overriding default compiler pathPatrick Georgi
When looking for C compilers, xcompile uses the "" prefix to "gcc" and "clang" as a last-resort option. This fails in environments where such default names are blocked to prevent "unclean" builds - such as Chrome OS. Allow overriding this prefix using the GENERIC_COMPILER_PREFIX variable that is hopefully both descriptive enough to suggest what it is for and unusual enough to not trigger by chance. Change-Id: I16239f66730f1dbcb7482f223cea4ee5957af10c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-28util/spd_tools/lp4x: Add new memory parts and generate SPDsDavid Wu
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for ADL: 1. H54G46CYRBX267 2. H54G56CYRBX247 3. K4U6E3S4AB-MGCL 4. K4UBE3D4AB-MGCL BUG=b:194686484 b:194765811 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-17util/cbfstool: Remove unused pagesize parameterArthur Heymans
Change-Id: Ib672ba8ed418b1a76e4a48951eabda6923358e7a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55581 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17util/kconfig: Stop trying to make sense of Linux configsPatrick Georgi
It only leads to missing symbol errors. Change-Id: Idbce93232ba2b54561abab5b2747c418d6efa92b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15util/ifdtool: Add APL to IFDv2 platformsSubrata Banik
Initially APL was considered as IFDv2 platform irrespective being added into ifd_2_platforms[], hence commit hash 621ed4c had migrated APL into IFDv1 which break its FLMSTR1/FLMSTR2/FLMSTR3 Read/Write access. This change adds APL into the list of IFDv2 platforms to fix booting issue on the LeafHill board. Change-Id: Ied59ddb2fe05b421266a6b119fd6eab17b8beedc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56300 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rick Lee <rick.lee@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14Revert "amdfwtool: Use relative address for EFS gen2"Kangheui Won
This reverts commit 0fc87e31e0b9ad15dd199fe96189a2ade6abf240. Reason for revert: Breaks psp_verstage in guybrush BUG=b:182477057 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14util/sconfig: Remove unused devicetree keywords ESPI & LPCMartin Roth
The ESPI & LPC keywords were added for the zork program, but it was found that they weren't needed, so they were never used. BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3a78afc55477d62eac8056e2ca4bcdd3ab12ea47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56197 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13util/kconfig: Uprev to Linux 5.13's kconfigPatrick Georgi
This was originally several commits that had to be squashed into one because the intermediate states weren't able to build coreboot: - one to remove everything that wasn't our own code, leaving only regex.[ch], toada.c, description.md and Makefile.inc. - one to copy in Linux 5.13's scripts/kconfig and adapt Makefile.inc to make the original Makefile work again. - adapt abuild to use olddefconfig, simplifying matters. - apply patches in util/kconfig/patches. - Some more adaptations to the libpayload build system. The patches are now in util/kconfig/patches/, reverse applying them should lead to a util/kconfig/ tree that contains exactly the Linux version + our own 5 files. Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-13util/abuild: Fix overriding results with the default configurationArthur Heymans
I a file in configs/* has no suffix, then the default configuration will override the results of the build generated by the configfile from configs/*. Fix this by adding a '_' to the buildname. Change-Id: Ic47105fafca41f1905a6569943079623bec5405a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-08amdfwtool: Fix the NULL pointer in parametersZheng Bao
Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08amdfwtool: Use relative address for EFS gen2Zheng Bao
The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. Chips like Cezanne can run in both cases, so no problem comes up so far. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-07util/ifdtool: Add sklkbl to IFDv2 platformsJan Tatje
Currently ifdtool breaks the descriptor because it treats it as IFDv1. This change adds it to the list of IFDv2 platforms. Fixes boot for X11SSH-LN4F. Fixes: 8c082e5fef ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset") Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594 Signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56070 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05util/board_status: Do not display grep messagePaul Menzel
Redirect stdout and stderr from grep to check for unknown timestamps, when no timestamps are stored, which is already logged earlier. Failed to run "/root/coreboot/util/cbmem/cbmem -t", ignoring Getting remote dmesg grep: /tmp/coreboot_board_status.dXmbUIBP/emulation/qemu-i440fx/4.14-876-gdb28040ee1/2021-07-02T23_14_33Z/coreboot_timestamps.txt: No such file or directory Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-02util/cbfstool: Allow setting alignment for payloadRaul E Rangel
The -a flag was already implemented, it just wasn't exposed for the add-payload command. Setting the alignment of the payload will enable using the SPI DMA controller to read the payload on AMD devices. BUG=b:179699789 TEST=cbfstool foo.bin add-payload -a 64 ... Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02util/intelp2m: use import once for all included modulesMaxim Polyakov
There is no need to repeat "import" for each module in GoLang. Use this keyword only once in each file for code cleanliness. Change-Id: Ibb24fafd409b31b174946a39ca1f810d59b87e76 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55985 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01cbfstool/cbfs-mkstage.c: Change signature of parse_elf_to_xip_stage()Arthur Heymans
The dereferced parameter is never updated so passing a copy would work too. Change-Id: Ie36f64f55d4fc7034780116c28aaed65aa304d5e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55792 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28security/intel/cbnt: Build test CBnT provisioningArthur Heymans
This updates the intel-sec-tools submodule pointer to include a fake acm binary to be included for buildtesting. Change-Id: Id4a9e177f71306b8c5538a578da229a53d19487a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-26cbfstool: Unset ${DEBUG} when making vboot hostlibNico Huber
Vboot's Makefile is controlled by a ${DEBUG} environment variable. As the name is very generic, it may be set by accident without any intention to change the build. Having it set would break reproduci- bility at least but it also turns out that the hostlib build would be incomplete so that linking cbfstool fails due to internal calls to vb2api_fail() which is not built in. Change-Id: I2a9eb9a645c70451a320c455b8f24bfed197117c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-26util/ifdtool: Add Xeon SP Lewisburg PCH platform support under IFDv2Johnny Lin
After commit 8c082e5fe (util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset) w/o this xeon_sp/cpx would be detected as IFDv1 and see build error. Fixes: 8c082e5fe ("util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset") Change-Id: I444e7d35a85d9d42fc25d654e57386f38cf1ec85 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-25cbfstool: Make use of spurious null-terminationNico Huber
The null-termination of `filetypes` was added after the code was written, obviously resulting in NULL dereferences. As some more code has grown around the termination, it's hard to revert the regression, so let's update the code that still used the array length. This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read) which actually did fix something, but only one path while it broke two others. We should be careful with fixes, they can always break something else. Especially when a dumb tool triggered the patching it seems likely that fewer people looked into related code. Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-22docker/coreboot.org-status: Update URL schemes to git reposPatrick Georgi
We moved from gitweb to cgit to gitiles and some of the URL schemes were lost during the transitions. Update to the gitiles scheme so board-status links work again. Change-Id: Id2a840bf89fab172e0eab21e303ac0c4666b6751 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-06-20util/ifdtool: Use ICH Strap Length (ISL) to identify APL chipsetSubrata Banik
Use offset FLMAP1 bit 24:31, called ISL (ICH Strap Lenth) to uniquely identify the chipsets without any additional logic. +---------+-----------+ | Chipset | PSL Value | +---------+-----------+ | APL | 0x13 | +---------+-----------+ BUG=b:153888802 TEST=Able to dump FD contains correctly without specifying platform quirks on APL (IFDv1) Platform. > ifdtool -d coreboot.rom PCH Revision: Apollo Lake: N3xxx, J3xxx Change-Id: I02bcc6b1ca61c4ee59582f1b310ed0fba0ef1d9a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-20util/ifdtool: Use -p platform name to detect IFDv2 platform and chipsetSubrata Banik
ifdtool uses `chipset` information to determine how certain straps are decoded. This has been used for IFDv1 platforms as well as IFDv2 platforms (CHIPSET_500_600_SERIES_TIGER_ALDER_POINT). IFDv2 platforms are all expected to pass in `-p` argument to identify the platform. This platform information can be used to identify the appropriate chipset information. For IFDv1 since `-p` argument is not provided, ifdtool needs to use certain fields in the descriptor (e.g. strap length) for unique identification of IFDv1 chipset. This change updates `check_ifd_version()` function to: 1. Determine if IFD version is v1 or v2 based on `-p` argument. If `-p` is not provided, it assumes that the platform is using IFDv1. 2. Based on IFD version, it calls either `ifd2_platform_to_chipset()` or `ifd1_guess_chipset()` to determine chipset information. This fixes the issue reported with CB:44815, where ifdtool is unable to identify Alder Lake chipsets. BUG=b:153888802 TEST=Able to dump FD contains correctly with platform quirks on Brya Platform. > ifdtool -d coreboot.rom -p adl PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54305 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18util/ifdtool: Add Elkhart Lake platform support under IFDv2Lean Sheng Tan
Add EHL under same family tree as TGL & JSL, also fix a spacing inconsistency line. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ice09861c104c4e339fc83631c75089fa069b3931 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16util/intelp2m/fsp: Update some deprecated macrosBenjamin Doron
Avoid using deprecated macros, where possible. "GpioResetPwrGood" represents multiple valid updated values, depending on the GPIO community and will be more difficult to update. While Kabylake supports both sets of macros, it will cause build errors on Coffeelake. In the GPD group, replace with "GpioDswReset." Replace with "GpioResumeReset" in any GPP group. Change-Id: Iab0bb09adad997bef3a2133c443471d4c634f423 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2021-06-15treewide: Disable R_AMD64_32S relocation supportPatrick Rudolph
This fixes a hard to debug hang that could occur in any stage, but in the end it follows simple rules and is easy to fix. In long mode the 32bit displacement addressing used on 'mov' and 'lea' instructions is sign-extended. Those instructions can be found using readelf on the stage and searching for relocation type R_X86_64_32S. The sign extension is no issue when either running in protected mode or the code module and thus the address is below 2GiB. If the address is greater than 2GiB, as usually the case for code in TSEG, the higher address bits [64:32] are all set to 1 and the effective address is pointing to memory not paged. Accessing this memory will cause a page fault, which isn't handled either. To prevent such problems - disable R_AMD64_32S relocations in rmodtool - add comment explaining why it's not allowed - use the pseudo op movabs, which doesn't use 32bit displacement addressing - Print a useful error message if such a reloc is present in the code Fixes a crash in TSEG and when in long mode seen on Intel Sandybridge. Change-Id: Ia5f5a9cde7c325f67b12e3a8e9a76283cc3870a3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-14amdfwtool: Null check the pointers before using themZheng Bao
BUG=b:188769922 Reported-by: Coverity (CID:1438963) Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14util: Add DDR4 generic SPD for MT40A512M16TB-062E:RWisley Chen
Add SPD support for DDR4 memory part BUG=b:190020997 TEST=none Change-Id: I423131cb674e1e5ec699c7a28e5b5e6746247b2a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55164 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-12util/intelp2m/fsp: Fix wrong register decoding for direction and interruptBenjamin Doron
Using the wrong registers to build the fields led to incorrect GPIO direction and interrupt trigger values. Change the calls to fix the tables. Change-Id: Icbeeb1fec6a863d0f86659c21924e15ae6765d47 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54973 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-09amdfwtool: Add missing license headerZheng Bao
Change-Id: Id466e733d421602cfe0403ead95e417f0bb37eb4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-09amdfwtool: Move EFS related definitions to header fileZheng Bao
EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-08lint: checkpatch: Add SUSPICIOUS_CODE_INDENT testJulius Werner
This patch adds a new test to checkpatch that identifies cases where a line after a conditional statement is incorrectly intended (possibly indicating the mistake of forgetting to add braces), like this: if (a) b; c; Unfortunately, it seems like checkpatch is partially unmaintained in upstream Linux at the moment with maintainers either not responding at all or not even willing to look at new patches [1]. Since detecting this error class is important to coreboot, let's just carry this feature locally for now. [1] https://lkml.org/lkml/2021/4/15/1488 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I7bb90b56dfc7582271d2b82cb42a2c1df477054f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-07amdfwtool: Print the entry type when dumping the firmwaresZheng Bao
Change-Id: I07bf10e16a42a2b2ab784ee6ac4a4465b7412da6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07amdfwtool: Set the region_type as 0 for entry "BIOS level 2"Zheng Bao
This region_type is actually not used. But we need to set it explicitly as a known value. We can refer "PSP spec #55758" or the link below: https://doc.coreboot.org/soc/amd/psp_integration.html Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-07sb/intel/bd82x6x: Drop P_LVLx support in FADTAngel Pons
IO MWAIT redirection is not enabled, and C-states are reported using the _CST ACPI object, which overrides the P_LVLx values. Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-06util/crossgcc: Avoid complex filename setsPatrick Georgi
bin/{foo,bar,baz} can fail if one of the files doesn't exist (depending on the shell in use). Instead, cd into the directory and list the files individually. Change-Id: I042b2e45fded1b63551d8e65ead2a7bbbf96b1e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-06util/crossgcc: Update to clang 12Patrick Georgi
Change-Id: I38fc64fa872e2ecb0a10fb5378b3ce0d6a02443c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-04Revert "util/vboot_lib: Add description.md"Angel Pons
This reverts commit 255b6f8646903594fb728f8228908792bad766f0. No longer needed after commit dd01e0131a8ba901bedec48844502fe85663390a (Revert "util/lint: Add test for documentation in util dirs") has been submitted. Plus, `util/vboot_lib/description.md` gets deleted whenever one runs `make -C util/cbfstool clean`, which is rather annoying. Change-Id: Ic93da096b6186d1d2af12243a74ec597694960c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55162 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04util/cbfstool/linux_trampoline.h: Fix typo in commentAngel Pons
inlucde ---> include Change-Id: I38987119ddabb08c457c9a7c8aecb8025fe2d9d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55161 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 configAmanda Huang
CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config") incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2. This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2. BUG=b:186616388 Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-02cbfstool/linux_trampoline.S: Fix up the e820 tableArthur Heymans
The e820 type don't fully match the LB_TAG_MEMORY types, so change all unknown types to e820 to '2', reserved memory. TESTED with Linuxboot: e820 now shows the CBMEM region as reserved. Change-Id: Ie0e41c66e002919e41590327afe0f543e0037369 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55074 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Rocky Phagura Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-01mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-01soc/amd/picasso: introduce and use chipset device treeFelix Held
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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