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authorFelix Held <felix-coreboot@felixheld.de>2021-05-31 19:44:46 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-06-01 20:37:15 +0000
commit4fbab545b2a99407ff444a29730c443aee4f24db (patch)
treebd256e2e0a4f76cf7af09a55e17c33c3be4a646f /util
parentc4eb45fa85d9860ce94829c6c977b9e28a297bf9 (diff)
mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'util')
-rw-r--r--util/mainboard/google/trembyle/template/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/util/mainboard/google/trembyle/template/overridetree.cb b/util/mainboard/google/trembyle/template/overridetree.cb
index d09c942296..52607d14c9 100644
--- a/util/mainboard/google/trembyle/template/overridetree.cb
+++ b/util/mainboard/google/trembyle/template/overridetree.cb
@@ -37,7 +37,7 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
- device pci 1.7 on end # GPP Bridge 6 - NVME
+ device ref gpp_bridge_6 on end # NVME
end # domain
device mmio 0xfedc4000 on end