Age | Commit message (Collapse) | Author |
|
- Improve description a bit, especially wrt chip packages and
protocols.
- Add some missing parameters to manpage option descriptions.
- Remove long obsolete DoC support note.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Tested on an iWILL DK8-HTX board.
Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4086 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4083 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
romtool by changing the Makefiles to be no longer recursive (once again,
recursive make is to be considered harmful). Tried to (quickly) unify most of
the Makefile code, but medium-term this is going to be worked on for Kconfig
support anyways.
Also fix a sign cast error in rom-mkpayload in case people want to compile this
with -W -Werror
Patch relative to coreboot-v2/util/romtool
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
and
Acked-by: Stefan Reinauer <stepan@coresystems.de>
in order to get the tree working decently asap
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
(coreboot.org build system internal)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
romtool is still built in util/romtool, as happens without this patch.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4061 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
issues (see buildbot).
The romfs image was always built, and sometimes broke (because of
the different image layouts) for buildrom images. After the patch, these
issues are avoided by not adding payloads to the romfs image (they
wouldn't be read anyway). Both workarounds (in buildrom code for
romfs and vice-versa) aren't very pretty, but that's what our buildsystem
requires.
As I had to create a "communication channel" (via the romfs-support
files), I took the chance to also use it for compression
information, so if you configure lzma support, you'll get lzma
compressed payloads in romfs.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
The compile_file calls seem to be in the wrong order, but
romcc actually requires it that (probably some stack-like
file processing)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
romfs.
Everything else to make a target romfs aware happens in the targets.
What the patch does:
1. missing romfs.h include
2. special handling while creating coreboot.rom
While the romfs code path in the makefile doesn't actually use the file,
it's possible that the build of coreboot.rom fails in a romfs setup,
because the individual buildrom image is too small to host both coreboot
and payloads (as the payloads aren't supposed to be there). Thus, a
special case to replace the payload with /dev/null in case of a romfs
build.
There would be cleaner ways, but they're not easily encoded in the
Config.lb format.
3. config.g is changed to create rules for a romfs build
Targets should still build (they do for me)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
I've attached a patch that removes the 3-mile-long compiler
commandlines, which vim's quickfix doesn't like so much. Instead of
putting all those -DXYZ='bla' on the compiler commandline, they are put
in a file called settings.h (as #define XYZ bla) and only a
--include=settings.h is put on the commandline.
This file is created unconditionally at the same time as when the
CPUFLAGS simply expanded make variable used to be created (not via a
target rule and dependency), so it shouldn't change anything.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
There are a few changes. The 20K bootblock size restriction is gone.
ROMFS has been tested and works on v2 with qemu and kontron. Once this
patch is in, those patches will follow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
This is a BCM5785 based machine, WP# and TLB# need to be deasserted using
GPIO 2 and 5 from the PM registers of the southbridge.
This is very similar to the x3455 implementation.
Signed-off-by: Mondrian Nuessle <nuessle@uni-hd.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- Add missing contributor in README.
- Cosmetic fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
strtoul() conversion result.
Thanks to Mart for finding and reporting the problem!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
the struct to the individual struct members to improve readability.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.
By moving the table to the high tables area (if it's activated), this problem
is fixed.
In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.
This patch also adds "table forward" support to flashrom and nvramtool.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Some bootloaders seem to overwrite memory starting at 0x600, thus destroying
the coreboot table integrity, rendering the table useless.
By moving the table to the high tables area (if it's activated), this problem
is fixed.
In order to move the table, a 40 bytes mini coreboot table with a single sub
table is placed at 0x500/0x530 that points to the real coreboot table. This is
comparable to the ACPI RSDT or the MP floating table.
This patch also adds "table forward" support to flashrom and nvramtool.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Add support for clang's scan-build utility to abuild. scan-build wraps
the compiler and runs its own compiler on the same sources to do some
static analysis on them. It adds an option "-sb" or "--scan-build" that
creates a coreboot-builds/$target-scanbuild directory for every $target,
containing the output of scan-build, which is a HTML documentation on
its results.
Be aware, that scanbuild significantly increases build time: A board
that takes 6-7 seconds normally requires 60 seconds with that option
enabled on my test system.
The patch also moves the stack-protector option down a bit, so it
applies to crosscompiled targets, too (which overwrote the compiler
settings before)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
- add configure only mode to easily and quickly check Config.lb and Option.lb
files
- fix up cross compiler handling
- don't use in-place sed, not all sed versions can do it
- use perl instead of date to avoid non-gnu date trouble
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Fix bash script type.
Removed const return type on msraddrbyname() to fix gcc warning/error.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
attempt trickery, we can simply rename the accessor functions.
Patch created with the help of Coccinelle.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Idwer Vollering <idwer_v@hotmail.com>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3984 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
spotted assignments to volatile variables which were neither placed
inside the mmapped ROM area nor were they counters.
Due to the use of accessor functions, volatile usage can be reduced
significantly because the accessor functions take care of actually
performing the reads/writes correctly.
The following semantic patch spotted them (linebreak in python string
for readability reasons, please remove before usage):
@r exists@
expression b;
typedef uint8_t;
volatile uint8_t a;
position p1;
@@
a@p1 = readb(b);
@script:python@
p1 << r.p1;
a << r.a;
b << r.b;
@@
print "* file: %s line %s has assignment to unnecessarily volatile
variable: %s = readb(%s);" % (p1[0].file, p1[0].line, a, b)
Result was:
HANDLING: sst28sf040.c
* file: sst28sf040.c line 44 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 43 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 42 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 41 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 40 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 39 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 38 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 58 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 57 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 56 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 55 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 54 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 53 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
* file: sst28sf040.c line 52 has assignment to unnecessarily volatile
variable: tmp = readb(TODO: Binary);
The following semantic patch uses the spatch builtin match printing
functionality by prepending a "*" to the line with the pattern:
@@
expression b;
typedef uint8_t;
volatile uint8_t a;
@@
* a = readb(b);
Result is:
HANDLING: sst28sf040.c
diff =
--- sst28sf040.c 2009-03-06 01:04:49.000000000 +0100
@@ -35,13 +35,6 @@ static __inline__ void protect_28sf040(v
/* ask compiler not to optimize this */
volatile uint8_t tmp;
- tmp = readb(bios + 0x1823);
- tmp = readb(bios + 0x1820);
- tmp = readb(bios + 0x1822);
- tmp = readb(bios + 0x0418);
- tmp = readb(bios + 0x041B);
- tmp = readb(bios + 0x0419);
- tmp = readb(bios + 0x040A);
}
static __inline__ void unprotect_28sf040(volatile uint8_t *bios)
@@ -49,13 +42,6 @@ static __inline__ void unprotect_28sf040
/* ask compiler not to optimize this */
volatile uint8_t tmp;
- tmp = readb(bios + 0x1823);
- tmp = readb(bios + 0x1820);
- tmp = readb(bios + 0x1822);
- tmp = readb(bios + 0x0418);
- tmp = readb(bios + 0x041B);
- tmp = readb(bios + 0x0419);
- tmp = readb(bios + 0x041A);
}
static __inline__ int erase_sector_28sf040(volatile uint8_t *bios,
It's arguably a bit easier to read if you get used to the leading "-"
for matching lines.
This patch was enabled by Coccinelle:
http://www.emn.fr/x-info/coccinelle/
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Joseph Smith <joe@settoplinux.org>
--
http://www.hailfinger.org/
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Right now we perform direct pointer manipulation without any abstraction
to read from and write to memory mapped flash chips. That makes it
impossible to drive any flasher which does not mmap the whole chip.
Using helper functions readb() and writeb() allows a driver for external
flash programmers like Paraflasher to replace readb and writeb with
calls to its own chip access routines.
This patch has the additional advantage of removing lots of unnecessary
casts to volatile uint8_t * and now-superfluous parentheses which caused
poor readability.
I used the semantic patcher Coccinelle to create this patch. The
semantic patch follows:
@@
expression a;
typedef uint8_t;
volatile uint8_t *b;
@@
- *(b) = (a);
+ writeb(a, b);
@@
volatile uint8_t *b;
@@
- *(b)
+ readb(b)
@@
type T;
T b;
@@
(
readb
|
writeb
)
(...,
- (T)
- (b)
+ b
)
In contrast to a sed script, the semantic patch performs type checking
before converting anything.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: FENG Yu Ning <fengyuning1984@gmail.com>
Tested-by: Joe Julian
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3971 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
caused same filenames to still cause objects being dropped from the build list
- which was the whole purpose of the patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
similar to what v3 does. This is required to have two source files with
the same name but in different directories. (As in, two different SuperIOs on
board, with a superio.c each)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Report by Holger Mickler. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and
mainboard_$VENDOR_$BOARD_config to mainboard_config.
Ron's part:
The config change that makes the naming change not break every build.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Elan SC520 requries us to deal with flash chip base addresses at locations
other than top of 4GB. The logic for that was incorrectly triggered also when
a board had more than one flash chip. This patch will honor flashbase only when
probing for the first flash chip on the board, and look at top of 4GB for later
chips.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: David Tiemann <davidtiemann@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
initialized same way as ICH7.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Thanks for the idea Mart!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Thanks to Mart for spotting this!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Thanks Patrick!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Test report from Julia. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Julia Longtin <juri@solarnetone.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3916 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3914 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
SST AAI is Auto Address Increment writing, a streamed write to the flash chip
where the first write command sets a starting address and following commands
simply append data. Unfortunately not supported by Winbond SPI masters.
From July 2008.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3912 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Developed and tested to work on Intel D201GLY in July 2008.
Tested by a helpful person on IRC whose name I've since forgotten. Sorry!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Through DirectIO from coresystems GmbH we now support Darwin/Mac OS X.
DirectIO is available at http://www.coresystems.de/en/directio
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
physmap() call.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
The function exit()s on failure, and no callers check the return value.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
As reported by Jody McIntyre. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Report by Jody McIntyre. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Report by Scaldov M.V. Thanks!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
resolves #121
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
parts.
This should help to reduce the code duplication for Rudolf's K8/VIA SMM
implementation...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: FENG yu ning <fengyuning1984@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
board_pciid_enables more readable.
Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr>
> What real problem does this solve?
1. Next time someone adds a new struct member, we avoid mistakes of
ordering of initializers
2. we avoid mistakes in the first place.
The .x = y stuff was added for a (good) reason, I think this is an
improvement.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge.
The board uses GIGABYTE's patented BIOS failover technology, and at this point
we do not know how to control which of the two chips flashrom actually hits.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Fix build error on distros with warn_unused_result attributes in glibc.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Yul Rottmann <yulrottmann@bitel.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Mimicked from flashrom.c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
AT25DF021 AT25DF041A AT25DF081 AT25DF161 AT25DF321 AT25DF321A AT25DF641
AT25F512B AT25FS010 AT25FS040 AT26DF081A AT26DF161 AT26DF161A AT26DF321
AT26F004
Straight from the data sheets, untested because I lack the hardware.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
incorrect license section.
- Remove the copyright listings and refer the reader to the source
files.
- Update the author list to those which have copyright messages in the
source files.
- Correct the license from GPL v2+ to (GPL v2, with some files under
later versions as well)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
flashchips.c over what's currently in flashrom HEAD.
The explicit initialization makes sure any future struct flashchip
reordering is not needed. (Except for the case where we need arrays
of some of the struct members.)
Signed-off-by: Stephan Guilloux <mailto:stephan.guilloux@free.fr>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Fix that by throwing an error instead.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
There seem to be at least two versions of the board out there, and the
subsystem IDs changed between the versions.
Patch successfully tested on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
used for a SIR/FIR device.
Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Ulf Jordan <jordan@chalmers.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
* rename ich_check_opcodes to ich_init_opcodes.
* let ich_init_opcodes do not need to access flashchip structure:
. move the definition of struct preop_opcode_pair to a better place
. remove preop_opcode_pairs from 'struct flashchip'
. modify ich_init_opcodes and generate_opcodes so that they do not access the flashchip structure
* call ich_init_opcodes during chipset enable. Now OPCODES generation mechanism works.
* fix a coding style mistake.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
support the MX29LV040C.
MX29LV040C probe and read support tested by khetzal on IRC.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
configuration is locked down.
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Signed-off-by: FENG yu ning <fengyuning1984@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
Looks like this:
Supported flash chips: Tested OK operations: Known BAD operations:
AMD Am29F002(N)BB
AMD Am29F002(N)BT PROBE READ ERASE WRITE
AMD Am29F016D
AMD Am29F040B PROBE READ ERASE WRITE
AMD Am29LV040B
Atmel AT45CS1282 READ
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|
|
This patch adds SB700 support to flashrom. The code for enabling the flash
rom is the same as for SB600. It was tested (read, write, verify) with an
ASUS M3A-H/HDMI which contains a Macronix MX25L8005.
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
|