summaryrefslogtreecommitdiff
path: root/util
AgeCommit message (Collapse)Author
2019-05-13util/intelvbttool: Add error checking for memory allocationJacob Garber
It is possible that 'malloc_fo_sub' and 'remalloc_fo' can fail, so add appropriate error checks for those cases. This incidentally fixes a possible memory leak when 'malloc_fo_sub' succeeds but 'remalloc_fo' does not. Found-by: Coverity Scan #1396050 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/intelvbttool: Free file object on error pathJacob Garber
Prevents a memory leak. Found-by: Coverity Scan #1396047 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/ifdtool: Add find_fd null checkJacob Garber
As the previous comment indicated, this null check is currently superfluous, but adding it in makes Coverity happy, and future-proofs the code in case someone changes the internals of 'find_fcba' later and forgets/doesn't know to update this error check. Found-by: Coverity Scan #1395066 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-09vboot: include vb2_sha.h when requiredJoel Kitching
Should include vb2_sha.h header when SHA library functions or constants are required. This replaces NEED_VB2_SHA_LIBRARY. BUG=b:124141368, chromium:956474 TEST=make clean && make test-abuild BRANCH=none Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368 Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:1583820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-07{src,util}: Remove duplicated includesElyes HAOUAS
Change-Id: Id09cec6b2aae58b131b208e96fec539d068ff68a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07sconfig: Add SMBIOS type 9 entriesPatrick Rudolph
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments. The field is valid for PCI devices and only compiled if SMBIOS table generation is enabled. smbios_slot_desc arguments: 1. slot type 2. slot lenth 3. slot designation (optional) 4. slot data width (optional) Example: device pci 1c.1 on smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8" end # PCIe Port #2 Integrated Wireless LAN Tested on Lenovo T520. Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-06inteltool: Add Sunrise Point-LP Skylake PCH IDsFelix Singer
Sunrise Point-LP is used on Skylake and KabyLake platforms, but the PCH IDs differ. This commit adds the PCH IDs for Skylake mobile platforms and renames the Kabylake macros to distinguish them. Used Intel documents: - 332995-001EN (I/O datasheet vol. 1) - 332996-002EN (I/O datasheet vol. 2) Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6 Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-03sdm845: Combine BB with QC-Sec for ROM bootT Michael Turney
TEST=build & run Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-24util/sconfig: Throw an error if override tree has no devicesFurquan Shaikh
If override tree does not have any device, then the chip info structure in it cannot be associated with the correct device and ends up being added as a standalone chip info structure without any device actually using it. This change prevents this condition by throwing an error during compilation. BUG=b:130342895 Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-04-23cbfstool: Fix cbfs_file_next_attrPatrick Rudolph
The last attribute was never returned. Fix size compare to retrieve all attributes. Manually tested and seen all attributes, including the last one. Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23crossgcc: Update acpica to version 20190215Elyes HAOUAS
Support for ACPI specification version 6.3: Add PCC operation region support for the AML interpreter. This adds PCC operation region support in the AML interpreter and a default handler for acpiexec. The change also renames the PCC region address space keyword to PlatformCommChannel. Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG. These methods provide OSPM with health information and device boot status. PDTT: Add TriggerOrder to the PCC Identifier structure. The field value defines if the trigger needs to be invoked by OSPM before or at the end of kernel crash dump processing/handling operation. SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT is used for describing devices such as heterogeneous processors, accelerators, GPUs, and IO devices with integrated compute or DMA engines. MADT: Add support for statistical profiling in GICC. Statistical profiling extension (SPE) is an architecture-specific feature for ARM. MADT: Add online capable flag. If this bit is set, system hardware supports enabling this processor during OS runtime. New Error Disconnect Recover Notification value. There are a number of scenarios where system Firmware in collaboration with hardware may disconnect one or more devices from the rest of the system for purposes of error containment. Firmware can use this new notification value to alert OSPM of such a removal. PPTT: New additional fields in Processor Structure Flags. These flags provide more information about processor topology. NFIT/Disassembler: Change a field name from "Address Range" to "Region Type". HMAT updates: make several existing fields to be reserved as well as rename subtable 0 to "memory proximity domain attributes". GTDT: Add support for new GTDT Revision 3. This revision adds information for the EL2 timer. iASL: Update the HMAT example template for new fields. iASL: Add support for the new revision of the GTDT (Rev 3). More changes in this version at https://acpica.org/node/166 Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23crossgcc: Update CMake to version 3.14.2Elyes HAOUAS
Release Note : https://cmake.org/cmake/help/v3.14/release/3.14.html "The FindFontconfig module added by 3.14.0 accidentally used uppercase FONTCONFIG_* variable names that do not match our conventions. 3.14.1 revises the module to use Fontconfig_* variable names. This is incompatible with 3.14.0 but since the module is new in the 3.14 series usage should not yet be widespread" Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23crossgcc: Upgrade GCC to version 8.3.0Elyes HAOUAS
Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23Klocwork: Fix the Null pointer derefernce found by klocworkThejaswani Putta
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI ↵Robin Broda
devices Signed-off-by: Robin Broda <robin@broda.me> Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-19src/mb/Kconfig: Fix PCI subsystem IDsElyes HAOUAS
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed in commits dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem() 00bb441 sb/intel/lynxpoint: Remove PCI bridge function Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-17util/docker: Update JRE in coreboot-jenkins-node DockerfileMartin Roth
openjdk-8-jre-headless is no longer available in the debian image we're basing the coreboot-sdk off of. Update it to 'default-jre-headless'. Change-Id: I60f6ecbaedccc0da61f96e0bce4122406ba4bd91 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-15util/genbuild_h: Prefer iasl from .xcompile over a hard codePatrick Georgi
build.h provides iasl's version but right now assumes that it's kept in util/crossgcc/xgcc/bin. Often true, but not always, so use the one found in .xcompile to query the version as that's the version that is used in coreboot builds. Change-Id: Iaeedc22e0e14fa96b4f2a68127f405c7f0c9d5cc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-12util/genbuild_h: Allow operation with older git versionsPatrick Georgi
if git log --no-show-signature is not supported, retry without. Change-Id: I9ee1f8e887cde5e4d6c5e6958f269c62572cdd53 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32299 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11util/genbuild_h: Do not print PGP verification results in `git log` outputSergey Alirzaev
Signed-off-by: Sergey Alirzaev <zl29ah@gmail.com> Change-Id: I102ecc79bb649a67661c3d22988453dc7741acda Reviewed-on: https://review.coreboot.org/c/coreboot/+/32129 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11util/inteltool: Swap conditions to prevent uninit readsJacob Garber
Both values in each array are only initialized if `two_channels` is true, so we need to check that first. Found-by: Coverity Scan #1370{584,585,588,589,590-596,600} Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11Documentation: Explain FMAP and FMDHung-Te Lin
The Flashmap (FMAP) was not clearly documented. The new flashmap.md explains where to find more details about that and how / why it was used in coreboot. Also explained what is FMD and how to use it (based on original README.fmaptool). BUG=None TEST=None (only documentation) Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11kconfig_lint: Make uses of CONFIG() on an unknown option an errorJulius Werner
This check had very few false positives which were all easily resolved, and it's unlikely that further false positives will become problematic in the future. On the other hand, it does detect a very severe bug (when you think you're using a Kconfig but you aren't due to a typo), so since warnings are currently not very visible, let's turn this into an error because the pros clearly outweigh the cons for that. Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32257 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09util/docker: Update coreboot-sdk Dockerfile for new debian imageMartin Roth
libssl1.0-dev is no longer available: - Update to libssl-dev - Add libcrypto++-dev to provide additional crypto libraries not available in libssl-dev. Change-Id: Ie10e14ebf7ae849301302008ee6ffeec1f40ccab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-04util/docker: work around toolchain autotools issueMartin Roth
The patches added to `make` require that we use automake & aclocal to rebuild the configuration, but version 1.15 of autotools is expected. After debian sid updated to autotools 1.16, the tools can't be located. We'll just pretend to have version 1.15 with symbolic links. This doesn't seem to be a good solution but gets the job done. Change-Id: I9f616b96e728106e7adf321325caa06808e064c2 Signed-off-by: Martin Roth <martinr@coreboot.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28544 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-03util/arm_boot_tools/mksunxiboot: Correct format stringsJacob Garber
%lx is the right format string for printing longs. Found-by: Coverity Scan, CID 1229686, 1229687 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ib7ab54dc039bdd60969c79f3c881d69fc68f0d2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/32008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-03util/kconfig: Fix missing library issue with ld 2.24 and newerWerner Zeh
When invoking 'make menuconfig' with gcc 4.9.2 an error is thrown: ld: build/util/kconfig/lxdialog/checklist.o: undefined reference to symbol 'acs_map' This happens with ld version 2.24 and newer when menuconfig is executed for the first time after make clean. This does not happen with ld 2.20 (part of gcc 4.4.7). It can be fixed with the flag -ltinfo in HOST_LOADLIBES. Change-Id: I6216bb4d276d4bf98aa4ec06457b809fdcd73235 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-02util/lint: list files with whitespace issuesBalazs Vinarz
Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-01util/spdtool: Add tool to extract SPD from BLOBsPatrick Rudolph
Opens a binary file to extract DDR SPDs using known bits. At the moment only DDR4 SPDs are supported. Dumps the found SPDs into the current folder, as either binary or hex encoded file. Works with python2 and python3. Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-25crossgcc: Upgrade LLVM to 8.0.0Elyes HAOUAS
Change-Id: I80efe90e21947aac631d54fd7983319602fc39c2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-22crossgcc: Update CMake to version 3.14.0Elyes HAOUAS
Change-Id: I9fec45429d80500d80cc6b774718ecc91720f3f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22lint/kconfig: More checks, more errorsJulius Werner
This patch changes a few more Kconfig linter warnings to errors that currently do not show up in the tree and that seem unlikely to become false positive in the future. One instance of duplicated code that essentially checks for the same thing was consolidated. It also adds a new test for references to boolean Kconfig options that do not use the CONFIG() wrapper macro. It's a little flaky (e.g. hard to handle multi-line comments), but it should be helpful the majority of the time as a warning in a Jenkins comment. Change-Id: I975ee77d392ed426f76f7671d9b6ef9441656e6a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-18util/autoport: Rewrite readme.mdAngel Pons
The last part of the file has not been modified much. Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18util/autoport: Trim gfx.did to sizeAngel Pons
Since the values are hardcoded, we might as well hardcode values that make sense. Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18util/autoport: fix default headersAngel Pons
Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-15Revert "lint/clang-format: set to 96 chars per line"Julius Werner
This reverts commit 626ba097a2cd1c87800a2154420829b09803467e. This change was submitted under the incorrect assumption that there was agreement on a coding style change. There wasn't, so while the issue is under discussion we should revert to the previous status quo. Making clang-format honor the line length is a separate issue from changing the line length, and can be reuploaded as a separate CL. Change-Id: I433c82c95a897b3113cace3668cc8ce0f1ab75bf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15inteltool: add 300 and C240 Series PCHThomas Heijligen
Values from - Intel doc 337347 rev4 - coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not accessible. Using a static value instead. 0xfd000000 is a common value chosen by coreboot and non-coreboot firmware. Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8 Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-15util/amdfwtool: Allow 0-length blobsMarshall Dawson
A side effect of the change 8e0dca05 "util/amdfwtool: Add generic image copy function" was to treat a read operation of zero bytes as a failure. Some implementations exist that use zero length files as a means of removing functionality. This causes amdfwtool to exit with an error. Put the zero length capability back in, and generate the requested table entry with a length field of 0x0. TEST=Boot google/grunt, inspect PSP directory table BUG=b:128507639 Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31891 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14util/autoport: remove obsolete symbol SANDYBRIDGE_IVYBRIDGE_LVDSAlexander Couzens
This symbol was removed in a6be58fecec5 ("nb/intel/sandybridge: Remove the C native graphic init") Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: I87801552e1c37162897949ec0db3904f850f0bfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/31823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-13util/autoport: Separate NB and SB PCIe port IDsAngel Pons
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe root ports. Put the latter on sandybridge.go instead, and add missing IDs. Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08lint/kconfig: Update to support new CONFIG() macroJulius Werner
This patch updates the Kconfig linter to support the new CONFIG() macro in the same manner that IS_ENABLED() was previously supported. It will be flagged when it is used on non-bool Kconfigs or used with #ifdef, and it is supported for checking used Kconfigs. Remaining uses of IS_ENABLED() are flagged with a deprecation warning. Change-Id: I171ea8bc8e2d22abab7fc4d87ff4cf8aad21084f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31776 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07intelmetool: Add more flag descriptionsDamien Zammit
Obtained by inspecting intel SPSinfo tool output Change-Id: I69eb0dd86761984b6f0a450b7d8757268b0b248e Author: roncapat Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31589 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07intelmetool: Consolidate all model support from upstreamDamien Zammit
Some of the older chipsets that are known not to have ME at all were removed for some reason, add them back in. Also some newer chipsets/ME models were missing, add them in. Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-07util/amdfwtool: Remove fanless SMU optionsMarshall Dawson
Complete the removal of the fanless command line options. The only soc using them has been converted to use the subprogram option instead. TEST=Verify amdfw.rom is unchanged before and after the conversion BUG=b:126691068 Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Split type field for PSP entriesMarshall Dawson
Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Streamline functions with contextMarshall Dawson
Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Add generic image copy functionMarshall Dawson
Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Combine table header populationMarshall Dawson
Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Remove duplicate PSP2 supportMarshall Dawson
There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 2 of 2 to reduce the number of command-line options to amdfwtool. Part 1 added the --combo-capable option that helps put the PSP directory pointer in the correct location. Part 2 removes the duplicated table, the support code, options, and updates the usage text. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO defined as 1. BUG=b:126691068 Change-Id: I542a7f5023137f30fbe00533452d4448117df487 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Introduce combo-capable optionMarshall Dawson
There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 1 of 2 to reduce the number of command-line options to amdfwtool. Create a new option that is used as an indicator for which Embedded Firmware offset to use. Part 2 will be added once makefiles no longer use the duplicated options. This patch also adds two new options for fanless SMU firmware to be used instead of the ones that will be removed in part 2. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied BUG=b:126691068 Change-Id: I249700c6addad1c0ecb495a406ffe7a022dd920b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Clarify call to fletcher32Marshall Dawson
The fletcher32 algorithm generates a sum over a range of 16-bit WORDs. Change the function's interface to be more generic, accepting a more intuitive size in BYTEs. Don't require the caller to understand the nature of the algorithm and convert to WORDs prior to calling. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07util/amdfwtool: Clarify calculations with structuresMarshall Dawson
Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07util/amdfwtool: Fix iteration of PSP firmwaresMarshall Dawson
Correct an oversight in the utility that attempts to match up eligible PSP directory table entries with blob names passed on the command line. A 1:1 matchup of items shouldn't be assumed, so the i iterator shouldn't be used to walk both lists. This change has no effect on google/grunt (Family 15h Models 70h-7Fh), but eliminates blank entries of all FF's on builds of amd/bettong (F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries also affects the checksum accordingly. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07security/tpm: Fix TCPA log featurePhilipp Deppenwiese
Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-06pci_drivers/cpu_drivers: Fix constructed arrays on x86_64Patrick Rudolph
The __pci_driver and __cpu_driver uses variable length arrays which are constructed by the linker at build-time. The linker always place the structs at 16-byte boundary, as per "System V ABI". That's not a problem on x86, as the struct is exactly 16 Bytes in size. On other platforms, like x86_64 it breaks, because the default data alignment isn't SysV compatible. Set -malign-data=abi to make x86_64 gcc use the SysV psABI. Fixes broken __pci_driver and __cpu_driver on x86_64. Change-Id: I2491d47ed03dcfd8db110dfb181b2c5281449591 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06inteltool: Add multiple device IDs of Intel GPUsFelix Singer
* Intel HD Graphics 510 * Intel HD Graphics 515 * Intel HD Graphics 520 * Intel HD Graphics 530 (2x) * Intel UHD Graphics 615 (2x) * Intel UHD Graphics 617 * Intel UHD Graphics 620 (3x) * Intel UHD Graphics 630 (7x) * Intel UHD Graphics 640 * Intel Iris Graphics 540 * Intel Iris Graphics 550 * Intel Iris Pro Graphics 580 * Intel Iris Plus Graphics 650 * Intel Iris Plus Graphics 655 Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30610 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06util/superiotool/ite.c: add support for IT8613EKrystian Hebel
Based on not publicly available IT8613E Preliminary Specification V0.3. Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-06lint/kconfig: Fix check for IS_ENABLED(XXX) where someone forgot CONFIG_Julius Werner
This is a great check, but unfortunately it's currently not effective because most uses of IS_ENABLED() do not have whitespace in front of them (they're mostly used as part of an if (IS_ENABLED(...)) condition). This patch makes the linter a little more generous in what it considers in scope to avoid these false negatives in the future. Change-Id: I2296410c73cd6e918465c90db33e782936bec0f9 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31746 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05cbfstool: Support new FMD flag "PRESERVE"Hung-Te Lin
When updating firmware, it is very often that we may want to preserve few sections, for example vital product data (VPD) including serial number, calibration data and cache. A firmware updater has to hard-code the section names that need to be preserved and is hard to maintain. A better approach is to specify that in FMAP area flags (the `area_flag` field) using FMAP_AREA_PRESERVE. With this patchset, a FMD parser flag "PRESERVE" is introduced and will be converted to FMAP_AREA_PRESERVE when generating FMAP data (by fmap_from_fmd.c). For example, The FMD statement: RO_VPD(PRESERVE)@0x0 16k will generate an FMAP firmware section that: area_name = "RO_VPD" area_offset = 0 area_size = 16384 area_flags = FMAP_AREA_PRESERVE BUG=chromium:936768 TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices Manually added 'PRESERVE' to some FMD files, and verify (by running fmap.py) the output coreboot.rom has FMAP_AREA_PRESERVE set Change-Id: I51e7d31029b98868a1cab0d26bf04a14db01b1c0 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-05rmodule: Add support for R_X86_64_PLT32Patrick Rudolph
The recent toolchain update also updated binutils, which has a new relocation type, introduced with commit bd7ab16b (x86-64: Generate branch with PLT32 relocation). Add support for R_X86_64_PLT32, which is handled as R_X86_64_PC32. Add comment explaining the situation. Fixes build error on x86_64. Change-Id: I81350d2728c20ac72cc865e7ba92319858352632 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31468 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05cbfstool: Change FMD annotation to flagsHung-Te Lin
The idea of "annotation" for firmware sections was pretty flexible, but in future we will want multiple attributes applied to same area. For example, indicate the section must be preserved when updating firmware so serial number or MAC address can be preserved. The solution here is to extend annotation so it can take multiple identifiers (flags) in a row. For example, to declare a 64KB COREBOOT section as CBFS using annotation: COREBOOT(CBFS)@0x0 64k If there's a new flag "PRESERVE" indicating the section must be preserved before update, we can declare it following CBFS flag: COREBOOT(CBFS PRESERVE)@0x0 64k The flags are directly parsed in fmd_parser, and stored in an union flashmap_flags. Output modules can choose to ignore or process the flags. Currently the only supported flag is "CBFS" (for backward compatible with annotation). There will be more new flags in follow up patches. BUG=chromium:936768 TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices Change-Id: Ie2d99f570e6faff6ed3a4344d6af7526a4515fae Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31706 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05util/lint: Fix clang-format test and enable it by defaultPatrick Georgi
git diff needed to emit diffs without prefix (e.g. a/ and b/) for clang-format-diff to be able to work. Also require that the test succeeds, but note that it only runs on trees whitelisted in $(top)/.clang-format-scope. Change-Id: I7e9a32eb9281b5cb0b45506a206500fd1d315372 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05lint/clang-format: set to 96 chars per linePatrick Georgi
80 chars + 2 tabs was the compromise we got to in the last round of discussion. Change-Id: I9293a69d1bea900da36501cde512004d0695ad37 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-05util/inteltool: Add Apollo Lake GPIO groups and namesNico Huber
Apollo Lake has four GPIO communities each with a single group named after the physical location of the pads (I guess): North West, North, West and South West. Also add some logic to be able to tag the default function of a pad (with an asterisk before its name). This seems easier to review in the tables, but we could also encode the number of the default explicitly instead. Used Intel documents: - 334817-001 (datasheet vol. 1) - 334819-001 (datasheet vol. 3) Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-04fmap: Add FMAP_AREA_PRESERVEHung-Te Lin
When updating firmware, we may need to preserve some sections like VPD, calibration data, ... etc. The logic can be hard-coded in updater as a list of known names, but a better solution is to have that directly declared inside FMAP area flags. To do that, the first step is to apply the changes in flash map (http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now defined and will be set in future with new syntax in FMD parser. BUG=chromium:936768 TEST=make; boots an x86 image. Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/31676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-03rmodule: Don't emit reloc for R_X86_64_PC64Patrick Rudolph
Relocations for PC relative instructions must not emitted. As PC64 are unlikely with current code, it never was an issue. Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31469 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-01util/cbmem: Improve utility descriptionKyösti Mälkki
Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28cpu/intel: Rename socket_mFCPGA478 to socket_mNico Huber
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN, the successor of the socket that was meant. The official name of this socket is mPGA478MT. But "Socket M" is much easier to distinguish. Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-27util/abuild: Set fatal asserts when running scanbuildMartin Roth
Because coreboot's asserts aren't fatal by default, scan-build finds problems in code that is actually protected by an assert. This change fixes that and allows us to add asserts to protect against other failures. Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/31650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-26ACPI: Fix error on asl_compiler_revision formatElyes HAOUAS
dmesg report wrong asl compiler version as this value wasn't in hexadecimal: FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 01341407) DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215) This error was introduced on change-Id: I91b54b43c8b Tested on 945G-M4 board, dmesg now report the right value: FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 20190215) DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215) Change-Id: I5494bb1e7af17eba0c2da8a0c2eb9e40ffd8d065 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31612 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25security/vboot: Add measured boot modePhilipp Deppenwiese
* Introduce a measured boot mode into vboot. * Add hook for stage measurements in prog_loader and cbfs. * Implement and hook-up CRTM in vboot and check for suspend. Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25intelmetool: Use GPLv2+ where possibleDamien Zammit
Upstream intelmetool is out of date; I suggest I archive it instead of trying to merge coreboot's changes into it. However I would like to preserve the licensing of files in the tool as GPLv2+ where possible instead of GPLv2-only. Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/c/31587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-22intelvbttool: Add support for reading vbt from sysfsAlex Feinman
VBT on Intel(R) systems is available via sysfs as /sys/kernel/debug/dri/0/i915_vbt However the size of this file reads as 0 causing intelvbttool to fail. This patch implements incremental reads with realloc for such cases or whenever the file size is not available (e.g. reading from stdin). After this patch is applied, intelvbttool can be used as follows: sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d Change-Id: I5d17095a5747550b7115a54a7619b7294a846196 Signed-off-by: Alex Feinman <alexfeinman@hotmail.com> Reviewed-on: https://review.coreboot.org/c/31531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21ACPI: Correct asl_compiler_revision valueElyes HAOUAS
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21SMBIOS: Fix bios versionElyes HAOUAS
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-20util/lint: Exclude util/inteltool from checkpatchNico Huber
It's causing too much noise during review of register tables. Change-Id: Iae6cd4454c5ed84b5fe0ea5f8a244e2a2fa13407 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31367 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18crossgcc: Update MPFR to version 4.0.2Elyes HAOUAS
Change-Id: I5569e61c2a3a64cf353afe3195eca82709362305 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31218 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-15crossgcc: Update binutils to version 2.32Elyes HAOUAS
Change-Id: I943863587dff6db72d12673bc30ea46f4fd4b66f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-14util/ifdtools: Make EC region readable to BIOS/CPUBora Guvendik
Allow EC region to be readable by BIOS/CPU so that flashrom can read it. BUG=b:123199222 TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, run firmware_LockedME test. Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/31377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-06Makefile.inc: Create a default SMMSTORE regionArthur Heymans
Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-06Makefile.inc: Optimize generating the default x86 fmapArthur Heymans
Put the FMAP FMAP region right above the coreboot CBFS region. The other regions like RW_MRC_CACHE and CONSOLE often have alignment requirements so it makes sense to put those on top. This also simplifies the code the generate the default fmap a little. Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30419 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-01cbmem: use aligned_memcpy for reading cbmem address informationAaron Durbin
The coreboot table entry containing the memory entries can have fields unnaturally aligned in memory. Therefore one needs to perform an aligned_memcpy() so that it doesn't cause faults on certain architectures that assume naturally aligned accesses. BUG=chromium:925961 Change-Id: I28365b204962ac89d65d046076d862b6f9374c06 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/31181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Manoj Gupta <manojgupta@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-29util/docker: Update container for doc.coreboot.orgPatrick Georgi
Now running 1.8.3, with a fix to the theme so search still works, and a recommonmark version that properly rewrites links to .md files. Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-29util/ifdtools: Consider EC region accessLijian Zhao
Version 2 IFD will have flmstr5 as EC region access control, consider it during descriptor lock/unlock process. BUG=N/A TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check flmstr5 value by hexdump the SPI image at offset FMBA+0x90. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8 Reviewed-on: https://review.coreboot.org/c/31111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-29util/ifdtool: Add lock support for CNL and ICLLijian Zhao
Cannonlake and Icelake have same read/write region permission settings with skylake and kabylake, so add it here as well. BUG=b:123199222 TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the setting matches 0x0D for read and 0x04 for write. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2 Reviewed-on: https://review.coreboot.org/c/31104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-26Revert "util/bincfg: code cleanup: convert sym_table to a local variable"Angel Pons
This reverts commit 48c24ce5eefe64b1aa82237f0a4be2772c686ef6. Reason for revert: Commit broke bincfg, and sym_table as a global variable is less bad than passing it around in function calls. Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/31105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-26crossgcc: Update CMake to version 3.13.3Elyes HAOUAS
Change-Id: If3bd670e2273715b6996e2ca78a0b9c412bfd220 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-26util/crossgcc: Update to binutils 2.31.1 and gcc 8.2Patrick Georgi
Change-Id: Icf7c6bdd4021bf84cc295c819f93838248e0f4c7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-25util/superiotool: detect Fintek F81866, F8196*Kyle Stevenson
F81866 detection tested with the iBASE SI-613: superiotool r4.9-420-g034e5e6 Found Fintek F81866 (vid=0x3419, id=0x1010) at 0x4e F8196* detection is based on chip IDs provided by iBASE, but untested. Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39 Signed-off-by: Kyle Stevenson <kstevenson@comqi.com> Reviewed-on: https://review.coreboot.org/c/31052 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24util/lint: update non-ascii linter checking rulesMartin Roth
- Check non-external payloads - Remove directories that aren't in the coreboot git repo. - Remove non-phrase rule from list of excluded phrases Change-Id: I9e056e8b43af567f102dfc0db76f60328aa1ed04 Signed-off-by: Martin Roth <martinr@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24util/kconfig: Add `toada` Ada spec generation toolNico Huber
Converts `auto.conf` to an Ada spec file. Write to $(obj)/cb-config.ads and set the package name to `CB.Config`. Change-Id: I97c060d8a613c74a82a18aff9524ad4b01f9df56 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-24cpu/intel/model_206ax: Remove the notion of socketsArthur Heymans
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23util/lint: Update non-ascii linter for FreeBSDMartin Roth
On FreeBSD, this test was failing with the error: "grep: Argument list too long" - Remove support for testing coreboot not in a git repo. Many of the other linters already don't support this. - Use git grep to find offending files, then xargs to print out the lines. Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd Signed-off-by: Martin Roth <martinr@coreboot.org> Reviewed-on: https://review.coreboot.org/c/28448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-22util/crossgcc: use fixed length version string.Wonkyu Kim
After merging util/crossgcc: derive date and version from latest commit (https://review.coreboot.org/c/coreboot/+/30804), crossgcc build is broken in internal repository due to long version name;coreboot.org repository is ok because it uses short tag name. The patch uses "git describe" which is dependent on git tag name. If tag name is little bit long, it can cause crossgcc build failed. To avoid this issue, use only short version of hash string which is fixed length. And it's enough as version string, because we also use date(CROSSGCC_DATE) together. TEST=Build crossgcc in both coreboot.org and internal repository which uses longer tag name and check version string in build log. Change-Id: I405b2e4e5c05831c25aebf1c73a281adab8ef452 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/31001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-21util/inteltool: Add support for DenvertonThomas Heijligen
Used documents: - C3000 Product Family Datasheet Change-Id: I54d09c78e1cce84b63300dfc0aa1bb374bb7faae Co-authored-by: Felix Singer <migy@darmstadt.ccc.de> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/30887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-20util/autoport: Make dsdt.asl prettierAngel Pons
Small cosmetic changes which fix aesthetic inaccuracies. Change-Id: I8fef4bbe12b283cee2ab8d078de950171757bbfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-18util/autoport: Fix include styleAngel Pons
Change-Id: If0dfee38bd82b3c8e9b5173e520cb244787c0a9a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30970 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18util/autoport: Break very long lineAngel Pons
Change-Id: Id45b0970a457ad4a724b71b4887ce4a1332596be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30968 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18util/autoport: Correct DSDT include statementAngel Pons
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file), some model_206ax code was moved to a common place. However, autoport was not updated accordingly. Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30967 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 06:13:51 +0000