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authorAngel Pons <th3fanbus@gmail.com>2019-01-16 00:18:33 +0100
committerFelix Held <felix-coreboot@felixheld.de>2019-01-18 19:36:13 +0000
commit07b6f16063861061da5c14fdd749c85b70848557 (patch)
tree8beb1b75a823d7edacda09ce12a7fe5902319e66 /util
parentcd97982e2e2a9eaff50cc9dce02d7d5a18685583 (diff)
util/autoport: Correct DSDT include statement
With commit aaced4a (cpu/intel/common: Use a common acpi/cpu.asl file), some model_206ax code was moved to a common place. However, autoport was not updated accordingly. Change-Id: I51b7e9c5d226f591596c33d6a3cb326a34420493 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/30967 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util')
-rw-r--r--util/autoport/sandybridge.go2
1 files changed, 1 insertions, 1 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index cf2b85987c..4f08ad9f36 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -122,7 +122,7 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
KconfigInt["MAX_CPUS"] = 8
DSDTIncludes = append(DSDTIncludes, DSDTInclude{
- File: "cpu/intel/model_206ax/acpi/cpu.asl",
+ File: "cpu/intel/common/acpi/cpu.asl",
})
DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{