| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-05-09 | util/: Replace GPLv2 boiler plate with SPDX header | Patrick Georgi |
| 2020-05-09 | AUTHORS, util/: Drop individual copyright notices | Patrick Georgi |
| 2018-11-22 | riscv: fix bug of sifive-gpt.py | Xiang Wang |
| 2018-11-17 | treewide: use /usr/bin/env where appropriate | Yegor Timoshenko |
| 2018-09-14 | riscv: add trampoline in MBR block to support boot mode 1 | Philipp Hug |
| 2018-07-26 | util: Add description.md to each util | Tom Hiller |
| 2018-04-26 | src/sifive: Add the SiFive Freedom Unleashed 540 SoC | Jonathan Neuschäfer |
| 2018-04-25 | util/riscvtools: Rename to util/riscv/ | Jonathan Neuschäfer |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |