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Change-Id: I66a243486a347313103ffd2cb2ca0447228e4054
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Behavior matches with other dumps of inteltool.
Change-Id: Id9755d251fc42185c9e8d574deb55c76e129b718
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The SATA device moved from 0:1f.2 to 0:17.0, 0:1f.2 became PMC. We
detect that by checking the PCI device class.
The ABAR MMIO space has grown to 2KiB and up to 8 ports are supported
now. For backwards compatibility, only dump port registers of ports
that are enabled in the Ports Implemented (PI) register.
Change-Id: I8e0f07d7359d92f689882b5afefa5ffb3766ee8b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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We have to call pci_free_dev() for each device we allocated with
pci_get_dev(). Since that's not the case for `sb`, we can close
this TODO.
Change-Id: I1ef80c837263a205467f835156dcb8fa667d3a8f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ia5ef6b04f01e381174a4d8f73ddafeb18d488803
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This is supposed to fill the `size[]` array with the actual sizes of
a device' MMIO ranges, but apparently isn't implemented for every
access method in libpci (we let the library choose one). It tells us
by clearing `PCI_FILL_SIZES` in the return value of `pci_fill_info()`
(which we don't check). Since we don't ever use `size`, we can just
make it clear and don't ask for it.
Change-Id: I3fb9334472f1c7563a9e17910190f73affbe067a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The Wildcat Point-LP Premium is handled the same as the Wildcat Point-LP,
but it wasn't supported by inteltool.
Change-Id: I694514e1963f074582a3f5f81d63c20e7fa49189
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19445
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Lint prevents my next commit which adds a new line to the table
so it's better to break all the > 80 character lines so it will be
consistent with the new line I'm about to add.
Change-Id: Ic7ad0cb90e861cd830db1186225d4f839250792a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19444
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Reuses ICH10R functions.
TESTED on Intel DG43GT (Not supported by coreboot)
Change-Id: If9ae8ba8b95e3a7bf6596ae639eb8cafab583298
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19232
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Without this change inteltool cannot read BIOS_CNTL values nor can it
read the SPIBAR values.
Change-Id: I9ff16e060aca66e3cb11c8315a6843ccecd1d3c2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The ICH7 SPIBAR offset and registers are different from later
generation.
ICH8 has a different offset from later generation.
ICH6 has no SPI controller.
Change-Id: I7691bce619089b15805114047bcb1fd121a5722b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Use a unique bus/device/function if a bay trail LPC bridge was found.
TEST=Run on MinnowBoard MAX Turbot and customer's LynxPoint-LP.
Change-Id: Ib4b50aaf9817ac94f46c28925081540676226d84
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17464
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Id42a2901cf76e6b867f62a752a38bbd6f6e5f54e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17059
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I9d27c276053c51021166f4b22d150060e415d08f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17025
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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According to datasheets for Intel ICH/PCH, it works for chipsets from
ICH7 to 9-series PCH, with PCI device address D31:F2.
Change-Id: If1ddd7208108bda949b5a94894a7bf9e8bfe1e5f
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/15106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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These non-ascii & unprintable characters aren't needed.
Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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A struct pci_dev was allocated but not freed.
Change-Id: I6a8bbef6a118fc1f0aa7037e72c4d0dda9208f4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1353037
Reviewed-on: https://review.coreboot.org/15971
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Iba5fc92d8740d0bb7d41f8a83513ba7fb97be592
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15900
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The current implementation from Vladimir simply dumps 1 MB of memory
contents starting at the base address of the second PCI device (which
most likely is the VGA controller on Intel systems). This locks up a
number of different systems, e.g. my Ibex Peak-based T410s.
This patch documents the issue and stops dumping the graphics registers
for the -a/--all parameter.
Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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- manpage
- usage message
- new warning message if -S is used on an unsupported chipset
Change-Id: I1acaa5f4232b65244ec00fd22ec7460d9cc387f1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14624
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The license text that we decided to remove was removed from the headers
of these files, but was still left in the help text. Remove it from
those locations as well.
Change-Id: I0e1b3b79f1afa35e632c4a4dd09a8bf2b02eaa6d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12913
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Tested on NetBSD-7.0/i386
Change-Id: I6a693633d3a80ea07ade233b1b4fd1c5a1412032
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12835
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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- Have clean remove junit.xml files.
- Remove junit.xml target from cbmem makefile - this is in the top
level Makefile.inc now.
- add distclean targets to makefiles.
- Make sure all makefiles have .PHONY set up.
- rm commands need -f or they will fail if the file they're trying
to remove doesn't exist, causing the build to fail.
Change-Id: I2f0635f2c0a9417e3377a90c8d67103323c4a72f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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E.g. on my MacbookAir to generate spd.bin to be used
with coreboot I do:
./inteltool -S spd.bin
Change-Id: If165475ed3e1f3262a8926ef619128d25b1e2896
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11847
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Previously, X4X was incorrectly named because it provides
support for SKUs within XX4X range. This is renamed.
This patch provides support for all X4X SKUs according to
datasheet Intel 4 Series Chipset Family Specification Update,
namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions).
Tested on Gigabyte GA-G41M-ES2L
Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/11245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Replace usage of u<bitness> types with proper uint<bitness>_t types.
Change-Id: I8359d70304a138b29bfc1358af77af26b2bc8682
Signed-off-by: Roger Pau Monne <roger.pau@citrix.com>
Reviewed-on: http://review.coreboot.org/11364
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.
Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10322
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Useful for autoport and other gfx-related developpement.
Change-Id: I1fc0952bc30ab15cd39a4f0c00649714dcf318f3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10276
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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add handling of PCI IDs for Broadwell-U/Wildcat Point LP,
using same functions as Haswell-U/Lynx Point LP
Change-Id: I1094cbdace3c73f0f85c2e27c676b877b1a04bfe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10209
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Tested on a Lenovo X61.
Change-Id: I047f5a029d9be9fe6a000e2b45be44c7f14b33d7
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: http://review.coreboot.org/8568
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ia90f967a4988214c719f374a49233bb6fade11b0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8481
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8049
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Add silvermont (Bay Trail core) MSRs - these are shared with
rangeley/avoton.
- Add GPIO values and GPIO muxing information.
- Add Bay Trail to the PM list.
Still to do:
- Northbridge functionality (RCBA, Memory timings, etc.)
- Add Graphics registers
Change-Id: I9fe0c0f1efe5f4344aeb3bad3f13037555109060
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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abuild, inteltool, and superiotool's manpages still referenced reporting
bugs to tracker.coreboot.org. Remove that url and change the message
to point to the coreboot mailing list instead.
Change-Id: I7a85bc2b36ccdb7f3798a39a08345c1a02a67e65
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7712
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Add IDs of some SNB and Haswell chips; use more descriptive names.
Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell.
Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
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If we find multiple LPC controllers, we want to tell the user that we'll
ignore all but the first. However, we use 'dev' in the message (the
current device found) instead of 'sb' (the one we want to use).
Fix the message by using 'sb' and break the loop right away in this
case. It's sufficient to tell the user once which LPC controller we'll
use.
Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/7342
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
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Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7337
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Mathias Krause <minipli@googlemail.com>
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Change-Id: I408614e743ab6f0f447b327c01d8f4dacf787124
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6692
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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It never worked.
Change-Id: Ic68614bb8ed481babf54b4f9d8db00635755f4d1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7324
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Change-Id: I2d5a31c831afeb92522b2673fde82922dc4efca5
Reviewed-on: http://review.coreboot.org/7275
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Nicolas Reinecke was noticing that in my Lenovo T410s logs the GPIO*3
settings were missing. This led to some investigation and this patch, thanks!
Change-Id: I7ba28aa00d10f988a7fe81e61d2e216b54a11006
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/7239
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I8c30742f6cd759dce4c9641edad107d9e3154975
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/6766
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header
is incorrectly reported as 'GPIO_SEL3'.
Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6459
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch supports northbridges: 0x0150 0x0154 0x0158 0x015c as 3rd gen core.
Tested on 0x0150 (0x0154 previously only model).
Change-Id: I53a33d864494dd4ac1cb9e8330450f56001ed92c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5873
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This bothers rpmlint.
Change-Id: I27d9cfac3ef6834ff87acc5a5ccbf332e59eeb1a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: http://review.coreboot.org/5075
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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The raw CPUID is useful for matching the directories under 'src/cpu/intel'
and is not easy to find out otherwise because it is most often decoded
already. The decoded values are not obviously hexadecimal so prepend
them with 0x to make sure they are unambiguous.
The output differences look like this:
- CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
+ CPU: ID 0x20652, Processor Type 0x0, Family 0x6, Model 0x25, Stepping 0x2
Change-Id: Id47f0b00f8db931f0000451c8f63ac1e966442c4
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3788
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Tested-by: build bot (Jenkins)
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Also, add pretty printing of Westmere's DMI registers (tested on my t410s
by staring at non-zero output values :)
Apparently Nehalem does not have a MEMBAR? But there are some
documented memory controller control registers in PCI configuration
space... left out for now.
The PCIEXBAR is not documented publicly AFAICT, but there is
a similar register on a device on bus 0xFF. phcoder might know more...
Change-Id: I5faadb6e4f701728f5290276c02809b4993bd86d
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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e4e8e090fa36cb3a098e1ddf0ea44c796c140572 does add support for QM57,
but there are many more that should work with that code(?).
Does not explode on...
CPU: Processor Type: 0, Family 6, Model 25, Stepping 2
Northbridge: 8086:0044 (1st generation (Westmere family) Core Processor)
Southbridge: 8086:3b0f (QS57)
Change-Id: I85e15ba45678a5bd635415a7a8d69c05bff8f7ef
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3321
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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Dump registers on mobile 5. Successfully tested on X201.
Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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When building inteltool with Clang, it warns about the following.
$ clang --version
Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
Target: i386-pc-linux-gnu
Thread model: posix
$ CC=clang make
[…]
clang -O2 -g -Wall -W -c -o pcie.o pcie.c
pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
pciexbar_phys = pciexbar_reg & (0xff << 28);
~~~~ ^ ~~
pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
pciexbar_phys = pciexbar_reg & (0x1ff << 27);
~~~~~ ^ ~~
pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow]
pciexbar_phys = pciexbar_reg & (0x3ff << 26);
~~~~~ ^ ~~
3 warnings generated.
[…]
Specifying the length by using the suffix `0xffULL` fixes these issues
as now enough bits are available.
These issues were introduced in commit 1162f25a [1].
commit 1162f25a49e8f39822123d664cda10fef466b351
Author: Stefan Reinauer <stepan@coresystems.de>
Date: Thu Dec 4 15:18:20 2008 +0000
Patch to util/inteltool:
* PMBASE dumping now knows the registers.
* Add support for i965, i975, ICH8M
* Add support for Darwin OS using DirectIO
[1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39822123d664cda10fef466b351
Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3015
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In [1] Idwer Vollering noted, that the type `u64` is not portable so
on his FreeBSD system, the following warning is shown.
$ clang -O2 -Wall -W -I/usr/local/include -c -o amb.o amb.c
amb.c:441:22: error: use of undeclared identifier 'u64'
ambconfig_phys = ((u64)pci_read_long(dev16, 0x4c) << 32) |
The type `uint64_t` seems to be defined also on FreeBSD, so using this
fixes the warning.
Note, this warning is not reproducable with Debian Sid/unstable for
example. I have no idea why though.
[1] http://review.coreboot.org/#/c/3015/
Change-Id: Ic22f4371114b68ae8221d84a01fef6888d43f365
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3086
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Change-Id: I6a119b1f362f481914377e8d14c713159f895130
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3030
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This fixes at least one warning on my machine where "llx" is replaced by PRIx64.
Change-Id: Iee3e5027d327d4d5f8e6d8b2d53d051f74bfc354
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/3024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Cppcheck [1], a static code analysis tool, warns about the
following.
$ cppcheck --version
Cppcheck 1.59
$ cppcheck --enable=all .
[…]
Checking cpu.c...
[cpu.c:951]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
[cpu.c:962]: (warning) %d in format string (no. 1) requires a signed integer given in the argument list.
[…]
And indeed, `core` is an unsigned integer and `man 3 printf` tells
the following about conversion specifiers.
d, i The int argument is converted to signed decimal notation. […]
o, u, x, X
The unsigned int argument is converted to unsigned octal (o), unsigned decimal (u), or unsigned hexadecimal (x and X)
notation.
So use `u` and Cppcheck does not complain anymore.
[1] http://cppcheck.sourceforge.net/
Change-Id: If8dd8d0efe75fcb4af2502ae5100e3f2062649e4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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When building inteltool under x86-32, the following warnings are
shown.
$ gcc --version
gcc-4.7.real (Debian 4.7.2-15) 4.7.2
Copyright (C) 2012 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ make
[…]
amb.c: In function ‘amb_read_config32’:
amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
amb.c: In function ‘amb_read_config16’:
amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
amb.c: In function ‘amb_read_config8’:
amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
[…]
Nico Huber commented the following [1].
I don't see those warnings because I build for x86-64. I guess
they could be fixed by casting to `ptrdiff_t` (from stddef.h)
instead of `uint64_t`.
And indeed, using `ptrdiff_t` fixes the warning. But as Stefan
Reinauer commented in [2], `intptr_t` is more appropriate as this
is just a pointer and no pointer difference.
So `intptr_t` is taken, which fixes these issues warned about too.
These warnings were introduced in commit »inteltool: Add support for
dumping AMB registers« (4b7b320f) [3].
[1] http://review.coreboot.org/#/c/2996/1//COMMIT_MSG
[2] http://review.coreboot.org/#/c/3002/1/util/inteltool/amb.c
[3] http://review.coreboot.org/525
Change-Id: I2ea1a31dc1e3db129e767d6a9e0433fd75a77d0f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3002
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
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When buidling inteltool with GCC, the following warning is printed.
$ make
[…]
gcc -O2 -g -Wall -W -c -o memory.o memory.c
memory.c: In function ‘print_mchbar’:
memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat]
[…]
This was introduced in commit »inteltool: Add support for H65 Express
chipset« (c7fc4422) [1].
Address this warning, by using `%llx` instead of `%lx`.
[1] http://review.coreboot.org/1258
Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2994
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Tested-by: build bot (Jenkins)
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Allow to override the variables `CC`, `INSTALL`, `PREFIX`,
`CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`.
This way for example a different compiler can easily be used.
CC=clang make
As a side note, Clang in contrast to GCC does *not* issue the
following warnings.
$ clang --version
Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2)
Target: i386-pc-linux-gnu
Thread model: posix
$ gcc --version
gcc-4.7.real (Debian 4.7.2-15) 4.7.2
Copyright (C) 2012 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ make
[…]
amb.c: In function ‘amb_read_config32’:
amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
amb.c: In function ‘amb_read_config16’:
amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
amb.c: In function ‘amb_read_config8’:
amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
[…]
These are only shown under 32-bit and not 64-bit
$ uname -m
i686
and are going to be fixed in a separate patch.
Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2996
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds default values for the GPIO setup on Intel's Cougar Point and
Panther Point platform controller hubs (PCH). Values are taken from [1] and
[2], respectively. I've tested this with an H77 PCH. See below for the
output.
[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
Document-Number: 324645-006
[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
Datasheet
Document-Number: 326776-003
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: If99cf8d5c93e34ad28f52080fff64e01c220eb27
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds an option -G, --gpio-diffs to inteltool, which shows GPIO settings
that differ from platform defaults. For differing registers, the current,
the default, and an xor of the default and the current value is printed. A
follow-up commit will add defaults for the Cougar/Panther Point platform
controller hubs. If you specify both, -g and -G on the command line, all
GPIO registers will be printed interleaved with the diff.
Here's a preview:
$ ./inteltool -G
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
========== GPIO DIFFS ===========
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
$ ./inteltool -gG
CPU: Processor Type: 0, Family 6, Model 3a, Stepping 9
Northbridge: 8086:0150 (unknown)
Southbridge: 8086:1e4a (H77)
============= GPIOS =============
GPIOBASE = 0x0500 (IO)
gpiobase+0x0000: 0xb96ba1fb (GPIO_USE_SEL)
gpiobase+0x0000: 0xb96ba1ff (GPIO_USE_SEL) DEFAULT
gpiobase+0x0000: 0x00000004 (GPIO_USE_SEL) DIFF
gpiobase+0x0004: 0x06ff6efb (GP_IO_SEL)
gpiobase+0x0004: 0xeeff6eff (GP_IO_SEL) DEFAULT
gpiobase+0x0004: 0xe8000004 (GP_IO_SEL) DIFF
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0xe1f17f7e (GP_LVL)
gpiobase+0x000c: 0x02fe0100 (GP_LVL) DEFAULT
gpiobase+0x000c: 0xe30f7e7e (GP_LVL) DIFF
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (RESERVED)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (GP_SER_BLINK)
gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS)
gpiobase+0x0024: 0x00000000 (GP_SB_DATA)
gpiobase+0x0028: 0x0000 (GPI_NMI_EN)
gpiobase+0x002a: 0x0000 (GPI_NMI_STS)
gpiobase+0x002c: 0x00002000 (GPI_INV)
gpiobase+0x002c: 0x00000000 (GPI_INV) DEFAULT
gpiobase+0x002c: 0x00002000 (GPI_INV) DIFF
gpiobase+0x0030: 0x0aff70ff (GPIO_USE_SEL2)
gpiobase+0x0030: 0x020300ff (GPIO_USE_SEL2) DEFAULT
gpiobase+0x0030: 0x08fc7000 (GPIO_USE_SEL2) DIFF
gpiobase+0x0034: 0x15038ff2 (GP_IO_SEL2)
gpiobase+0x0034: 0x1f57fff4 (GP_IO_SEL2) DEFAULT
gpiobase+0x0034: 0x0a547006 (GP_IO_SEL2) DIFF
gpiobase+0x0038: 0xb65e7f4f (GP_LVL2)
gpiobase+0x0038: 0xa4aa0007 (GP_LVL2) DEFAULT
gpiobase+0x0038: 0x12f47f48 (GP_LVL2) DIFF
gpiobase+0x003c: 0x00000000 (RESERVED)
gpiobase+0x0040: 0x000001f3 (GPIO_USE_SEL3)
gpiobase+0x0040: 0x00000130 (GPIO_USE_SEL3) DEFAULT
gpiobase+0x0040: 0x000000c3 (GPIO_USE_SEL3) DIFF
gpiobase+0x0044: 0x00000ef3 (GPIO_SEL3)
gpiobase+0x0044: 0x00000ff0 (GPIO_SEL3) DEFAULT
gpiobase+0x0044: 0x00000103 (GPIO_SEL3) DIFF
gpiobase+0x0048: 0x00000dfc (GPIO_LVL3)
gpiobase+0x0048: 0x000000c0 (GPIO_LVL3) DEFAULT
gpiobase+0x0048: 0x00000d3c (GPIO_LVL3) DIFF
gpiobase+0x004c: 0x00000000 (RESERVED)
gpiobase+0x0050: 0x00000000 (RESERVED)
gpiobase+0x0054: 0x00000000 (RESERVED)
gpiobase+0x0058: 0x00000000 (RESERVED)
gpiobase+0x005c: 0x00000000 (RESERVED)
gpiobase+0x0060: 0x00000000 (GP_RST_SEL1)
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DEFAULT
gpiobase+0x0060: 0x01000000 (GP_RST_SEL1) DIFF
gpiobase+0x0064: 0x00000000 (GP_RST_SEL2)
gpiobase+0x0068: 0x00000000 (GP_RST_SEL3)
gpiobase+0x006c: 0x00000000 (RESERVED)
gpiobase+0x0070: 0x00000000 (RESERVED)
gpiobase+0x0074: 0x00000000 (RESERVED)
gpiobase+0x0078: 0x00000000 (RESERVED)
gpiobase+0x007c: 0x00000000 (RESERVED)
Change-Id: Ic77474c4bc0871e95103ddecd9f6a9406c8f016d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3000
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds the power management register definitions for Intel's Cougar
Point and Panther Point platform controller hubs (PCH). The definitions
are actually a subset of the older ICH10R registers: I've added just
those that are mentioned in the public specifications in [1] and [2].
I've tested dumping with an H77 PCH.
NM70 is missing in [1]. Therefore, I didn't add it here.
[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
Document-Number: 324645-006
[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
Datasheet
Document-Number: 326776-003
Change-Id: Ia6945fe96cd96b568ed5191e91dbba5556e1ee95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds the PCI IDs of Intel's Cougar Point and Panther Point platform
controller hubs (PCH) to the dumping of the root complex configuration
under the root complex base address (RCBA). Those PCHs are handled exactly
as the older ICHs which can be seen in [1] and [2]. I've tested dumping
with an H77 PCH.
NM70 is missing in [1]. Therefore, I didn't add it here.
[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
Document-Number: 324645-006
[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
Datasheet
Document-Number: 326776-003
Change-Id: I2296caae57e614171300362d41715deecec77762
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2986
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This adds the GPIO register definitions for Intel's Cougar Point and
Panther Point platform controller hubs (PCH). All information is taken
from the public specifications in [1] and [2]. I've tested it with an
H77 PCH.
NM70 is missing in [1]. Therefore, I didn't add it here.
[1] Intel 6 Series Chipset and Intel C200 Series Chipset - Datasheet
Document-Number: 324645-006
[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH) -
Datasheet
Document-Number: 326776-003
Change-Id: I31711e24f852e68b3c113e3bd9243dc7e89ac197
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2961
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds correspondings #defines for the PCI IDs of the LPC device on
Intel's Cougar Point and Panther Point platform controller hubs. Those
will be used more in later commits.
I've checked all those IDs against the specification updates [1] and [2].
[1] Intel 6 Series Chipset and Intel C200 Series Chipset Specification
Update
Document-Number: 324646-019
[2] Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)
Family - Datasheet Specification Update
Document-Number: 326777-010
Change-Id: Ibef5a30d283c568c345eb8d8149723e7a3049272
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/2960
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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reference for Atom MSRs are from
Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3C: System Programming Guide, Part 3
Order Number 326019, January 2013, Table 35-4, 35-5
Has been successfully tested on the targeted cpu.
Change-Id: If94279caeab27121c63ec43c258dc962c167ad51
Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2192
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Output values of 64bit registers and fix settings for GPE0_EN for
ICH9/10.
Change-Id: I8ca6b32500331707670972b38466345f581844cd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1625
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
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Use the verbatim variable method to define and export test code and
the actual libpci test from flashrom. This improves readability and
will work with stricter compiler (settings).
Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1575
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ied0ff16c16d8c2f04b55fe6b0a6ee38966d3c424
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1576
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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- Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
- Refine some names and macros.
- Clean up some whitespace errors.
- Add IDs and names of 5, 6 and 7 Series southbridges and the three
latest Core CPU families with integrated memory controllers but do
not implement any pretty printing routines for them yet.
The first generation Core family is already supported, although it
was wrongly named after the PCH and used the wrong ID. Also, the BAR
values have been mangled to 32b instead of 64b. Both errors have been
fixed and most basic support for the other two generations was added.
Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1574
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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&> is a bashism to redirect both outward streams (stdout and stderr), but
with other shells this introduces a race condition with the rm command
after it, because the compiler execution is done in the background/
in parallel. Found and tested with dash.
Change-Id: I08516494828c9f7af168f954f2df027372657867
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1573
Tested-by: build bot (Jenkins)
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
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Added few MCH and DMI registers for H65E.
Description of them can be found at
"2nd Generation Intel Core Processors
Family datasheet"
Change-Id: If4fee35bb5a09b04ea0684be9cbd3c1e9084b934
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1258
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
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Change-Id: I2cd1dac0dd9a5da1000a3ffa3e1c8ee4c5c8ba43
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1175
Tested-by: build bot (Jenkins)
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- Fix some poor programming practice (breaks of strict aliasing as well
as not checking the return value of read)
- Use PRIx64 instead of %llx to prevent compilation warnings with both
32bit and 64bit compilers
- Use same compiler command options when linking inteltool and when
detecting libpci for inteltool
Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/752
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
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Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/525
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/356
Tested-by: build bot (Jenkins)
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The inline assembly for cpuid() was 32 bit specific. Additionally a
format string referencing a size_t argument wasn't using the %z length
modifier.
Change-Id: Iac4a4d5ca81f9bf67bb7b8772013bf6c289e4301
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/211
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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When building a position independent executable (PIE) EBX is used
internally by the compiler to generate position independent address
references so it cannot be used in the clobber list. Use the already
existing code for the Darwin plattform for that case, too -- it'll
preserve the EBX value.
Change-Id: Ief6d4872b8cd990856a0e8227a88bb228782aced
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/209
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
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Change-Id: I6f2272ae4071025e671638e83bade6a96aac658b
Signed-off-by: Ruud Schramp <schramp@holmes.nl>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/185
Tested-by: build bot (Jenkins)
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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See http://www.coreboot.org/DirectHW for more information
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5. Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6 on i865.
Sample output:
Disabling memory access:
$ sudo setpci -s 6.0 0x04.b=0x0
$ sudo ./inteltool -m | head -n 9
Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7
Intel Northbridge: 8086:2570 (i865)
Intel Southbridge: 8086:24d0 (ICH5)
============= MCHBAR ============
Access to BAR6 is currently disabled, attempting to enable.
Enabled successfully.
BAR6 = 0xfecf0000 (MEM)
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- pmbase is on southbridge function 3 on I82371XX
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5770 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the Intel ICH10 Family Datasheet.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Both are tested and appear to be working, however I'm not 100% clear
on if the NM10 has any other PCI IDs.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Björn Busse <bj.rn@co-assembler.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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northbridge. Also add support for the very similar Q963/965 northbridge.
Tested:
D510: confirmed working, with MCHBAR enable code
Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work
Untested:
D410/D525/N400: should be the same northbridge
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5598 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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ICH6 Southbridge,
82915 Series Northbridge,
P4 6xx Series CPU
to inteltool
Tested on my Clevo D900T, based on ICH6 and i915P, with a p4 630
installed.
Signed-off-by: Pat Erley <pat-lkml@erley.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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