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2021-07-31soc/amd/common/block/acpi: Add IVRS kconfigJason Glenesk
Add new IVRS kconfig option to control IVRS generation. BUG=b:190515051 Change-Id: Iad0c6401dbccd2f3f75464a69e4c27f64d3507a5 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-31arch/x86/acpi: Add code for KEY_MICMUTE and KEY_KBDILLUMTOGGLEScott Chao
Chromebook have some platform need support MICMUTE and KBDILLUMTOGGLE. BUG=b:194146863 BRANCH=none TEST=check on evtest type 4 (EV_MSC), code 4 (MSC_SCAN), value ab type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), 1 type 4 (EV_MSC), code 4 (MSC_SCAN), value 9b type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1 Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Ic39ecb3118e885c9e6d84d7b78bf435cb903d17e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-07-31mb/google/dedede/var/boten: Set the xHCI LFPS period sampling off time to 0msstanley.wu
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:187801363 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I9328e758ed92389e44b25ff4daf6ec19b37ae7d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.corp-partner.google.com>
2021-07-31soc/amd/common/block/gpio_banks: use unsigned int for gevent parameterFelix Held
A valid GEVENT number is never negative. The local variable in set_single_gpio still needs to be a signed integer, since the return value of get_gpio_gevent being -1 indicates that the GPIO can't generate a GEVENT. The check for that makes the function return before calling program_smi of program_sci, so the parameter of those functions can be changed to unsigned. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add missing newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I87595aea45bb3852a70c7322eae5a94abecb76a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56704 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add comment in check_gpiosFelix Held
Each bit in the GPIO wake status index registers is set to 1 when at least one of 4 corresponding GPIO pins has its wake status register set. Added the comment since the gpio_base + i * 4 in the next line looked as if it calculates some absolute register value which is not what the code does or should be doing. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: use size_t where neededFelix Held
Since the parameter the variable gets compared with is size_t type, use size_t as type for that variable too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbersFelix Held
With the addition of the remote GPIO support, the GPIO number won't fit into 8 bit any more, so use the gpio_t type instead which is an uint32_t typedef. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/gpio_banks/gpio: factor out set_gpio_muxFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: drop unused GPIO bank definesFelix Held
The offsets of all GPIOs in the up to four regular banks are all calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to tableFelix Held
GPIO bank 3 isn't used in coreboot, but the existence is documented in both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and for those two SoCs all 4 banks are covered by the corresponding Memory32Fixed region in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01Ronak Kanabar
The headers added are generated as per FSP v2265_01. Previous FSP version was v2237_00. Changes Include: - Add Irms UPD in FspsUpd.h - Adjust Reserved UPD Offset in FspsUpd.h - Few UPDs description update in FspmUpd.h BUG=b:194032028 BRANCH=None TEST=Build and boot brya Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f Cq-Depend:chrome-internal:4004482 Cq-Depend:chrome-internal:4003608 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56511 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30mb/google/brya/variants/primus: Disable PCIe6Malik_Hsu
WWAN (fibocom L850-GL) works in USB mode, so turn off PCIe 6. BUG=b:194861116 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: Ie04a5bb2af9ce11f57339f460a7f880bfc14b688 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-29mb/google/dedede/var/cappy2: Add I2C devicesSunwei Li
Add tp and audio devices support in devicetree. BUG=b:193099842 BRANCH=dedede TEST=i2c devices function is OK Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I995e93b5a4c4294d6f6b97c48d14fabf48004d92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56513 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai
Sync the MemInfoHob.h with current FSP code. BUG=b:190339677 TEST=dmidecode -t 17 can show the memory information. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-29mb/google/brya: add BASEBOARD_DIR to support different baseboardZhuohao Lee
In order to support different baseboard configuration, we add the BASEBOARD_DIR to switch the directory. The expected structure looks like: mb ..|_ google .........|_ brya .............. |_ variants .....................|_ baseboard ..............................|_ brya ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ..............................|_ brask ....................................|_ gpio.c ....................................|_ memory.c ....................................|_ devicetree ......................|_ brya_variant1 ......................|_ brya_variant2 ......................|_ ... ......................|_ brask_variant1 ......................|_ brask_variant2 ......................|_ ... ...............|_ <all mb common code> BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ic99e42dbbd27fa3e1f6cb3a1b5daee1c8c7b1083 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-07-29mb/google/dedede: Configure VCCIOSEL for EN_SPKR GPIO PadKarthikeyan Ramasubramanian
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Storo. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ibd3bc90bd0bbc9a35922b29e3d1e106321bc7a06 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56616 Reviewed-by: Evan Green <evgreen@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh
Latency Tolerance Reporting is yet another PCIe power management feature which can have a bad influence on realtime performance. Disable this feature for all PCIe root ports. Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh
L1 substates of a PCIe link are meant to save some power when the link is not active but have the drawback that the PCIe latency is increased as PLLs are switched on and off as needed. In order to get a better realtime performance, disable all substates for every PCIe root port. Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-29mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driverWerner Zeh
This variant uses I210 MACPHYs so enable the I210 driver in order to set the needed MAC addresses. In addition add the function to retrieve a valid MAC address for the given MACPHY. Change-Id: Id1d59349db1b86cfdd71bbe27577c0530e8f0b51 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56567 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable Siemens NC-FPGA driverWerner Zeh
All the boards based on the mc_ehl baseboard have the NC-FPGA available. Enable the appropriate driver on baseboard level. Change-Id: I40b76a837b7ddb70ceba3135996b1c1080170c4d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56566 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable SIEMENS_HWILIBWerner Zeh
All variants based on mc_ehl will use the Siemens HWILIB. Select the Kconfig switch on baseboard level. Change-Id: I940f84a4a7449487fe78c793f8dbb1c1b49fa54b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56565 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Enable In Band ECCWerner Zeh
Enable IBECC for mc_ehl1 to provide a memory failure protection. Change-Id: If8f81d6bacb77dc38e231c1cedf22831de8a38a9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56564 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl1: Disable System Agent dynamic frequency supportWerner Zeh
In favor of better realtime performance disable dynamic frequency support in the System Agent for mc_ehl1. Change-Id: I0e62bcf2e5efa97d89bf7192f1536747a02ad992 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56563 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/siemens/mc_ehl: Enable measured bootWerner Zeh
Enable measured boot for all boards based on mc_ehl baseboard. Change-Id: I3aff943305c024d1f25d2127e6f60495828da3eb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-29mb/siemens/mc_ehl: Enable LPC TPMWerner Zeh
All the boards based on the mc_ehl baseboard have a TPM which is connected to SPI but mapped into the address space of the x86 so that it acts like a LPC attached TPM. Enable the TPM driver so that it will be used. In addition add the needed entry in devicetree. Change-Id: I301d0ed4a108bac45d95eced120e7ba280945d9c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-07-29mb/siemens/mc_ehl: Add external RTC RX6110SAWerner Zeh
All the mainboards based on mc_ehl use the external RTC RX6110SA. Enable the driver in Kconfig for all boards based on mc_ehl. In addition, as mc_ehl1 has the RTC attached to the SMBus, add the devicetree entry on behalf of the SMBus device 00:1f.4 for this variant. Change-Id: Ie1f45d0e6f9063c00253fe58a6268d40de91cf63 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56523 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29arch/x86/thread: Add #error when compiling for x86_64Raul E Rangel
The x86 thread code is all x86_32 specific. It needs to be updated to work with 64 bit. For now just throw an error when compiling. BUG=b:179699789 TEST=none Suggested-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I96187ad84bdec40c6883748afa41e217bc389b79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-29mb/google/dedede/var/storo: Set the xHCI LFPS period sampling off time to 0msTao Xia
LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:193898133 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ic84dc83b749cf3c6029a06730096b64ef8cb8cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-29commonlib: Add timestamp strings for TS_FSP_MULTI_PHASE_SI_INIT_xSubrata Banik
TEST=Refer to `cbmem -t` output below: Without this code changes, timestamp ids 962 and 963 are listed as `unknown`. 962:<unknown> 1,704,863 (157) 963:<unknown> 1,704,878 (14) With this code changes, lists the timestamps along with the timestamp strings. 962:calling FspMultiPhaseSiInit 1,704,863 (157) 963:returning from FspMultiPhaseSiInit 1,704,878 (14) Change-Id: I528567e4cc630e15dffffd1c7684798fcdde4535 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56641 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/google/dedede/var/pirika: Configure I2C times to 380-400 kHz for touchpadAlex1 Kao
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Audio codec:388.91 kHz Touchpad:394.48 kHz BUG=b:193864546 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: Ia57c90ead44ceb0990878dc0566e595bae5a9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56383 Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-29mb/intel/ehlcrb: Select LPSS console by defaultLean Sheng Tan
Select `INTEL_LPSS_UART_FOR_CONSOLE` to allow using PCH UART 2 as coreboot console. Also, simplify `UART_FOR_CONSOLE` defaults. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I853777116fc541e5dc31f3ca8673f8bf66c7c9e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-29soc/intel/elkhartlake: Update UART clock divider paramsLean Sheng Tan
As EHL UART source clock is 120MHz, update the clock divider parameters (M & N) to reflect the right value. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-28mb/google/brya/var/kano: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B H54G46CYRBX267 H54G56CYRBX247 K4U6E3S4AB-MGCL K4UBE3D4AB-MGCL BUG=b:194766276 b:194686484 b:194765811 TEST=build Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iba019c50224be8322865eee7baf81e3a574ff9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28util/spd_tools/lp4x: Add new memory parts and generate SPDsDavid Wu
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for ADL: 1. H54G46CYRBX267 2. H54G56CYRBX247 3. K4U6E3S4AB-MGCL 4. K4UBE3D4AB-MGCL BUG=b:194686484 b:194765811 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-28mb/google/volteer/variants/drobit: Add Charger Performance Control table ↵Wayne3 Wang
TCHG for DPTF setting. Add Charger Performance Control table TCHG for DPTF setting. BUG=b:194256990 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by thermal team. Change-Id: I9dba3f0e75d07d8ee9656bd1ee8d6de2d3b8c152 Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Paul F Yang <paul.f.yang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
2021-07-28mb/google/brya/variants/primus: Update NVMe clkMalik_Hsu
According to the schematic diagram of proto, modify the clock of nvme from the baseboard default to src0. BUG=b:194487277 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I41be517b434513bca2332ec37e54f56910302bb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-28Revert "soc/intel/common/block/gpio: Add support to program VCCIO selection"Karthikeyan Ramasubramanian
This reverts commit 4c569b52f6053fc39cb07eed4a0753ade567c5b6. This has introduced a regression in mainboards using JSL SoC such that it overrides the soft straps for all the GPIOs. This in turn has led to some of the peripherals not working. BUG=None TEST=Build and boot to OS in Storo. Ensure that the regressed peripherals are working back again. Change-Id: Ibfeed1075fe28051b926ddd7ca771693dc19dae8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56613 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28Revert "soc/intel/jasperlake: Enable support to program VCCIO selection"Karthikeyan Ramasubramanian
This reverts commit 16f2c5082c92ceb4defc252819aaeca96d801543. Change-Id: Id0f960fdeca5895afc22809ff3f0236d6dbe82f4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56614 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28Revert "mb/google/dedede: Program VCCIO selection for EN_SPKR GPIO"Karthikeyan Ramasubramanian
This reverts commit ce79ceec86a38145b3a27aa4c78cf83a76cd51d0. This has introduced a regression in mainboards using JSL SoC such that it overrides the soft straps for all the GPIOs. This in turn has led to some of the peripherals not working. Change-Id: Ifea5d4d0f474873f8bf4818ec1986e534f455216 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56615 Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28ec/roda/it8518/acpi: Remove unnecessary assignmentsFelix Singer
Simplify some operations to get rid of unnecessary assignments. Change-Id: I02c93d42ce1de693d5d58fd9a29ccd5bff0f5978 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-28ec/roda/it8518/acpi: Use lower-case hex formatFelix Singer
Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I9f08b048d41ab7a5d7d7dc735779ea019517491a Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56608 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28ec/roda/it8518/acpi: Use mathematical operatorsFelix Singer
Use mathematical operators instead of their equivalent methods. Change-Id: I5b1d5d9882eae5e8bcf2d97bcefaeea1a7ad8f4d Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56607 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28ec/roda/it8518/acpi: Use bit-wise and logical operatorsFelix Singer
Use bit-wise and logical operators instead of their equivalent methods. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I30807e14b2a9a8203a76d418f586423bcaec2a3a Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-28ec/roda/it8518/acpi: Make use of the assignment operatorFelix Singer
Replace `Store()` with the assignment operator. Change-Id: I2931a3e1b9a55198ec4dacc9218b6c9028052631 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Get rid of `Index()`Felix Singer
Use `FOOO[1337]` instead of `Index(FOOO, 1337)`. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I4f5d5cb8ce8c3ae37dc44ca87bd67596af9feee8 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Use decimal integers for accessing indexesFelix Singer
Change-Id: I7d4fb69a223e3b48a790e9144d2682619c18d513 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Make use of `Printf("...")`Felix Singer
Replace `Store("...", Debug)` with `Printf("...")`. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: Ie1a1f7320ef2850e4f861b1426240e6940036844 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28ec/roda/it8518/acpi: Don't hard-code GPE offsetNico Huber
The GPE offset of 16 is PCH specific. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I4ec38fc28d2436f84a090bb4ab38f20612cfd795 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-28mb/google/dedede/var/magolor: Add custom Wifi SAR for magisterDavid Wu
Add wifi sar for magister. Due to fw-config cannot distinguish between magolor and magister. Using sku_id to decide to load magister custom wifi sar. BUG=b:192290227 TEST=build and test on magolor/magister Cq-Depend: chrome-internal:3986580 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4510cc2ad42a11ec802ecd439b353f8e87d63868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28soc/intel/jsl: Add disable_external_bypass_vr configSimon Yang
This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake. BUG=b:191691430 BRANCH=dedede TEST=Build fw and confirm FSP setting are set properly by log Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28soc/intel/jasperlake: add pcie modphy settingsJamie Chen
This patch adds device tree settings to control pcie modphy tuning FSP UPDs. With this patch, the pcie modphy can be tuned per board. BUG=b:192716633 BRANCH=NONE TEST=build dedede variant coreboot with fw_debug enable and check if these settings have been changed successfully on fsp debug log. Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-28mb/google/dedede/var/sasukette: Set the xHCI LFPS period sampling off time ↵Tao Xia
to 0ms LTE module L850-GL may encounter U3 wakeup race condition with the host. Setting xHCI LFPS periodic sampling off time to 0ms so that the host would not miss the device-initiated U3 wakeup thus avoid the race condition. BUG=b:191426542 BRANCH=dedede TEST=flash the image to the device. Run following command to check the bits[7:4] is 0x0: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I3be7adad49f87956a6764ad91fec6e76681b393f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chiasheng Lee <chiasheng.lee@intel.com>
2021-07-28mb/google/volteer/var/collis: Update DPTF parameters for DVT buildFrankChu
Update Passive Policy and TCHG parameters. BUG=b:188936764 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Id75bfa74ba353f2342c95bcf8d73cd83c957deb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56512 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-28src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZEArthur Heymans
This symbol is only used in generating a default fmap. Change-Id: I8d92eba9978cdad5795b0f5755e1d75db7b3cb2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-07-28vc/mediatek/mt8195: Improve DRAM stability by impedance trackingRyan Chuang
Enable the impedance tracking for channel 2 and channel 3. The impedance tracking can compensate the settings of impedance when the temperature changes. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-27include/acpi/acpi.h: add comment about raw data in generic error statusFelix Held
Since the specification isn't very clear on this, add a comment about the optional raw data part of a acpi_generic_error_status block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6df7d2f216fe0515e89d08c8ed01f06d19461429 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-27cpu/x86/mp_init: don't wait between INIT and SIPI for X86_AMD_INIT_SIPIFelix Held
Since current AMD SoCs don't need some wait time between INIT and SIPI, we can skip the 10ms wait there, which improves the boot time a bit. before: CPU_CLUSTER: 0 init finished in 632 msecs after: CPU_CLUSTER: 0 init finished in 619 msecs mpinit still works on Mandolin and all CPU cores show up and are usable. This also doesn't change the binary in a timeless build for boards/SoCs that don't select X86_AMD_INIT_SIPI which I verified for lenovo/x230. BUG=b:193885336 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e044776f45021742a88a5e369a74383c1baaab6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26soc/amd/common/block/acpimmio: add Kconfig option for biosram accessorsFelix Held
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c is only used on Stoneyridge and the old amd/southbridge code and not on Picasso or Cezanne. It also only builds as a 32 bit binary and breaks when trying to build as a 64 bit binary, since the size of an uintptr_t is different on those two. There is no support for using the 32 bit binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP with 64 bit coreboot, so not building this for FSP-based SoC support moves us one step closer to be able to build coreboot as 64 bit binary for Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `FMDFILE` onceAngel Pons
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `OVERRIDE_DEVICETREE` onceAngel Pons
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/intel/galileo: Clean up `FMDFILE` Kconfig handlingAngel Pons
Remove redundant type, prompt and help text, and replace `depends on` clause with conditional default to allow specifying a FMAP when vboot is not selected. Change-Id: I37ddab3a27e304e810ea55f13821d755bb70cb4b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56551 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/facebook/monolith: Don't override `CBFS_SIZE` promptAngel Pons
Change-Id: I6fac40918f1ca3227ff68e79fcae039a26356d0d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56550 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/brya: Deduplicate chipset lockdown configFelix Singer
Due to an issue in sconfig, move `chipset_lockdown` out of `common_soc_config` and configure it separately in the baseboard's devicetree since it might get overwritten if a variant configures `common_soc_config`. Also, deduplicate the configuration of `chipset_lockdown`. Change-Id: Id969346df06aa82ab2ad2b1aa4884a9bcd876d75 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56408 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/intel/coffeelake_rvp: Use CHIPSET_LOCKDOWN_COREBOOTFelix Singer
Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown on all variants. Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26arch/x86,lib/thread: Enable thread support in romstageRaul E Rangel
This change does the following: * Pushes the cpu_info struct into the top of the stack (just like c_start.S). This is required so the cpu_info function works correctly. * Adds the thread.c to the romstage build. I only enabled this for romstage since I haven't done any tests in other stages, but in theory it should work for other stages. BUG=b:179699789 TEST=Boot guybrush with threads enabled in romstage Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8e32e1c54dea0d0c85dd6d6753147099aa54b9b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26arch/x86,cpu/x86/mp_init: Switch cpu_info index type to size_tRaul E Rangel
The alignment for `struct cpu_info` is wrong on x86_64. c_start.S uses the `push` instruction when setting up the cpu_info struct. This instruction will push 8 bytes but `unsigned int` is 4 bytes. By making it a `size_t` we get the correct size for both x86_32 and x86_64. BUG=b:179699789 TEST=Boot guybrush to the OS Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8ef311aaa8333ccf8a5b3f1f0e852bb26777671c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26arch/{arm,ppc64,riscv}: Remove cpu_infoRaul E Rangel
The structure and function are not currently used or implemented. x86 is the only arch that currently implements it. It is currently used for COOP_MULTITASKING and mp_init. Keeping around the unused definitions leads to confusion. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0775ef03168f7f9c41b1b05cb8f12724d0458ba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-26lib/thread,lib/hardwaremain: Lazy initialize threadsRaul E Rangel
By lazy initializing the threads, if a stage doesn't use them, they will be garbage collected. BUG=b:179699789 TEST=Boot guybrush to the OS and verify threads worked Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7208ffb5dcda63d916bc6cfdea28d92a62435da6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56532 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26lib/thread,arch/x86: Move thread stacks into C bssRaul E Rangel
There is no reason this needs to be done in asm. It also allows different stages to use threads. If threads are no used in a specific stage, the compiler will garbage collect the space. BUG=b:179699789 TEST=Boot guybrush to the OS Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib5a84a62fdc75db8ef0358ae16ff69c20cbafd5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56531 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26vboot/secdata_tpm: Add WRITE_STCLEAR attr to RW ARB spacesAseda Aboagye
It can be nice to update the TPM firmware without having to clear the TPM owner. However, in order to do so would require platformHierarchy to be enabled which would leave the kernel antirollback space a bit vulnerable. To protect the kernel antirollback space from being written to by the OS, we can use the WriteLock command. In order to do so we need to add the WRITE_STCLEAR TPM attribute. This commit adds the WRITE_STCLEAR TPM attribute to the rw antirollback spaces. This includes the kernel antirollback space along with the MRC space. When an STCLEAR attribute is set, this indicates that the TPM object will need to be reloaded after any TPM Startup (CLEAR). BUG=b:186029006 BRANCH=None TEST=Build and flash a chromebook with no kernel antirollback space set up, boot to Chrome OS, run `tpm_manager_client get_space_info --index=0x1007` and verify that the WRITE_STCLEAR attribute is present. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I3181b4c18acd908e924ad858b677e891312423fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/56358 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/dedede: Program VCCIO selection for EN_SPKR GPIOKarthikeyan Ramasubramanian
Realtek speaker amplifiers under auto mode operation have Absolute Max Rating (AMR) at 1.98 V. Hence probe the firmware config for speaker amplifier and program the VCCIOSEL accordingly. BUG=b:194120188 TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Ifa0b272c23bc70d9b0b23f9cc9222d875cd24921 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26soc/intel/jasperlake: Enable support to program VCCIO selectionKarthikeyan Ramasubramanian
Jasperlake is one of the few SoCs that support programmable VCCIO selection and this support is used by Dedede mainboard. BUG=b:194120188 TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: I54def27a499ccba7fd25cab1048fdca06dbc535f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56536 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26soc/intel/common/block/gpio: Add support to program VCCIO selectionKarthikeyan Ramasubramanian
Some of the Intel SoCs with more than 2 PAD configuration registers support programming VCCIO selection. Add a pad configuration macro to program VCCIO selection when the GPIO is an output pin. BUG=b:194120188 TEST=Build and boot to OS in Gallop. Ensure that the VCCIO selection is configured as expected and probing the GPIO reads the configured voltage. Change-Id: Icda33b3cc84f42ab87ca174b1fe12a5fa2184061 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56507 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/dedede/var/pirika: Add USB2 PHY parametersAlex1 Kao
This change adds fine-tuned USB2 PHY parameters for pirika. BUG=192601233 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Change-Id: Icf9fb41cd0ae40728e4ec5bd72a15ec3c45c963b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26soc/nvidia/tegra124: Increase bootblock sizeArthur Heymans
Verstage even fits in 44K so one can comfortably increase the bootblock size. This is need for the followup patches that turn console methods into drivers, which increase the bootblock a little, but still too much for the the bootblock to fit in the alloted size on this platform. Change-Id: If1eaf2b495e3032d156433fd0728134a66f4e49b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56521 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/dedede/var/cappy2: Generate SPD ID for supported memory partsSunwei Li
Add supported memory 'K4U6E3S4AA-MGCR' for cappy2 BUG=None TEST=Build the cappy2 board. Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ie76a4dca607bb2c3261bbe5478209a43e8430591 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26mb/asus/p5ql-em: Add default value for `gfx_uma_size`Angel Pons
Taken from Asus P5QPL-AM. Change-Id: If26e98eba5d762d99991bfc06cad1b84e1f430e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56562 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26soc/intel/jasperlake: Set xHCI LFPS period sampling off timeBen Kao
Provide an option to set xHCI LFPS period sampling off time (SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0). If the option is set in the devicetree, the bits[7:4] in xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated. The host will sample LFPS for U3 wake-up detection when suspended, but it doesn't sample LFPS at all time due to power management, the default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS period sampling off time is not 0ms, the host may miss the device-initiated U3 wake-up and causes some kind of race condition for U3 wake-up between the host and the device. BUG=b:187801363, b:191426542 TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash the image to the device. Run following command to check the bits[7:4]: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Ben Kao <ben.kao@intel.com> Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-26mb/google/brya: move the common config to the baseboardZhuohao Lee
This patch moves the common config to the Kconfig under BOARD_GOOGLE_BASEBOARD_BRYA and removes the redundant config. BUG=b:191472401 BRANCH=None TEST=build pass Change-Id: Ie59299dfaba6bb23758d4a4c22a6dbbb4ba6520e Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56387 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/google/brya: Enable BT offload conditionallySugnan Prabhu S
Currently, BT offload is disabled/enabled unconditionally based on the devicetree settings. BT offload uses I2S lines and cannot be enabled when a I2S based audio daughter card is active. So we need to enable BT offload only while using soundwire based audio daugther card. BUG=b:175701262 TEST=Verified BT offload on brya with soundwire audio daughter card BT offload enabled Change-Id: I6a9ad463e13e2cfcfc3b7de5a61a25cdef0641f7 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-26soc/amd/common/block/pm: Add support for Modern Standby event loggingKarthikeyan Ramasubramanian
Log the GPE and PM1 wake events into the event log using the SMI handler platform callback. BUG=b:186792595, b:186800045 TEST=Build and boot to OS in Guybrush. Ensure that the wake sources are logged into the event logs. 5 | 2021-07-15 16:26:43 | S0ix Enter 6 | 2021-07-15 16:26:49 | S0ix Exit 7 | 2021-07-15 16:26:49 | Wake Source | GPE # | 22 <- Trackpad 8 | 2021-07-15 16:27:07 | S0ix Enter 9 | 2021-07-15 16:27:13 | S0ix Exit 10 | 2021-07-15 16:27:13 | Wake Source | RTC Alarm | 0 25 | 2021-07-15 16:38:13 | S0ix Enter 26 | 2021-07-15 16:38:17 | S0ix Exit 27 | 2021-07-15 16:38:17 | Wake Source | GPE # | 5 <- Fingerprint Change-Id: Icec6fc03f4871cc46b32886575a7054bc289f4bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26soc/amd/common/block/acpi: Extract event logging helpersKarthikeyan Ramasubramanian
Move the event logging helpers defined in acpi into a separate library. This will allow logging power management and GPE events for both S3 and Modern Standby. Introduce a single helper acpi_log_events function to log both PM and GPE events. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-26lib/thread: Add asserts around stack size and alignmentRaul E Rangel
`cpu_info()` requires that stacks be STACK_SIZE aligned and a power of 2. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I615623f05bfbe2861dcefe5cae66899aec306ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26lib/thread: Guard thread_run_until with ENV_RAMSTAGERaul E Rangel
thread_run_until is a ramstage specific API. This change guards the API by checking ENV_RAMSTAGE. BUG=b:179699789 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4784942070fd352a48c349f3b65f5a299abf2800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56529 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-25mb/razer/blade_stealth_kbl/Kconfig: Fix up indentationAngel Pons
Change-Id: I0ffae7408f11f4f517204a0a670845c11b3601a8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56549 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-25sc7280: Increased CBFS_MCACHE sizeRavi Kumar Bokka
BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I16c41031718e1c3e41d0a128c8b254e2f6f94093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-07-25soc/amd/common/block/cpu/mca/mcax: add comment about McaXEnable bitFelix Held
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN APU that the McaXEnable bit is set in the CONFIG registers of all used MCAX banks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-24soc/amd/*/chip.h: Correct PSPP Enum ValueMatt Papageorge
It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-07-24mb/google/guybrush: Update GPIOs settingsMartin Roth
- The WWAN card was being disabled later than desired. - The SD card was never being placed into reset on BoardID 1. - Enable Touchscreen power - Enable PCIe_RST1 at the same points as PCIe_RST - Remove Redundant Bootblock settings BUG=b:193036827 TEST=Build & Boot, look at GPIO states through boot process Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5431da755d98e4ad0b300d01cac562d61db0bc08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-24src/drivers/intel/fsp2_0: allow larger FSP 2.0 headerNikolai Vyssotski
This is in preparation for migrating EDK2 to more recent version(s). In EDK2 repo commit f2cdb268ef appended an additional field to FSP 2.0 header (FspMultiPhaseSiInitEntryOffset). This increases the length of the header from 72 to 76. Instead of checking for exact length check reported header length against known minimum length for a given FSP version. BUG=b:180186886 TEST=build/boot with both header flavors Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56190 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24include/cpu: Remove one space from bitfield macro definitionSubrata Banik
This change is to maintain parity with other macro declarations. Change-Id: I67bf78884adf6bd7faa5bb3afa2c17262c89b770 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24include/cpu: Use tab instead of spaceSubrata Banik
Change-Id: I025c20cbcfcfafddbd72b18bca36165b98db8220 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56548 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24soc/intel/common/block: Add space before comment delimiterSubrata Banik
Update comment section to add space before comment delimiter to follow coding style. Change-Id: I883aeaa9839fa96fd7baf0c771b394409b18ddca Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56547 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-24soc/amd/common/block/cpu/mca/mca_common: remove additional newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49a27eb084b59db455153dd662d564a95940a0ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 23:27:45 +0000