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2022-12-05acpi/acpi.c: update ACPI table revisionsJonathan Zhang
Update SRAT table revision to 3 according to ACPI spec. Add CEDT table revision according to CXL spec. Change-Id: Iecc3a9892b0f8093013b2a426749e2ec5c00803b Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-05mb/amd/mayan: Improve naming of EC FWFred Reitberger
Change the EC FW CBFS filename prefix to a more accurate "ec/" Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic789df11160e3ffe7b7294b11e1fa80e3c3961ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/70206 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05google/skyrim/Kconfig: Enable DPTC for MorthalTim Van Patten
Enable SOC_AMD_COMMON_BLOCK_ACPI_DPTC for Morthal boards, to enable support for the low/no battery boot feature. BUG=b:217911928 TEST=build_packages --board=skyrim chromeos-bootimage --autosetgov Change-Id: I3eb6bee6601e34420a90f33f8f2c45cf3fe37f9b Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70216 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSDKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70065 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/amd/common/block/include/gpio_defs.h: Fix documentationFred Reitberger
Fixing documentation of PAD_INT macro and replacing spaces with a tab to match the rest of the documentation. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I72a2578ce21dd10b3beb65c706440c3379f216d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70281 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-05acpi: Helper functions to add certain _DSD propertiesKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70063 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05commonlib: Add essential comments for ELOG_CROS_DIAG_RESULTHsuan Ting Chen
ELOG_CROS_DIAG_RESULT_* codes should be consistent with the enum definition of enumerated histograms. Hence add comments based on the requirements of enum histograms in histogram guidelines. BUG=b:4047421 TEST=none Change-Id: I1a1a7c863d5aa9496649f81dc94fd79a6ad482df Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70145 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05superio/ite/it8772f/chip.h: Use 'bool' when appropriateElyes Haouas
Change-Id: I20c3298a920396718f0dc036e57faf8e46b82b2c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70253 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05superio/aspeed/ast2400/chip.h: Include <stdbool.h>Elyes Haouas
Change-Id: Ib4a0d77e7bb4cb52e91a5965cae0a6c7ddc40090 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70254 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05mb/intel/adlrvp: Add RTD3 support for PCIe slot1Cliff Huang
Add RTD3 support for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec BUG=none BRANCH=firmware-brya-14505.B TEST=Insert a SD card or NIC AIC on PCIe slot1 and run 'suspend_stress_test -c 1'. The RP8 should not cause suspend issue. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Ieb7d207a7ec3763bad3e82522e86a825c1ed00b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70119 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
2022-12-05mb/google/brya: Set power limit values for kano and zydronDavid Wu
Add the RPL CPU power limits to kano and zydron's power limit table. BUG=b:261127266 BRANCH=brya TEST="emerge-brya coreboot chromeos-bootimage", flash zydron with image-zydron.serial.bin and verify zydron boots successfully to kernel. Change-Id: I369c5d7a9a3db0c3e7184a23b0f159ed715b5a50 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70238 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/mediatek/mt8188: Add support for MIPI panelBo-Chen Chen
We need to add DSI and MIPI_TX settings to support MIPI panel. BUG=b:244208960 TEST=emerge-geralt coreboot Change-Id: Ib430939b4fa2d517d006b4c23d399754ef4583ff Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70184 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/mediatek: Fix DSI register definition for MT8186Bo-Chen Chen
The DSI CMDQ offset of MT8186 is different from previous SoCs. Therefore, we define two versions for DSI register header files. The v1 is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188. BUG=b:244208960 TEST=build pass BRANCH=corsola Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/mediatek/mt8188: Add display data path for MIPI outputBo-Chen Chen
For geralt project, we also support MIPI panel as our firmware display. So add this patch to configure ddp to choose eDP display or MIPI panel display. BUG=b:244208960 TEST=test firmware display pass for both eDP and MIPI panel on MT8188 EVB. Change-Id: I06f38b1889811274588c26e9284da4d502acf38b Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05nb/intel/gm45: Remove apic 0 from devicetreeArthur Heymans
This is added at runtime. Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69300 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05nb/intel/i945: Remove apic 0 from devicetreeArthur Heymans
This is added at runtime. Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69299 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05nb/intel/x4x: Remove apic 0 from devicetreeArthur Heymans
This is added at runtime. Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans
C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-05mb/google/zork: Select VBOOT by defaultMatt DeVillier
Zork boards will not boot without PSP verstage/VBOOT, so select it by default. Change-Id: I2447bf69baefd5560a0153dcd3d9b87b0a91a3f9 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69763 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05soc/nvidia/tegra210: Fix flushing SPI fifoArthur Heymans
This will avoid clearing the other bits in fifo_status. Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-05soc/intel/meteorlake: Add timestamp for cse_fw_syncDinesh Gehlot
The patch adds timestamp around cse_fw_sync(). BUG=none TEST=Verified on rex, cbmem -t: 948:starting CSE firmware sync 1,340,551 (50,657) 949:finished CSE firmware sync 1,379,348 (38,797) Port of 'commit b647e35119c1 ("soc/intel/alderlake: Add timestamp for cse_fw_sync")' Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70172 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-03mb/google/rex: Add PCIe based SD controllerSubrata Banik
This patch adds PCIe based SD controller at RP 7 (from RP 11) with Proto 1 schematics dated 11/30. Additionally, added the RTD3 entries for the SD controller. Finally, ensured that EN_PP3300_SD (GPP_D03) is configured in bootblock and SD_PERST_L (GPP_D02) is configured in romstage to meet the power cycle requirement. BUG=b:242917011 TEST=Able to build and boot Google/Rex. SD card detection is due for the Proto 1 hardware. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23d53e4d61ec36d2145f9e5816d97d13eb5b219e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70064 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-03mb/google/rex: Drop `board_id` check while configuring GPIOSubrata Banik
This patch drops the usage of reading `board_id()` while performing the GPIO configuration. The reason to drop the board_id check is to ensure that GPIO configuration for MLB (mainboard) would remain the same and the only GPIO PIN configuration that differs would be due to usage of having different DBs (daughter board) which will be taken care using CBI (and fw_config.c file) in coreboot. Additionally, drop unused early GPIO default configuration table. BUG=b:260804656 TEST=Able to perform the GPIO configuration and able to boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I96cafd1c904001cbf4199977e9e721afe5eab470 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-03mb/google/rex: Add probed fw_configs to SMBIOS OEM stringsSubrata Banik
Enable this feature, and it can use the probe statement in devicetree to cache of fw_config field as oem string. TEST=With CBI FW_CONFIG field set to 0x1561 localhost ~ # dmidecode -t 11 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: AUDIO-MAX98357_ALC5682I_I2S String 2: CELLULAR-CELLULAR_PCIE String 3: UFC-UFC_MIPI String 4: WFC-WFC_MIPI String 5: DB_SD-SD_GL9755S Change-Id: I6cb35eb9c0fbe32764ca76bb7a929cc92fc38404 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70228 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-03mb/google/herobrine: NVMe id determined by logical (not physical) bitShelley Chen
NVMe is determined by a logical bit 1, not the physical SKU pin. Thus, (logical) sku_id & 0x2 == 0x2 would mean that the device has NVMe enabled on it. Previously, I thought that it was tied to a physical pin, but this is not correct. BUG=b:254281839 BRANCH=None TEST=flash and boot on villager and make sure that NVMe is not initialized in coreboot. Change-Id: Iaa75d2418d6a2351d874842e8678bd6ad3c92526 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70230 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/alderlake: Update cpu and pch tracehub modesSridhar Siricilla
The patch gets the cpu and pch's tracehub mode from the debug area of the Descriptor Region and updates the respective UPDs. TEST=Build, verify the tracehub mode values. Update CPU' and PCH's Trace Hub modes: img=coreboot.rom printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc Check coreboot logs: [DEBUG] rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-02mb/system76/tgl-h: Convert oryp8 to a variantTim Crawford
Change-Id: Ied55add6d7549f165d8b97032d7f21ede0ce2dde Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02mb/purism/librem_14: Enable both lanes of left side USB 3.0 portJonathon Hall
Fixes using USB-C devices in either orientation on left-side USB-C port. Test: Plug USB-C device in both orientations on left-side USB-C port, check speed with lsusb -t. Change-Id: I9fbc53bb51a5225e92b0b6bb9ced87a0ab90c9ce Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69702 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/alderlake: skip external buses for D-states listEran Mitrani
The devices in the list that was introduced in commit c66ea985776 ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02mb/google/brya/var/zydron: Add WiFi SAR tableDavid Wu
Add WiFi SAR table for zydron. BUG=b:260770999 TEST=build FW and checked SAR table can load by WiFi driver. Change-Id: I8d5f966c7af3ac6d9923d4f6c851bfb340f31fab Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02mb/prodrive/atlas: Enable GPP_B14 buzzer supportLean Sheng Tan
Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using 8254 timer counter 2 output. However when 8254 timer is used, S0ix will not work as 8254 has to be gated instead. For further info on s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified Checklist). This CL also disables s0ix because it is not required by the platform. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67553 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02mb/prodrive/atlas: Add DP++ supportLean Sheng Tan
Update VBT configurations for DP++ and DP dongles support. Tested working on customer's side. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I7aa34297a10bf16b9043140bff91fd3a8c4009d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70154 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/meteorlake: Refactor `pmc_lockdown_cfg` functionKapil Porwal
This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. This patch also locks PMC features like: 1. Debug mode configuration and host read access to PMC XRAM. 2. PMC soft strap message interface. 3. PMC static function. and then calls into the PMC IPC function that informs about PCI enumeration. Port of - 1. commit 2eec87a553ec ("soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function") 2. commit bae4a0b5a1e4 ("soc/intel/alderlake: Implement PMC feature lock") 3. commit c2570dc99800 ("soc/intel/alderlake: Implement PMC soft strap interface lock") 4. commit f021952c4067 ("soc/intel/alderlake: Implement PMC static function lock") 5. commit 457891415380 ("soc/intel/alderlake: Call into PMC IPC to inform PCI enumeration done") BUG=none TEST=Boot to OS on google/rex. Register values in OS - # busybox devmem 0xfe0018d4 32 #bit31 0x80000000 # busybox devmem 0xfe001024 32 #bit21,18,17,4 0x00362610 # busybox devmem 0xfe001818 32 #bit27,22 0x2B4F0004 # busybox devmem 0xfe00104c 32 #bit0 0x00000001 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02nb/intel/i945: Use boolean for gpu_lvds_use_spread_spectrum_clockElyes Haouas
Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-02nb/intel/pineview: Remove unused 'gpu_lvds_use_spread_spectrum_clock'Elyes Haouas
'gpu_lvds_use_spread_spectrum_clock'is only used on i945. Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70147 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}Elyes Haouas
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-02nb/intel/pineview: Use {true,false} instead of {0,1}Elyes Haouas
"use_crt" and "use_lvds" are boolean, so use "true/false". Change-Id: I5b5b42c27351331ad40fbe92fb87390cb1284aa9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70148 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02mb/system76/adl-p: Disable SATA DevSlpTim Crawford
After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in system76/ec@cc3effb6a451 ("board/system76/common: use SLP_S0# pin for modern standby detection"), DevSlp blocks suspend entry. Disable it until it is fixed. Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02mb/system76/adl-p: Add Galago Pro 6 as a variantTim Crawford
The Galago Pro 6 (galp6) is an Alder Lake-P board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - All USB ports - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Windows 10 and Linux 6.1 - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.0.6 - Internal flashing with flashrom v1.2-1087-gde016a17 Not working: - Detection of devices in TBT slot on boot Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02mb/system76/cml-u: Convert lemp9 to a variantTim Crawford
Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-12-02mb/google/herobrine: Update FMD file for multiple ROM sizesMartin Roth
The Piglin & Hoglin boards were built with a couple of different sizes of ROM chips. Despite this, the desire was to use just a single FMD file. The different sizes are already accounted for in Kconfig, so add the Kconfig size here to be used. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-02soc/intel/meteorlake: Allow sending late EOP cmd to CSESubrata Banik
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA common code to skip sending CSE EOP cmd during finalize operation rather uses boot state machine (either payload load or payload boot) to delay in sending EOP cmd to CSE. BUG=b:260041679 TEST=Able to boot to Google/Rex with this patch and observed ~150ms savings in boot time Without this patch: 942:before sending EOP to ME 1,795,702 (354) 943:after sending EOP to ME 1,950,526 (154,824) With this patch: 942:before sending EOP to ME 2,051,406 (35,484) 943:after sending EOP to ME 2,057,583 (6,177) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Allow to perform essential CSE operations post EOPSubrata Banik
This patch allows to send late EOP cmd to CSE (after CSE .final) using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD) if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config. Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()` to make the function name more meaningful with its operation. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-12-02soc/intel/cmn/cse: API to perform essential CSE operations post EOPSubrata Banik
This patch creates an API that can perform essential CSE operation after sending the late EOP command to the CSE and prior booting to OS. Lists of operation are - Perform global reset lock - Put HECI1 to D0i3 and disable the HECI1 if the user selects - Set D0I3 for all HECI devices. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Send EOP cmd from .final aka `cse_final()`Subrata Banik
This patch refactors common code to allow cse_final() function to send EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig. This patch helps cse_final_ready_to_boot() and cse_final_end_of_firmware() function for being meaningful with its operation and let cse_final() being that outer layer to perform three operations based on the selected kconfig. 1. send cse eop command 2. perform cse_final_ready_to_boot() operations 3. perform cse_final_end_of_firmware() operations Additionally, ensures the platform that choose to send EOP late (like JSL and TGL) is not being impacted due to this code refactoring hence, skip calling into CSE.final if SoC selects `SOC_INTEL_CSE_SEND_EOP_LATE` config. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I412291c9378011509d3825f9b01e81bfced53303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02soc/intel/cmn/cse: Create another config for sending CSE EOP cmd lateSubrata Banik
Presently, coreboot supports two instances of sending EOP cmd to the Intel CSE. 1. Sending EOP cmd to CSE during `.final` operation from cse pci driver. 2. Starting with Alder Lake, the recommendation was to send EOP to CSE earlier than CSE `.final` operation. Since then it's referred to as `Sending EOP Early`. This method helped to save the CSE EOP response time significantly. During Meteor Lake platform, CSE EOP response time has become non-deterministic and we have figured that sending EOP command later than CSE .final operation is actually helping to optimize the boot time significantly (around ~150ms savings compared to sending from `.final` ops and ~5sec compared to sending CSE early). Hence, this patch intended to create yet another kconfig for sending CSE late (specifically after `.final` operation). The idea for this newer config is to use the boot state machine for sending CSE EOP cmd. The patch train in this series would add the specific changes to allow sending EOP late and perform other essential operations required prior booting to OS as coreboot decided to skip calling into FSP Notify phase. Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this config is applicable for those platforms. The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake platform will select this newer config from SoC code. BUG=b:260041679 TEST=Able to send EOP command successfully for Google/Taeko. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02mb/google/brya/var/anahera: Adjust I2C5 timing for touchpadWisley Chen
Adjust scl_lcnt, scl_hcnt, sda_hold value for I2C5 to meet touchpad SPEC. BUG=b:260540852 BRANCH=firmware-brya-14505.B TEST=build, checked TP function work normally, and measure the timing meet SPEC tLOW ~1.72 us tHIGH ~0.63 us tHD ~0.69 us fscl 383 kHz Change-Id: I9036a604a90558911c4f8a492db9f1f0f28bf404 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-02mb/google/nissa/var/xivu: Fine-tune eMMC DLLLawrence Chang
Fine-tune eMMC DLL based on Xivu EVT system. BUG=b:256538132 TEST=executed 3000 cycles of cold boot successfully Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69892 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-02mb/google/skyrim/var/frostflow: Enable DPTC supportJohn Su
Enable DPTC support for frostflow. BUG=b:257187831 TEST=emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iac7b8789a5189827fe98cb06328d666300841a5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69931 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01vboot: Allow for comparison of hash without zero-paddingJakub Czapiga
Adjust asserts to allow to store and compare (at S3 resume) hashes without padding to maximum hash length / slot size. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: If6d46e0b58dbca86af56221b7ff2606ab2d1799a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01vboot/vboot_common: Fix vboot_save_data() code exclusion guardJakub Czapiga
Compilers are not optimizing-out code correctly. This patch fixes incorrect behavior by splitting if statement and extracting code to another function, this allowing for better code size optimization and reduction of undefined references. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ia5330efeeb4cfd7477cf8f7f64c6abed68281e30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69761 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-12-01mb/google/brya/var/gaelin: Configure audio in devicetreeRaymond Chung
Refer to brask board to add audio settings for gaelin. BUG=b:253177160 BRANCH=firmware-brya-14505.B TEST=Able to verify audio playback on gaelin with kernel v5.10. Change-Id: Ibc8cacce6cb4b3e55fc7332bb9eb9ac20848fc5b Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01mb/google/brya/var/gaelin: Add camera module settingsRaymond Chung
Modify USB2.0 port[4] settings to support camera. BUG=b:238252678 BRANCH=firmware-brya-14505.B TEST=with brask overlay changes, camera in camera app works Change-Id: I42325b75e129429ee451ded6a2086fd3808e581a Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE`Subrata Banik
This patch ensures dropping of the duplicate macro introduced with 'commit 9e4488ab06fd9c4 ("soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS")' `PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range which can be used as is even in ufs.asl file. BUG=b:252975357 TEST=Build and boot nirwen and see no issues in PLT runs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-01ec/google/chromec: Add DPTC support for host event 1/2/9EricKY Cheng
DTTS is Dynamic Thermal Table Switching Proposal. Add DPTC support for host event lid-open/lid-close/Thermal Threshold. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I156a9d138ccac7f75cc0dd0d827f7a721fcbc782 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67793 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-12-01mb/siemens/mc_ehl2: Disable GSPI2 controllerMario Scheithauer
GSPI2 interface is not used on this mainboard and can be disabled. It will in addition remove the warning of a leftover static device in the log. Change-Id: I6e7462312953d50385ca7bb2f2e0abb8fc3a5886 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-01mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos caseFelix Held
Commit 2c102232e8f7 ("mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte flash size, the amdfw part won't be placed on the expected position, since the cbfs header is in that exact location and cbfstool places the amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for the non-chromeos builds to work around this. TEST=Non-chromeos chausie build now boots and doesn't fail any more before releasing the x86 cores from reset Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/70133 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01mb/google/nissa/pujjo: Add new audio sku configureLeo Chou
Add new audio sku configure for Pujjo board. BUG=b:260538412 TEST=Boot to OS on pujjo and check that audio are configured based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ia9ddc683945002a0b19efd67006e1983b2eb9f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01cpu/intel/model_206ax: Remove fake lapic deviceArthur Heymans
Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic device is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-01cpu/intel/sandybridge: Use enum for ACPI C statesArthur Heymans
Also remove the now unnecessary comments from the devicetree. Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-01soc/intel/meteorlake: Log CSE RO write protection info for MTLKapil Porwal
The patch logs CSE RO's write protection information for Meteor Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL"). BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2022-11-30mb/google/herobrine: Mask out upper bits from sku_id()Shelley Chen
When retrieving the SKU id value through the sku_id() function in mainboard_needs_pcie_init(), we only want the values in the lower 5 bits as we can only represent SKU id up to 27. Everything in the higher bits should be masked out because they are not needed. BUG=b:254281839 BRANCH=None TEST=Make sure that NVMe is not initialized Tested on a herobrine board with SKU id 0 Change-Id: I0e786ec392b5e1484cb2ff6d83a8d4fdd698950c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70164 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30mb/google/herobrine: Only retrieve sku_id from EC onceShelley Chen
Currently, we are getting the sku id from the EC every time we call the sku_id() function. However, this will never change so we only need to retrieve it once. Inserting exit condition if sku id is already set, then don't get it from the EC again. Also, removing the ram_code function, which does nothing right now. There is already a weak stub_function for this in src/lib/coreboot_table.c that already does the same thing. BUG=b:260740438,b:182963902 BRANCH=None TEST=make sure image still boots to login on herobrine device Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
2022-11-30mb/amd/birman/gpio: Configure birman GPIOsFred Reitberger
Configure birman GPIOs per schematic 105-D67000-00B v0.7 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I5459efb38431e568e25405c440b5b9cf1354f02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-11-30soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parametersEricKY Cheng
Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for dynamic table switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-11-30mb/system76: Rename gaze16 to tgl-hTim Crawford
Change-Id: Icbf9348447b9e7acc0caa8082cf5dd00853da37a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2022-11-30arch/x86: Buildtest clang targets with VBOOT_STARTS_BEFORE_BOOTBLOCKArthur Heymans
TESTED: google/vilboz boots with clang build. Change-Id: Ie115c27b4cb0b8f83d7647bdd27ffcbac9376399 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69746 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30arch/arm/armv7: Disable generating neon FPU codeArthur Heymans
By default clang generates code with neon instructions. These are not supported on all arm targets so default to fpu=none. Change-Id: I48fc505107d131466be39f466151df62b2d2bd0b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69745 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30arch/arm/eabi_compat.c: Add eabi_clrX and eabi_memcyXArthur Heymans
Clang generated code uses this for zero initialized variables. Change-Id: I460a0096918141c1cf8826bdf1853a3aa3aecff8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-30arm/armv7/Makefile.inc: Fix processing ld files with clangArthur Heymans
When processing linker scripts clang needs to be set for the proper target or it gets confused by other options. Change-Id: I040aa14a06c728269ca1026e0002392e5ac8fef8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69744 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30ec/google/chromeec: Add packed attribute to structs in unionArthur Heymans
Clang warns about structs inside a union also needing the packed attribute. This files is copied from the chromeec project, so it adds comment next to the coreboot specific changes as a reference. TEST: google/vilboz remains the same with BUILD_TIMELESS=1 and gcc. Change-Id: I8b5233618081db86caedcb2d14870974e109ed9b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-11-30mb/google/brya: Enable Fast VMode for brya0, skolas and skolas4esJeremy Compostella
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. FSP silicon discards the request if the Voltage Regulator or SoC does not support the feature. BUG:b:259057787 TEST:Verify that the feature is enabled by reading from pcode No PnP regression observed BRANCH=firmware-brya-14505.B Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7e318534f1429af8ec06048430966344ddd346a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69579 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetreeArthur Heymans
Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30nb/intel/sandybridge: Add a chipset devicetreeArthur Heymans
This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30soc/intel/meteorlake: Rename method is_eom to is_manufacturing_modeKapil Porwal
BUG=none TEST=Build and boot to google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-30mb/google/brya/var/zydron: Add mipi hi556 camera supportDavid Wu
This patch supports multiple camera modules based on FW_CONFIG. BUG=b:251235140 TEST=Test the changes with ov2740/hi556 camera. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib0a4f46d889e9f6c2898efee6825cf2d02252d87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jim Lai <jim.lai@intel.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-11-30mb/google/brya: Enable crashlogGaggery Tsai
This patch enables crashlog for all brya projects. BUG=b:190756531, b:259978562 BRANCH=None TEST=emerge-brya coreboot chromeos-bootimage & ensure the crashlog PCIe device 0xa.0 is enabled and intel-pmt kernel driver is loaded. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ib632c8ac9ea7a4f0e0b08b96eb149f8ef1386be0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68526 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-11-30mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4zhourui
This change disables unused PCIE RP8 and CLKSRC4. Without this change sasukette cannot enter into s0ix properly. BUG=b:259891452 TEST=Build and verified in sasukette Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-30nb/intel/e7505: Hook up PCI domain and CPU ops to devicetreeKyösti Mälkki
Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70058 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-30/: Remove extra space after commaElyes Haouas
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29Revert "src/arch/x86: Use core apic id to get cpu_index()"Arthur Heymans
This reverts commit 095c931cf12924da9011b47aa64f4a6f11d89f13. Previously cpu_info() was implemented with a struct on top of an aligned stack. As FSP changed the stack value cpu_info() could not be used in FSP context (which PPI is). Now cpu_info() uses GDT segments, which FSP does not touch so it can be used. This also exports cpu_infos from cpu.c as it's a convenient way to get the struct device * for a certain index. TESTED on aldrvp: FSP-S works and is able to run code on APs. Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29soc/intel/alderlake/acpi.c: Don't look up coreboot CPU indexArthur Heymans
The coreboot CPU index for a lapic is arbitrary: it depends on which CPU obtains a spinlock first. Simply using an increasing index will result in consistent ACPI tables across each boot. Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29mb/google/brya: Add ACPI DmaProperty for ethernet devicesKapil Porwal
Add ACPI DmaProperty for ethernet devices. BUG=b:259716145 TEST=Verified SSDT on google/osiris. Before: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) } } After: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I647593fd02644d30cd21b60d8305c0ec55dc64cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/70017 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29drivers/net/r8168: Add support for ACPI DmaPropertyKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/osiris. Before: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) } } After: Scope (\_SB.PCI0.RP01) { Device (RLTK) { Name (_HID, "R8168") // _HID: Hardware ID Name (_UID, 0xD0E889DD) // _UID: Unique ID Name (_DDN, "Realtek r8168") // _DDN: DOS Device Name Name (_ADR, 0x00000000) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x07, 0x03 }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"), Package (0x01) { Package (0x02) { "DmaProperty", One } } }) } } Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I647230082362b1093b63793a201eba23a6289121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70016 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29mb/google/brya/var/kinox: Add ACPI DmaProperty for WLAN deviceKapil Porwal
BUG=b:259716145 TEST=TBD Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ifaa0912b38129ed2db01fb78ed39c0db89e746fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/70018 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29soc/intel/cmn/block/pcie/rtd3: Add support for ACPI DmaPropertyKapil Porwal
BUG=b:259716145 TEST=Verified SSDT on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I921b06e8d35ddac0bc8175b13a33c84515b282a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70028 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29drivers/{wifi,wwan}: Use helper function to add DmaProperty in _DSDKapil Porwal
BUG=b:259716145 TEST=Build google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I991bc822fbb72cfaa9485abe882950fc7bcef498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70023 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29acpi: Create a common method to add DmaPropertyKapil Porwal
Create a common method to add DmaProperty. BUG=b:259716145 TEST=Verified SSDT on google/osiris. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I75b3f22ad29f90f3c3b251bd0d70bae9d75f71fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/70022 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29mb/google/skyrim/var/frostflow: Update RAM ID tableFrank Wu
Add new ram_id:0100 for memory Samsung K3LKBKB0BM-MGCP. Add new ram_id:0101 for memory Samsung K3LKCKC0BM-MGCP. The RAM ID table has been assigned as: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNCP3MLYR-N6E 1 (0001) MT62F2G32D8DR-031 WT:B 2 (0010) H9JCNNNFA5MLYR-N6E 3 (0011) K3LKBKB0BM-MGCP 4 (0100) K3LKCKC0BM-MGCP 5 (0101) BUG=b:254758998 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I8ff879ff7185f5a0ca1b9632820aba3b0f5d02c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-11-29mb/google/skyrim/var/frostflow: Set Package Power ParametersJohn Su
Set Package Power Parameters from AMD DevHub document #57316. "stapm_time_constant_s" = "200" BRANCH=none BUG=b:257187831 TEST=emerge-skyrim coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69565 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-11-29mb/google/skyrim: Move common DPTC values to devicetree.cbTim Van Patten
The Skyrim devices share a common set of DPTC values to enable booting with low/no battery. Rather than duplicating them in each variant's overridetree.cb, move them into the baseboard/devicetree.cb. BUG=b:217911928 TEST=tast run <IP> power.ShutdownWithCommandBatteryCutoff Change-Id: I20f0a8259c2fc986da23026da88feadd69942046 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69904 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29{soc/intel/cmn/pcie, mb/google/volteer}: Rename `is_external` variableKapil Porwal
Name a variable based on its utility. `is_external` variable adds `ExternalFacingPort` _DSD property to an ACPI device hence rename it to `add_acpi_external_facing_port`. BUG=b:259716145 TEST=Build google/rex with this flag and verify it in SSDT at runtime. SSDT snippet: Name (_DSD, Package (0x04) // _DSD: Device-Specific Data { ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"), Package (0x01) { Package (0x02) { "HotPlugSupportInD3", One } }, ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), Package (0x01) { Package (0x02) { "ExternalFacingPort", One } } }) Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28sb,soc/intel: Drop spurious SMI entry messageKyösti Mälkki
The message only makes sense if ACPI PM base address is allowed to be dynamic. If requested, it can be logged in common code. Change-Id: Iad7a60098c0391cc23384035af49e373dad90233 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-11-28sb/intel/common: Rename TCO timeoutKyösti Mälkki
Rename TCO1_TIMEOUT to TCO_TIMEOUT to match rest of the tree. Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-11-28sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-28sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLITKyösti Mälkki
Tree is inconsistent with the use of TCO register space offsets and related preprocessor defines. The legacy space was offset from ACPI PM base by 0x60, but this changed with later platforms. The convenient way is to define the TCO registers relative to its base address and subtract 0x60 here, but this change cannot be easily done tree-wide or in one go. For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until all platforms use a clean style of tco_{read,write} accessor functions instead of {read,write}_pmbase16(), or worse, inw/outl(). Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-28aopen/dxplplusu: Support SMM_ASEG and SMM_TSEGKyösti Mälkki
Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occurring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 05:38:41 +0000