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2023-08-24mb/google/brya/var/osiris: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/omnigul: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/mithrax: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/rex/var/karis: Disable GSPI0Tyler Wang
According to the schematic, karis does not have a SPI touchscreen, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-24mb/google/brya/var/marasov: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/kano: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/gimble: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/felwinter: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24mb/google/brya/var/crota: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-24mb/google/brya/var/banshee: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-24soc/nvidia: Fix incorrect SPDX licenseMartin Roth
The SPDX license header for this file did not match the license text in the file. Update the SPDX header and remove the license text. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ifc0db79e43df6d14b80b0ad3061fe42de17ed90f Reviewed-on: https://review.coreboot.org/c/coreboot/+/77379 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-24soc/intel/jasperlake: Use boolean type where applicableMichael Strosche
Change-Id: If3c2e5bd9ee7e0f77d0c39ffe2ca9ad17b77d9bd Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-23mb/amd/mayan: Enable the DT and M.2 SSD1 PCIE slotsAnand Vaikar
Program the EC GPIOs to enable the DT or M.2 SSD1 PCIe slots based on the config option selected. Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-08-23soc/intel/xeon/spr: Improve RMT configurationNaresh Solanki
Set EnforceDdrMemoryFreqPor to 0 for RMT builds. This is needed for proper functioning when EnforcePopulationPor is set to 1. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Icf4fe01ac9b546830334717dbfa53782d2a85ba1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23soc/mediatek/mt8188: Simplify pmif init flowSen Chu
Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx", MT8188G used in ChromeOS project does not support clock hardware monitor. Thus, we can simplify the initialization flow by removing the hardware default value check. BUG=b:292866009 TEST=emerge-geralt coreboot BRANCH=none Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-23mb/google/brya: Create quandiso variantRobert Chen
Create the quandiso variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:296506936 BRANCH=firmware-nissa-15217.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_QUANDISO Change-Id: I846c39260e2db504d7bec6e81a8317b6824c17f4 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23mb/google/rex/var/karis: Remove WWAN temperature sensorTyler Wang
According to the schematic, karis does not have a WWAN temperature sensor, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ic82c6cfec067faa37d452bed5c4977402a2139a5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77284 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-23mb/google/dedede/var/pirika: Add USB2 PHY parameters for Type-A/Type-CDaniel_Peng
This change are added fine-tuned USB2 PHY parameters to improve the USB2 eye diagram result. BUG=b:296493887 BRANCH=firmware-dedede-13606.B TEST=Local build bios successfully. And verified the USB2 eye diagram test result. Change-Id: I915fe689883267901e8faba28632345d8c227c28 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77359 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-23mb/google/brask/var/constitution: Separate wifi sar tableMorris Hsu
Separate constitution and intrepid wifi sar table in variant.c BUG=b:291859402 BRANCH=firmware-brya-14505.B TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I0f89b3d5f5252a2b55bad4d91ad4ab9ec7519c50 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77242 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-22mb/google/brya/var/bb/brask: enable HDMI gpios earlyNick Vaccaro
Add some HDMI-related gpios that are needed for early sign-of-life to the early_graphics_gpio_table array so that SOL will show up on HDMI ports. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds without error. Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-22soc/qualcomm: Add missing newlines for logsYu-Ping Wu
Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21soc: Remove SOC_SPECIFIC_OPTIONSElyes Haouas
Move specific options under the boolean and remove dummy SOC_SPECIFIC_OPTIONS. Change-Id: I6ae52ceb61489e5a050a60d1fbbf4250960407eb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-21mb/google/rex/var/karis: Remove world facing cameraTyler Wang
According to the schematic, karis does not have a WFC. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I9b4ecf2e96c77c131a60e48614d792370dd33423 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-21ec/google/wilco/superio: Adjust PS2K HID/CID for Windows driversMatt DeVillier
Allows coolstar's Windows overlay drivers to attach, while not affecting operation under Linux or ChromeOS TEST=build/boot Win11, Linux 6.x on google/drallion Change-Id: I30ab2e9da00743c4d7086aac94652be46040f36d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77305 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco/acpi: Read message when notifying UCSICoolStar
Allows the EC to be properly notified of type-c events like charger wattage too low (eg), TEST=build/boot Win11, Linux 6.x on google/drallion Change-Id: I7a4130cf6f8c24e3f91e327adf1f3e563322c0af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77282 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco: Correct scope of UCSI ACPI deviceCoolStar
Set the USCI device scope to _SB and set HID to USBC000 so Windows driver attaches. This matches the ACPI used by the non-Chromebook version of the Dell Latittude 7410 (which uses the same EC). TEST=build/boot Win11 on google/drallion Change-Id: If482fa4a4856c7bc085795bc72b35ebefe2f15c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77281 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21ec/google/wilco/acpi: Unhide GOOG000C ACPI deviceMatt DeVillier
Allows coolstar's Windows drivers to attach. TEST=build/boot Win11 on google/drallion Change-Id: Idd339811563cd2cdfc4cc31bc5660a62f4e36a66 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-21ec/google/wilco/acpi/dptf: Fix mutex synclevelMatt DeVillier
Both Windows and MacOS get cranky if the Mutex synclevel is non-zero, aborting any Acquire() call with Mutex param that has a non-zero synclevel. TEST=build/boot Win11 on google/drallion, verify DPTF driver loaded and functional. Change-Id: Ie77e9ed04658b508b2063ae219afcdc0ac465c58 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77279 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21soc/intel/alderlake: add GPIO definitions for RPL PCHTim Crawford
The RPL PCH uses a different ACPI Device ID than ADL PCH. Ref: Intel 700 Series Chipset Family PCH Datasheet, Volume 1 (#743835) Change-Id: I03f47a43ff985213ad617e834db7f974f687d877 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21mb/msi/ms7e06: Add support for MSI PRO Z790-P DDR4/DDR5 (WIFI)Michał Żygowski
TEST=Boot Ubuntu 22.04 on MSI PRO Z790-P (DDR5 variant) with Intel Core i5-13600K using UEFI Payload. Change-Id: Id2c77621d24bb097b930342eb1961270854d5f68 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76325 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOTMichał Żygowski
Similar situation happened last year when IoT FSP for ADL-S came out before the Client FSP variant: https://github.com/intel/FSP/issues/83 It seems IoT FSP publishes the MemInfoHob.h file much later due to legal reasons. Hack the missing file to get the builds using RPL-S IoT FSP from repo working properly. This change could be merged, subject for later revert (when the header file is published). Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSPMichał Żygowski
PchPcieClockGating and PchPciePowerGating UPDs are not yet available in RPL-S IOT FSP. It also looks like those UPDs are not generally available in all public RaptorLake FSP headers yet, so guard it against SOC_INTEL_RAPTORLAKE to avoid build errors. Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-08-21soc/intel/broadwell/pch/Kconfig: Remove dummy PCH_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I21db0474157ba20cdf3eaef086aaf29fde29d6c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76701 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21mb/google/skyrim/var/crystaldrift: drop commented out line in DTMatt DeVillier
Line is a duplicate, commented out. Drop it as it serves no purpose. Change-Id: Id35bdea0915ca47cac4f38ede6ccbf2f2fb59f47 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77304 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-21device/dram: add DDR4 RCD I2C access functionsKrystian Hebel
Registering Clock Driver (RCD) is responsible for driving address and control nets on RDIMM and LRDIMM applications. Its operation is configurable by a set of Register Control Words (RCWs). There are two ways of accessing RCWs: in-band on the memory channel as MRS commands ("MR7") or through I2C. Access through I2C is generic, while MRS commands are passed to memory controller registers in an implementation-specific way. See JESD82-31 JEDEC standard for full details. Change-Id: Ie4e6cfaeae16aba1853b33d527eddebadfbd3887 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-21soc/intel/apollolake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: I6f2dc0fcc4392f77b8011221c0cf22af5da45172 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-21cpu/x86/smm: Don't save EFERArthur Heymans
The EFER MSR is in the SMM save state and RSM properly restores it. Returning to 32bit mode was only done so that fxsave was done in the same mode as fxrstor, but this is no longer done. See commit 1efca4d570 (cpu/x86/smm: Drop fxsave/fxrstor logic) TESTED on qemu: the smihandler works fine. Change-Id: Ie0e9584afd1f08f51ca57da5c4350042699f130d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-21device/dram: add DDR4 MRS commandsKrystian Hebel
Change-Id: I9d4f048c859bc89897d50a5a07468c3375aa1dcf Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-21vc/intel/fsp/mtl: Add PsysPmax FspmUpdKilari Raasi
This patch adds the PsysPmax Upd to FSPM header file. FSPM: 1. Add 'PsysPmax' UPD 2. Address offset changes BUG=b:295126631 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I892b8c2d75e58a42d3f85006237827da01426ea7 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77244 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21meteorlake/include/soc/iomap: Remove unused HPET_BASE_ADDRESSElyes Haouas
Remove unused HPET_BASE_ADDRESS. It is already defined at <arch/hpet.h>. Change-Id: I8c517283e56915873b8e1798571642fd9d8a5764 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-20soc/samsung/exynos5250/clock: Remove space before semicolonElyes Haouas
Change-Id: Id0adfd0e25806aef836f75e83ff86a55a5d799d6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-20soc/intel/bdw/pch: Remove SOC_INTEL_BROADWELL conditionalElyes Haouas
broadwell/pch/Kconfig is sourced if SOC_INTEL_BROADWELL is true. So remove 'if SOC_INTEL_BROADWELL' condition and duplicated 'INTEL_LYNXPOINT_LP' Change-Id: I9b5676fd232b47e9d5f89f7faffdfd5d2c76984e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76699 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20ec/google/wilco: Fix ACPI EC RAM read/write opsMatt DeVillier
While debugging lack of battery status under Windows, it was discovered that the read/write flags in the args to the EC RAM 'ECRW' method were not being correctly identified. Force set them from the R() and W() methods which call ECRW() so those calls are processed properly. TEST=build/boot Windows on google/drallion, verify battery status, charging, etc are all reported properly. Change-Id: I2a40b8d50ba65213813c781e53b56cc1a8b8debf Signed-off-by: Coolstar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-20soc/intel/mtl: Enable IOE_PMC supportDinesh Gehlot
IOE_PMC support was not enabled on Meteor Lake platforms. This patch adds the bare minimum hooks to initialize and allocate a memory region for IOE operations. Additionally, this patch moves those IOE operations to a newly included IOE-specific file, Previously, PMC was responsible for these operations. BUG=b:287419766 TEST=build and verified on google/rex. Change-Id: I8bbc0b8a3e32dad5404c80bc7717ef07e3ec60b9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77261 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20mb/intel/mtlrvp: Disable C1-state auto demotion for mtl-rvpSukumar Ghorai
C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter PC2 and lower state in camera preview case and save platform power. Note: C1 demotion heuristics used EPB parameter to balance between power and performance, i.e. low threshold when EPB is low in-order to get C1 demotion faster and vice-versa. ChromeOS operates at default EPB=0x7 (low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits than expected (similar to AC mode) and losing power respectively. ref. https://review.coreboot.org/c/coreboot/+/76827 BUG=b:286328295 TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also verified PC residency improvement ~10% in camera preview case. Change-Id: I1b2db634176f0072c535608c5600846a9086fef1 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-20mb/intel/archercity_crb: Set SMM console log level via VPDJohnny Lin
Change-Id: Ic7d51037d527f95e8664ad04e328fc27901cacde Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71993 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20mb/google/rex: include Elan HID over SPI ASL for Rex4ESEran Mitrani
Existing code did not include the HID over SPI for rex4es. This CL corrects this issue. BUG=None TEST=Tested on Rex Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I02f7c4b68cfee2ebb202581c9f031af99ab4b6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77245 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-20soc/intel/alderlake_n: Allow using the microcode repoFelix Singer
Allow users of Alderlake N processors to use the microcode repository and also add their related microcode blob to the list of microcodes which should be included in the coreboot rom. Change-Id: I11c9cb13fa81118bfcb819bad5fb39731c7e3e76 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2023-08-19drivers/intel/fsp2_0: Fix extraneous text after else directiveSubrata Banik
Fix the issue by adding the "ifeq" keyword which makes the extraneous text a correct conditional directive. Change-Id: Id8a8aa7acfdaeb0549f417fb013b2535a7298045 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77286 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-18mb/google/brya: Alphabetize board listings in Kconfig.nameMatt DeVillier
Change-Id: I551d71d968abb6a9cadbc0f87bc9258768db1fca Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77275 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/brya: Alphabetize selections inside Kconfig.nameMatt DeVillier
Change-Id: I7ed982c9dcf755c97f26cc43b3dc05b898e4150a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77274 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/brya: Add VBT data files for variantsMatt DeVillier
Add data.vbt files for all variants supported by current brya, brask, and nissa recovery images. Select INTEL_GMA_HAVE_VBT for all variants which currently have a VBT file. TEST=build/boot various brya variants (banshee, osiris, redrix) Change-Id: Ic66f91e264d37c3742cb17994f637604d77a1576 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77144 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18commonlib: Remove unused CBMEM IDSubrata Banik
This patch removes unused CBMEM ID named `CBMEM_ID_CSE_PARTITION_VERSION`. BUG=b:285405031 TEST=Able to build and boot google/rex w/o any compilation error. Change-Id: I83f53b7f64bdef62a8ee2061d5a9c9e22bc4b8a4 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77179 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/rex: Dump ISH version for `rex_ec_ish` variantSubrata Banik
This patch selects `SOC_INTEL_STORE_ISH_FW_VERSION` config to dump the ISH version as part of the .final hook. BUG=b:285405031 TEST=Able to build and boot google/rex_ec_ish. Verify the ISH version is same as MFIT ISH version section. > cbmem -c | grep "ISH" [DEBUG]  ISH version: 5.6.0.28821 Change-Id: I052af85ad836ab81ff6c510bb74e042b11940a65 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77178 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18soc/intel/meteorlake: Implement `soc_is_ish_partition_enabled` overrideSubrata Banik
This patch implements `soc_is_ish_partition_enabled()` override to uniquely identify the SKU type between ISH and non-ISH to conclude if ISH partition is enabled and need to retrieve the ISH version from CSE FPT by sending a HECI command. BUG=b:285405031    TEST=Able to uniquely identify the ISH SKUs while booting     to google/rex_ec_ish to dump the ISH version. Change-Id: I48358ad9e2e582e8b2274cbf4655de01f8792e6c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77177 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18{driver, soc/intel/cmn/cse}: Refactor ISH FW Version implementationSubrata Banik
This patch uses the CSE firmware specific data to store Intel ISH firmware related information. Sending an ISH partition version information command on every boot cycle would impact the overall boot performance. This information is used by the auto-test framework to ensure the ISH firmware update is proper for in-field devices. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified ISH FW version is getting displayed across warm resets without impacting the boot time. Change-Id: I0242c26dd90d834815799f54740d8147ff9d45b7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-08-18soc/intel/cmn/cse: Display CSE RW FW version by default for LITE SKUSubrata Banik
This patch selects SOC_INTEL_STORE_CSE_FW_VERSION config by default for CSE LITE SKU. It helps to dump the CSE RW firmware version which further consumed by auto-test infrastructure to ensure CSE RW firmware update is successful. BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. Change-Id: Iba5903c73c0a45b01e6473714e0d5f759c061825 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77175 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-18soc/intel/cmn/cse: Refactor CSE RW FW Version implementationSubrata Banik
This patch introduces a CSE firmware specific data in order to store Intel CSE and associated firmware related information which requires a sync between Pre-RAM and Post-RAM phase. This information will be used further to retrieve currently running CSE RW firmware instead of fetching the version information by sending a HECI cmd (which consumes 7ms-15ms depending upon the CSE operational state). Current implementation attempts to simply the CSE RW FW version store and retrieval operations as below * CSE sync in romstage (aka Pre-RAM) - Relying on .bss segment to store the CSE info data in absence of real physical memory and sync back into the CBMEM once available (after FSP-M exits). * CSE sync in ramstage (aka Post-RAM) - Directly stored the CSE RW version into the CBMEM (as CBMEM is online). BUG=b:285405031 TEST=Able to build and boot google/rex. Verified CSE RW FW version (for LITE SKU) is getting displayed without impacting the boot time. w/o this patch: 10:start of ramstage         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) w/ this patch: 10:start of ramstage                         722,257 (43) 17:starting LZ4 decompress (ignore for x86)  723,777 (1,520) Change-Id: Ia873af512851a682cf1fac0e128d842562a316ab Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77174 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2023-08-18nb/intel/haswell/nri: Only do CPU replacement check on cold bootsAngel Pons
CPU replacement check should only be done on cold boots. Original-Change-Id: I98efa105f4df755b23febe12dd7b356787847852 Original-Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I3c79f4e55e23c0b98da7661988e3ff8b50d6300d Reviewed-on: https://review.coreboot.org/c/coreboot/+/77048 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/poppy: add libgfxinit support for variantsMatt DeVillier
Add libgfxinit support for Nami, Nautilus, and Soraka. Panel timing values taken from default panel selection extracted from the respective VBTs. TEST=build/boot nami w/edk2 payload and libgfxinit selected Change-Id: If0ca389487338c47f9d8de990acf591c6907eaa9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77268 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-18mb/google/dedede: Add ACPI display brightness supportMatt DeVillier
Add support for ACPI display brightness controls, so that panel adjustment is available under Windows. TEST=build/boot Win11 on google/magpie, verify panel brightness controls available and functional. Change-Id: I66daa6bbca15046994dff83bee6e7cf99aae0b33 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77271 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/fizz/endeavour: update VBTMatt DeVillier
Update VBT with file extracted from FW_MAIN_A region of firmware file bios-endeavour.ro-13259-80-0.rw-13259-144-0.bin TEST=build/boot endeavour Change-Id: Ibf7b35c4e59c6fe816cf036e637483de75d6ecd4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-18vc/intel/fsp/mtl: Update header files from 3223.80 to 3292.83Dinesh Gehlot
Update header files for FSP for Meteor Lake platform to version 3292.83, previous version being 3223.80. The patch doesn't include any function changes, only a few comments and headers have been changed. BUG=b:295126631 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I27f88732bfafd4732ea39bf9c54e18341dd26cf9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-18mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control BUG=b:291217859 TEST=emerge-rex coreboot Change-Id: I6e6ad653157dc87a7d87b5ffc4f9590991a7c284 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76678 Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/volteer: Add ACPI display brightness supportMatt DeVillier
Add support for ACPI display brightness controls, so that panel adjustment is available under Windows. TEST=build/boot Win11 on google/drobit, verify panel brightness controls available and functional. Change-Id: Ic0c026ae09b3fde648db4bdeb4971423953c96a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77143 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex: Update ISH GPIO's configurationBernardo Perez Priego
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled, loaded, and functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I778251aadef4499427fc9855adfdd9cade3a3e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77235 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17soc/intel/alderlake: Set PchHdaSdiEnable for Alder LakeSean Rhodes
This UPD does exist for Alder Lake, so set it there also. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If2f405804ab675aaf6dbf8b12d149566055b9eef Reviewed-on: https://review.coreboot.org/c/coreboot/+/77125 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-17mb/starlabs/starbook/rpl: Fix the Thunderbolt cmos optionSean Rhodes
For Thunderbolt to be disabled, `UsbTcPortEn` and `TcssXhciEn` also need to be disabled. Change-Id: Ie02c1e0ea7583bbd78e25c8184e2cdf2b6281741 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-17mb/google/brya: Allow to show early splash screen using GFX PEIMSubrata Banik
This patch chooses to show the early splash screen which is an OEM feature. The current implementation is relying on the Intel FSP GFX PEIM to perform the display initialization. Having this feature allows the platform to show the user notification with 500ms since boot compared to traditional scenarios where first user notification is coming from kernel (typically ~3sec+ after cpu reset). Eventually this feature will help to improve the user experience while booting Intel SoC platform based chromeos devices. BUG=b:284799726 TEST=Able to see the early splash screen on google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2449bf97d6c82cb08f603b29643cc261738b5379 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17soc/intel/alderlake: Add provision to show pre-boot splash screenSubrata Banik
This patch adds the ability to show a pre-boot splash screen on Meteor Lake systems using FSP-S. The patch calls into `fsp_convert_bmp_to_gop_blt()` when the `BMP_LOGO` config is enabled. This function converts a BMP file to a BLT buffer, which is then used by FSP-S to render the splash screen. Additionally, increase the heap size (malloc'able size) upto 512KB (when BMP_LOGO config is enabled) to accommodate high resolution logo file. BUG=b:284799726 TEST=Able to see splash screen while booting google/marasov with BMP_LOGO config enable. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9f4d1bc0aa991e784624ca19ba96a259ab8ddfa6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17mb/google/nissa/var/yaviks: Disable SD card based on fw_configWisley Chen
Disable pins for SD card based on fw_config. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I0b383d1b00056a69ba925bb5203dc4ca026b9d8e Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77105 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17sb/intel/lynxpoint/acpi: Update xHCI workarounds for LPTAngel Pons
Backport commit cf544ac (broadwell: Remove XHCI workarounds on WPT). Newer Lynxpoint reference code shows LPT-H also uses these workarounds. Also, add the `ISWP` object (Name or Method) to test for WildcatPoint. Change-Id: I76bc07e585e8af292c7316442760d1cfabf1e9c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46960 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-17mb/google/rex/var/karis: Update USB settingsTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ia4bd6fe02ffa62ed8aeffb188de5c4c4b64900ff Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77106 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-17mb/google/rex/var/karis: Remove SD card and ISHTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I1575ee1d7e4c834ad15f60a3b7d63c041a8d4890 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77007 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Modify SSD settingsTyler Wang
Follow schematic, modify SSD related settings. BUG=b:294155897, b:289880020 TEST=emerge-rex coreboot Change-Id: Ie9c228ed7ccc83afaa8365f89c1d5cdedc4f0c8c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77006 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Copy devicetree from rex0Tyler Wang
Add initial devicetree config for karis. It's copied from rex0 and only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I89585a86e8afe636d3927a21a64451b59591acda Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-17mb/google/rex/var/karis: Copy Kconfig from rex0Tyler Wang
Add initial Kconfig settings for karis. Copied from rex for support audio codec, SD card and ISH. It's only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I4bcea7f5e678f2862b3477206838786ff5bad173 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77182 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Add TPM supportTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I4076ee4a16b7260db464760d5a19e1144081bab8 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77181 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Copy GPIO from rex0Tyler Wang
Add initial GPIO settings for karis. It's copied from rex0 and only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ic1e52a1eaca0aa5f68661826a70ccb89d6e302dc Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77003 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/ovis: Fix Bluetooth configurationJakub Czapiga
Bluetooth was missing USB configuration, so add it according to the schematics. BUG=b:290111789 TEST=Boot on Ovis and list bluetooth with `hciconfig` Change-Id: Iee8a3368bbad6c5b49f09ec7335d77ed63ecc784 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77146 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17soc/intel/meteorlake: Enable LZ4 compression for logo CBFS fileSubrata Banik
This patch selects LZ4 decompression for logo CBFS file. Able to save 2ms of the boot time when HAVE_FSP_LOGO_SUPPORT config is enabled. However, the compressed BMP logo size is increased by ~2KB. Raw BMP Image size is ~97KB. BUG=b:284799726 TEST=Able to see pre-boot splash screen while booting google/rex with 32MB (W25Q256JWEIM) SPI-Flash. w/o this patch: sudo cbfstool image-screebo4es.bin print -r FW_MAIN_A FMAP REGION: FW_MAIN_A Name Offset Type Size Comp ... ... logo.bmp 0x167480 raw 6172 LZMA (97078 decompressed) ... 15:starting LZMA decompress (ignore for x86)  849,090 (1,022) 16:finished LZMA decompress (ignore for x86)  851,207 (2,116) w/ this patch: sudo cbfstool image-screebo4es.bin print -r FW_MAIN_A FMAP REGION: FW_MAIN_A Name Offset Type Size Comp ... ... logo.bmp 0x167480 raw 8568 LZ4 (97078 decompressed) ... 17:starting LZ4 decompress (ignore for x86)   849,419 (1,279) 18:finished LZ4 decompress (ignore for x86)   849,559 (140) Change-Id: I856c39146a5ec0faf44c1cd37fa7c0d7296bf673 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17drivers/intel/fsp2_0: Add configurable compression for logo cbfs fileSubrata Banik
This patch adds a new configuration option to allow the compression algorithm for the logo cbfs file to be specified. By default, the logo cbfs file is compressed using LZMA. However, enabling LZ4 compression can save ~2ms of boot time when the BMP_LOGO config is enabled. This patch verified that the logo cbfs file can be booted using either LZMA or LZ4 compression. BUG=b:284799726 TEST=Able to boot google/rex and verified firmware splash screen using either LZMA or LZ4 compression. Change-Id: Ib0aa5320632ae3f734004d2b1d495af11c2e1928 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-17soc/intel: Update all references to ESE as ISSEUsha P
Intel has rebranded ESE as ISSE (Intel Silicon Security Engine),so all references to ESE is updated to ISSE in the current coreboot code. BUG=None TEST=Build all the variants based on Intel Meteor Lake SoC Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I1f8785704706d56a35e94a0f3386bc551cd1f263 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77241 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-16mb/google/skyrim: Enable SPL fusing on crystaldriftYunlong Jia
Enable Crystaldrift platform to send the fuse SPL (security patch level) command to the PSP. BUG=b:279499517 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1d41505e64bf54ad911ad7d287263013a9c458db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-08-16soc/intel/alderlake/chip.h: Use boolean type where applicableMichael Strosche
Change-Id: If26184058536590b70bbb03209913118307ff6c5 Signed-off-by: Michael Strosche <michael.strosche@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76830 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-16mb/google: Re-arrange mainboard_smi_sleep()Kyösti Mälkki
Change the order of enabling EC and GPE wake sources, so it comes more obvious we can use existing chromeec handlers without changes. Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74604 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/slippy: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I752d5644d6140e5a6d6f53543bbbc5ef7281f3b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74824 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/slippy: Re-arrange mainboard_smi_sleep()Kyösti Mälkki
Change-Id: I9ac7293e03bba773753f48163aca9385f819a71b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74822 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/auron: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I6b67358431d8c2b9f88b4e8948baf3497b902fed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74821 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16ACPI: Add usb_charge_mode_from_gnvs()Kyösti Mälkki
Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-16mb/google/nissa/var/pirrha: Update Kconfig for pirrhaSeunghwan Kim
Add support MIPI driver and DA7219 driver for pirrha. BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I6a8f0f942a54909627aad3bf447dc7225f57cef2 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-16mb/google/nissa/var/pirrha: Update DRIVER_TPM_I2C_BUS for pirrhaSeunghwan Kim
Correct TPM I2C BUS number for pirrha BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I9fa0b46db752d02368f19ce8c58a4122b371c100 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77164 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/nissa/var/pirrha: Increase VBT_DATA_SIZE_KB to 10Seunghwan Kim
Increase VBT_DATA_SIZE_KB to 10 since pirrha uses bigger VBT file. It includes MIPI power sequence data for panel. BUG=b:295112773 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: Ib6c293ccb4a8df3ebbd2271e7db2de4e7bd9cc3e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77163 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16vendorcode/fsp: Rename GLK to Gemini Lake to match other SOCsSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic559b78e6444acec36d437fe3c139b692a3f4d0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77126 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-08-16mb/google/nissa/var/pirrha: Update DQ/DQS tableSeunghwan Kim
BUG=b:292134655 BRANCH=nissa TEST=Boot to OS on pirrha ADV board Change-Id: I65429ec8d30b4458511f7c0138652528aadfde25 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76892 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-16mb/google/nissa/var/yaviks: Add elan i2c touchscreenWisley Chen
Implement support for elan i2c touchscreen and use fw_config to pick between i2c or HID-over-i2c touchscreen. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=build and verified touchscreen work Change-Id: I32ba97f5e5f6d280d1ae47da22360fde421a26c0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-15mb/google/beltino/smihandler: Remove 'return' from void functionElyes Haouas
Change-Id: Iadd8a0f3bae07918990cba8f33eb1e65f4e1977a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77188 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-15sb/amd/pi/hudson: Swap the 3-clause BSD license for an SPDX lineMartin Roth
This makefile had a 3-clause BSD license. Swap the full license text with an SPDX header. Looking through the history determined that it had copyright lines, so those were added back as the license required. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I53a746de6d2e6b60c41415531b7f261e02908b28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77151 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-08-15mb/google/dedede/var/boxy: update DPTF thermal settingsStanley Wu
Update DPTF thermal settings from thermal team suggestion: 1. Modify CPU passive policy to 95. 2. Modify TS0/TS1/TS2 passive policy to 90 for CPU. 3. Modify TS1 passtve policy watt to 6w. 4. Modify TS0/TS1/TS2 critical policy to 100. BUG=b:294479707 TEST=Build and verify DPTF value by thermal team on Boxy system Change-Id: Ic34e44f218ff980c54bf93841880fab5e21b3fca Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77108 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 16:14:07 +0000