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2021-07-15soc/amd/*/mca: factor out common MCA/MCAX check & print functionalityFelix Held
For Cezanne stubs are added for the functions that the SoC-specific code needs to provide. Since the mca_is_valid_bank stub on Cezanne always returns false, the checks get skipped for it at the moment. The actual functionality will be added in a later patch. Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/picasso/mca: factor out mca_has_expected_bank_countFelix Held
To factor out the rest of the common MCAX code, mca_bank_name[] may only be accessed by accessor functions, so implement this for the last place that still accessed mca_bank_name[] directly. Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/common/blocks/cpu/mca: factor out common BERT helper functionsFelix Held
Change-Id: I03365c3820cbe7277f14adc5460e892fb8d9b7a5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56284 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/*/mca: factor out BERT entry generation to soc/amd/commonFelix Held
Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56283 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/intel/alderlake: Add virtual GPIOs for community 1Maulik V Vaghela
Alder Lake SoC has virtual GPIOs for community 1 which was being programmed by FSP and hence was skipped by coreboot. As part of moving most of the GPIO programming to coreboot, we're skipping this programming in FSP now. TEST=Check register offset to see if programming is correct. Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55270 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15drivers: spi_flash: Add Fast Read Dual I/O supportJulius Werner
The Fast Read Dual Output and Fast Read Dual I/O commands are practically identical, the only difference being how the read address is transferred (saving a whooping 2 bytes which is totally irrelevant for the amounts of data coreboot tends to read). We originally implemented Fast Read Dual Output since it's the older command and some older Winbond chips only supported that one... but it seems that some older Macronix parts for whatever reason chose to only support Fast Read Dual I/O instead. So in order to make this work for as many parts as possible, I guess we'll have to implement both. (Also, the Macronix device ID situation is utter madness with different chips with different capabilities often having the same ID, so we basically have to make a best-effort guess to strike a trade-off between fast speeds and best chance at supporting all chips. If this turns out to be a problem later, we may have to add Kconfig overrides for this or resort to SFDP parsing, although that would defeat the whole point of trying to be fast.) BUG=b:193486682 TEST=Booted CoachZ (with Dual I/O) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-15google/trogdor: Enable SPI_FLASH_MACRONIXJulius Werner
We may want to use that flash vendor on future variants. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-15drivers/intel/gma: Restructure Opregion version info codeMeera Ravindranath
Define a structure for opregion version information to align with spec/kernel. BUG=b:190019970 BRANCH=None Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-15soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik
Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and SOC_INTEL_CRASHLOG is selected by the SoC user. Change-Id: Ibcd0259da86c8d9853e6cc4983675ac97df46c2d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56299 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik
Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and SOC_INTEL_CRASHLOG is selected by the SoC user. Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15mb/intel/adlrvp: Disable xDCI in devicetreeMonika A
Disable tcss_xdci as it is not used. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I94102240b13d2b96e0295f41bc2b0ba078faf342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-15mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a defaultMartin Roth
To be able to enable & disable PSP_verstage in the saved .config file, the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a select to a default with a prompt. BUG=182477057 TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK, verify that VBOOT_STARTS_IN_BOOTBLOCK is set. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso/mca: add missing types.h includeFelix Held
Change-Id: I67a88298c19657a5049ab69799be887555ca7240 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd: factor out check_mca to common codeFelix Held
Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56281 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/cezanne/mca: add empty mca_check_all_banks functionFelix Held
This will allow factoring out and moving check_mca() to soc/amd/common. Change-Id: I92c7657baef17c248a5aef1eda268e9647502837 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56280 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd: move check_mca prototype to soc/amd/common/blocks/includeFelix Held
Change-Id: Ia489dbfba59c334cf29f96a4000cef73b9b797d4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56279 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/stoneyridge: add and use mca_is_valid_bank & mca_get_bank_nameFelix Held
This patch changes the way how the not implemented MCA bank 3 gets skipped. For the not implemented bank 3 the name gets set to NULL resulting in mca_is_valid_bank returning false causing the bank to get skipped. This is a preparation for commonizing the MCA(X) handing in the soc/amd sub-tree. Change-Id: I40d6a6752504d804c45b445fce7e763e80161211 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-14soc/amd/picasso: implement and use mca_get_bank_nameFelix Held
Change-Id: I42abff5efcd7c85d2932a7aaacc736d0376cfaa0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd/picasso: implement and use mca_is_valid_bankFelix Held
In mca_check_all_banks only check valid MCA banks for errors. This aligns the Picasso code a bit more with the Stoneyridge code base which will be updated in a follow-up patch. This is a preparation for commonizing the MCA(X) handing in the soc/amd sub-tree. Change-Id: I0c7f3066afd220e6b8bf8308a321189d7a2679f6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso: check length of mca_bank_name arrayFelix Held
The length of mca_bank_name should match the return value of mca_get_bank_count which gets the number of MCA banks from an MSR. TEST=No error message on serial console on amd/mandolin Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56274 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso: add missing banks to mca_bank_name arrayFelix Held
Also use array indices for the initialization. TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16 Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14drivers/usb/acpi: Avoid dereferencing maybe-NULL pointerAngel Pons
Do not dereference a pointer before checking whether it is NULL. Change-Id: Icbe9ae99d91fd587d8e56cf3a0dcb59834ee6d07 Found-by: Coverity CID 1458232 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56266 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14drivers/usb/acpi: Replace unneeded `memcpy` useAngel Pons
A regular assignment works just as well and also allows type-checking. It also avoids a common mistake where `sizeof` is applied to a pointer to obtain the size of the data it points to, without dereferencing it. Found-by: Coverity CID 1458231 Change-Id: I7ed05322c3c911f3da4145f81e4d9760a275fec2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56265 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/stoneyridge: use index for mca_bank_name initializationFelix Held
Change-Id: Id640fd8006c47ce1db8a8729407c1c9a9c1e79c3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56272 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/stoneyridge/mca: add missing types.h includeFelix Held
Change-Id: Ifbcad4d81fb9f6c359a870be73b05ed86441e7f0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56271 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14src/device: Remove DEVICE_PATH_ESPI & DEVICE_PATH_LPCMartin Roth
The ESPI & LPC keywords were added for the zork program, but it was found that they weren't needed, so they were never used. The previous patch removes them from sconfig, so now they aren't needed in coreboot. BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9ae7817bb63d69ee272103b2d1186f125e188950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56278 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/common/block/lpc: Don't disable the HOG bitRaul E Rangel
According to the AMD FCH architects, we should be using the default value for the NO_HOG bit. This fixes a problem where the SPI DMA no longer functions after the LPC init runs. BUG=b:179699789, b:192373221 TEST=Boot guybrush and see SPI DMA working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-14soc/amd/cezanne: Move APOB update into ramstageRaul E Rangel
There is no technical reason this needs to be done in romstage. Moving it into ramstage allow us (in future CLs) to use threads to pre-load the apob from SPI. BUG=b:179699789 TEST=Boot and Ezkinil and Guybrush and verify APOB update still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-14thread: Add missing static inlineRaul E Rangel
BUG=b:179699789 TEST=Able to compile with the rest of the patch train. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-14soc/amd/common/block/apob: Fix incorrect printf formatRaul E Rangel
The %p format specifier already prints out 0x, so remove the 0x from the string. I also updated the other format specifiers to use the %# syntax to print out the 0x. BUG=b:179699789 TEST=see correct format. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/56225 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/cezanne: add basic MCA supportFelix Held
Currently the MCA support for Cezanne only clears the MCA status registers. The MCA error handling and BERT table generation will be added in subsequent patches. Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14include/cpu/amd/msr: add and use MC_CTL_MASK macroFelix Held
Add this macro to be able to conveniently access the MC_CTL_MASK register for each MCA bank. Also drop the unused definitions for MC1_CTL_MASK and MC4_CTL_MASK. Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msrFelix Held
This MSR isn't an architectural MSR, so it shouldn't be in the common x86 MSR definition header file. From family 17h on this register has moved to a different location. Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd/picasso/mca: use mca_clear_status()Felix Held
Since we can use both the old MCA registers and the new MCAX registers to access the MCA status registers, we can use the common mca_clear_status function here. Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14src: use mca_clear_status function instead of open codingFelix Held
Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56259 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14include/cpu/x86/msr: add mca_clear_status functionFelix Held
In multiple locations within the coreboot tree all available IA32_MC_STATUS registers are cleared, so add this to the common code to avoid duplication of code. Change-Id: I04af23c16021b0ce90f7105f7a3856bd26ffa736 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56258 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14mb/google/cherry: add configuration for tomatoRex-BC Chen
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I972c70773d4d928e75098efbf78f174d7c3ebf50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-14soc/mediatek/mt8195: Get DRAM size from DRAM calibration resultRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ic34f29d1692b94284b2cf6c5d91d323df736c76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56204 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/intel/alderlake: Add GFx Device ID 0x46a6Maulik V Vaghela
This CL adds support for new ADL graphics Device ID 0x46a6. TEST=Build and boot Adlrvp board Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56026 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/intel/common: Use SPR for backing up data way and eviction maskSubrata Banik
This patch replaces the usage of GPR (General Purpose Registers) like ECX and EBX for backing up data way and non-eviction mask with SPR (Special Purpose Registers) EDI and ESI. Purpose of this change is to ensure the safety while developers might use ECX often while doing rdmsr/wrmsr rather than making use of EDI. TEST=Able to boot JSL and TGL platform without any hang using eNEM. Change-Id: I12e0cb7bb050e4f7b17ecf30108db335d1d82ab7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56161 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/intel/skylake: Drop dead `ScanExtGfxForLegacyOpRom`Angel Pons
This devicetree option is never set and never used. Drop it. Change-Id: I9cd4733746849728b2b9f85793eace9191a97f49 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-07-14soc/intel/skylake: Rename `Rmt` devicetree settingAngel Pons
Rename `Rmt` to `RMT` for consistency with the UPD name. Change-Id: I905b9b65fa6c5711c6e726cc09d3cad5ba3640a1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-07-14mb/siemens/chili: Drop ineffective `SaGv` settingAngel Pons
SaGv is only available on ULT/ULX processors, which use PCH-LP. Given that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it does not use ULT/ULX processors, and thus does not support SaGv. Drop the `SaGv` setting from the devicetrees, as it has no effect. Change-Id: I5be518cce08206ad149efd1665e44a7111b24202 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56205 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14sb/intel/common: Hide IFD options if !HAVE_IFD_BINAngel Pons
When `HAVE_IFD_BIN` is not enabled, do not show IFD-related options. Change-Id: I8736f32b4c695efbd68adf551e1376726c718b56 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-14soc/intel/common/block/cpu/cpulib: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive, and make it constant. Change-Id: I449c74629ff16057c4559d7fd3620208230560f5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56245 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14cpu/intel/*/*_init: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive, and make it constant. In the case of Intel model 2065x the mca_get_bank_count() call replaces a magic number. Change-Id: I245b15f57e77edca179e9e28965383a227617174 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56244 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14include/cpu/x86/msr: introduce IA32_MC_*(x) macrosFelix Held
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly. Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/stoneyridge/mca: refactor warm boot check in mca_check_all_banksFelix Held
Change-Id: Id0cf8269d1b695e05c55f33af92978b8244090fa Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56242 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_check_all_banksFelix Held
Change-Id: I5496fd27f5c56d35ab95a5e02ea313b5b5536668 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56241 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_clear_errorsFelix Held
Change-Id: Id7a716a2598a6a7bea2d2d56898ea6329b5a3bec Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56240 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_print_error()Felix Held
Change-Id: I7cd05a389c34c2e5f3d0ab4cd06d60a7e3e5cad9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56239 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: use unsigned int for MCA bank numberFelix Held
Change-Id: Ib31075fd615eaa8492ce0179b3b21317554f1c80 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: clean up mca_bank structFelix Held
Only the fields bank and sts from the mca_bank struct were used outside a local scope, so remove the rest. Also rename the struct that now only contains the bank number and the status MSR content to mca_bank_status. Change-Id: I925347dff950ac2bd021635ca988c02fba48df7f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56237 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: mark num_banks as constantFelix Held
Change-Id: I23aa4d36d4e6d4c7ed66800c2e7963c4ed03c393 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56236 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISCFelix Held
Those registers are architectural MSR and this also gets them in line with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are ascending. Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56235 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14src: Use initial_lapicid() instead of open coding itArthur Heymans
Since initial_lapicid() returns an unsigned int, change the type of the local variables the return value gets assigned to to unsigned int as well if applicable. Also change the printk format strings for printing the variable's contents to %u where it was %d before. Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13intel/kblrvp: Move lockdown config to baseboard devicetreeFelix Singer
Clean up lockdown configuration and move it to the baseboard's devicetree. Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it for the rvp8 variant for consistency as well. Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains identical. intel/rvp8 changes, as expected. Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13mb/intel/kblrvp/variants: Fix indentation and remove empty linesFelix Singer
Change-Id: I4b5e0992494949bcb2fbda1361e0118c087a437a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56211 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00Ronak Kanabar
The headers added are generated as per FSP v2237_00. Previous FSP version was v2207_01. Changes Include: - Add VccInAuxImonIccImax in FspsUpd.h - Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:192199787 BRANCH=None TEST=Build and boot brya Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c Cq-Depend:chrome-internal:3970327,chrome-internal:3925290 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55896 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13soc/intel/alderlake: Implement WA for DDR5 DIMM modulesMeera Ravindranath
The coreboot SMBus driver requires additional changes to accomodate the DDR5 EEPROM read which has resulted in a broken code flow for boot. This CL serves as a temp WA to let FSP perform the SPD read for DDR5 and pass SPD addresses to FSP UPD array. BUG=b:180458099 TEST=Build and boot DDR5 adlrvp to OS Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50996 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13soc/intel/alderlake: Add (and fix) devices in IRQ tableTim Wawrzynczak
Some devices were missing from the IRQ table, and this lack of IRQ programming for the devices (although unused), was causing S0ix entry to fail. BUG=b:176858827 TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle correctly upon entry/exit from S0ix Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-13mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOTFelix Singer
Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown. Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56198 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13vc/mediatek/mt8195: Remove redundant codeRyan Chuang
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I10b2d3c6cb3480f9e3e3232b5ce87ecf7074bbbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-07-12security/intel/txt: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Change-Id: I28244c975ee34d36d0b44df092d4a62a01c3c79c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region"Felix Held
This reverts commit ce0e2a014009390c4527e064efb59260ef4d3a3b which was originally introduced as a workaround for the bug that the Linux kernel doesn't know what to do with type 16 memory region in the e820 table where CBMEM resides and disallowed accessing it. After depthcharge was patched to mark the type 16 region as a normal reserved region, the Linux kernel now can access the BERT region and print BERT errors. When SeaBIOS was used as payload it already marked the memory region correctly, so it already worked in that case. After commit 8c3a8df1021b8a2789c2a285557401837f9fc2b8 that removed the usage of the BERT memory region reserved by the FSP driver by the AMD Picasso and Cezanne SoCs and made them use CBMEM for the BERT region, no other SoC code uses this functionality. The Intel Alderlake and Tigerlake SoCs put the BERT region in CBMEM and never used this reserved memory region and the change for the Intel server CPU to use this was abandoned and never landed in upstream coreboot. AMD Stoneyridge is the only other SoC/chipset that selects ACPI_BERT, but since it doesn't select or use the FSP driver, it also won't be affected by this change. TEST=Behavior of the BERT code doesn't change on Mandolin Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12include/cpu/x86/msr: fix MCG_CTL_P definitionFelix Held
MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of that MSR contain the number of MCA banks being present on the CPU. At the moment this definition of MCG_CTL_P is unused. Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-12security/intel/txt: add missing cpu/x86/msr.h includeFelix Held
msr_t and a few other things used in here are defined in cpu/x86/msr.h, so include it directly in this file. Change-Id: I7a3299381ff54b7665620861dec60642f27bac8d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12soc/amd/*/mca: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I126767cf9ad468cab6d6537dd73e9b2dc377b5c4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12mb/google/brya: Update generic device number for mipi_camera deviceVarshit B Pandya
If two generic devices use the same number, device coming later overrides the earlier device, as a result of this the static.c has only one device. In the case where we have UFC set to UFC_USB, this will result in no IPU device scope in SSDT, since its entry will be set to disbled after UFC probe. TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12cpu/amd/*/model_*_init: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I70ad423aab484cf4ec8f51b43624cd434647aad4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12include/cpu/x86/msr: add mca_get_bank_count functionFelix Held
In multiple locations within the coreboot tree the IA32_MCG_CAP MSR gets read and masked with MCA_BANKS_MASK to get the number of available MCA banks on the CPU, so add this to the common code to avoid duplication of code. Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-12soc/amd/{cezanne,common}: Enable IOMMU PCIe DeviceRaul E Rangel
This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12acpi: Add function to simplify If (CondRefOf (..)) sequencesTim Wawrzynczak
The new function is called acpigen_write_if_cond_refof(), and it must be paired with a following acpigen_write_if_end() call. Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-12vc/amd/sb800: Cast to UINT32 for shift out of bounds fixPaul Menzel
It’s defined as `unsigned char`. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:643:53 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: I0c5fa16bce5b68ed3b48bb17eae6d81af894b688 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12vc/amd/sb800: Cast variable to 32-bit before shiftPaul Menzel
SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/Gpp.c:151:61 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: I6cbef2fa9806fd6da67031ca01bb25205013b478 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-12vc/amd/sb800: SBCMN: Cast to 32-bit before shiftPaul Menzel
SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:486:57 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: Id05b96f1f4cf4a1cf8283db22e10ab8df833406d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51286 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12drivers/intel/usb4/retimer: remove redundant structure member group(PLD)Maulik V Vaghela
Currently, we get PLD information from USB port structure itself, so devicetree does not need to fill PLD structure anymore. Thus remove obsolete variable. Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/brya,primus,voxel: Update controller field for tbt_dma entriesMaulik V Vaghela
We need to reference correct USB port number for driver to identify type-C port number correctly. BUG=b:189476816 BRANCH=None TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12drivers/intel/usb4/retimer: Update code to assign correct port numberMaulik V Vaghela
Since TBT controller can have maximum 2 ports per controller, our code will loop over DFP structure twice and determine port number. Retimer driver used to assign port number as below: 1. Check if power GPIO is assigned for particular DFP entry or not 2. If entry is there, assign loop count as port number Since loop count is 2, retimer will never assign port number = 2 even if it's present. In case of more than 1 controller, port number assigned will still be 0 or 1 even though actual port index might be 2 or 3. This will create an issue where even if you do transaction on device on controller 2 (port index 2 or 3), EC will route it on port 0 or 1 due to incorrect port index. Update the driver flow as per below to handle this scenario: 1. Check if power GPIO is assigned for particular DFP entry or not 2. Get USB port number from config since it's stored in usb port information under devicetree 3. Pass the port number to ACPI SSDT and EC code Above changes will ensure that we're assigning correct port number as per calculation and EC will use correct port index. BUG=b:189476816 BRANCH=None TEST=Checked that retimer firmware update works on both ports and update happens on correct port index. Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12drivers/usb/acpi: Create function to get PLD informationMaulik V Vaghela
Create a separate function to get PLD information from USB device. This is helpful in retimer driver where we can attach same USB port information to retimer instance and we can avoid duplication of information. BUG=None BRANCH=None TEST=Check if code compiles and function returns correct value Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/google/kukui: Add a new config 'Munna'Sunway
Introduce a new board 'Munna' to Kukui family. BUG=None TEST=make # select Munna BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ie53750d0b79fe6d7c6e7778ba4616b557708601d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56169 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBSubrata Banik
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Test=Boot ADLRVP and check cbmem -c | grep 'CBFS: Found' lists all stages. Change-Id: I38fd74c2edd71ce9f6c08db9dacb18e553745877 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-12soc/amd/cezanne/acpi: Change GPIO controller interrupt to sharedRaul E Rangel
The Majolica UEFI ACPI tables have this listed as shared. It's already a level interrupt, so no reason it shouldn't be shared. This change makes it so Windows can correctly initialize the GPIO controller. BUG=b:186212501 TEST=Boot guybrush to windows and see GPIO controller functional. Also boot guybrush to windows and verify GPIO controller still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12soc/intel/common/irq: Program IRQ pin in irq_program_non_pch()Tim Wawrzynczak
Previously, irq_program_non_pch() was only programming the IRQ line, but the pin is required as well. BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2a2823c183a3495721a912de285cddb4a9444c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56174 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/intel/alderlake: Add missing devices to pci_devs.hTim Wawrzynczak
There were some devices missing from pci_devs.h: 1) GNA 2) I2C6 and I2C7 3) UART3, UART4, UART5, UART6 4) UFS 5) GSPI4, GSPI5, GSPI6 BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56172 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/amd/picasso,stoneyridge/mca: remove unneeded line breakFelix Held
Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56180 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12mb/google/guybrush: enable psp_verstage by defaultKangheui Won
Select VBOOT_STARTS_BEFORE_BOOTBLOCK to turn on psp_verstage by default. BUG=b:182477057 TEST=boot guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I08befb93213aeb67e6a1e5fa91273ae61025707e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-12mb/google/brya/variants/primus: Update GPIO for PS8811 initCasper Chang
Route GPP_D14 to USB_A1_RT_RST_ODL for PS8811 init sequence BUG=b:193099675 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia950da61a50f30f7c4aaef572c5ed162ee76dd0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12soc/intel/alderlake: Set max Pkg C-states to AutoV Sowmya
This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-12mb/intel/adlrvp_m: Enable EC software syncThejaswani Putta
This patch enables CONFIG_VBOOT_EARLY_EC_SYNC. EC software sync will be performed in romstage. BUG=None BRANCH=None TEST=Verify EC software sync works on adlrvp_m Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56154 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12mb/google/brya: Create kano variantDavid Wu
Create the kano variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:193052432 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KANO Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/mediatek/mt8195: fine tune pmif spi hardware settings for stabilityJames Lo
Update IO driving setting for pmif spi. Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I48268cda8845a591592d8ca828ffe492e6dfe0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/56166 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12vc/mediatek/mt8195: Enable DRAM Vcore DVFS settingsRyan Chuang
Add the implementation for vcore voltage control. Also remove the reporting of vio18 because it is fixed during DRAM init, and we won't provide drivers for reading or writing it. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56106 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12vc/mediatek/mt8195: add FOR_COREBOOT defineRex-BC Chen
The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to identify implementations for Chromebooks (in coreboot) so we want to introduce a new flag FOR_COREBOOT to prevent confusion. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-09soc/intel: Fix microcode loadingTim Wawrzynczak
Commit 1aa60a95bd8363d2 broke microcode loading for chipsets that have a microcode blob with a total_size field set to 0. This appears to be support for older chipsets, where the size was set to 0 and assumed to be 2048 bytes. The fix is to change the result of the subtraction to a signed type, and ensure the following comparison is done without promoting the signed type to an unsigned one. Resolves: https://ticket.coreboot.org/issues/313 Change-Id: I62def8014fd3f3bbf607b4d58ddc4dca4c695622 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56153 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Stefan Ott <coreboot@desire.ch> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-09ppc64/byteorder.h: define use of big endianKrystian Hebel
All of the build configuration is set to produce big endian image on PPC64. In addition, the toolchain produced by coreboot-sdk does not include little endian libraries so it is not possible to build LE image even when that configuration is changed. This patch changes byte order definition which is required for proper work of functions that deal with endianness, like read_{le,be}*() or {le,be}*toh(). It also revealed bugs related to the endianness on BE targets that are addressed in the following patches. Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Change-Id: Id31328a832d11db20822733304b0ae477e858d25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-08mb/google/volteer/var/voema: Remove stop delay time for ELAN TSDavid Wu
Remove register "generic.stop_delay_ms" and measure data, it still can meet elan touchscreen specification that reset pull high to I2C time > 150ms (T3 > 150ms). BUG=b:185308246 TEST=Measure the T3 delay time is greater than 150ms on voema Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56087 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A BUG=b:190818098, b:190874372, b:192052098 TEST=build Change-Id: I62ee401e43bef22b4b09f41ea59bbdbc479f293c Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55885 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-08mb/google/brya: Create redrix variantWisley Chen
Create the redrix variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:192052098 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_REDRIX Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I4cfa0bd84e1ba9f8140f95d18a6da960da8124ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-08mb/google/brya0: Update the FIVR configurationsV Sowmya
This patch sets the disable the external voltage rails since brya board doesn't have V1p05 and Vnn bypass rails implemented. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I1c4fdb38c5c56798935b2c6627a75c3f1ac9fbef Reviewed-on: https://review.coreboot.org/c/coreboot/+/55704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-18 22:56:27 +0000