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2019-03-01mb/google/sarien: ALC3204 HDA verb table pin config changeJoyce Toh
On Sarien, change pin config of 0x19 (headset mic) and 0x21(headset headphone) to change jack location so that naming does not use "Front" in the name."Front Headphone" --> "Headphone" so it matches naming on Arcada. BUG=b:126334749 TEST= verify with 'evtest' command that jack name is "HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone" Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61 Signed-off-by: Joyce Toh <joyce.toh@intel.com> Reviewed-on: https://review.coreboot.org/c/31624 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28src/mb/sifive/hifive-unleashed: replace fdt in maskromXiang Wang
The fdt in the maskrom cannot be used to start linux. The correct fdt is dumped by replacing the bbl of the original firmware and used in coreboot. Correct the mac address in fdt by reading otp Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/31047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-02-28src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory areaFrans Hendriks
Calculation of memory reserved by FSP is incorrect. Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area BUG=N/A TEST=Intel CherryHill CRB Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28soc/intel/cannonlake: Add CometLake SoC supportSubrata Banik
This patch adds SOC_INTEL_COMETLAKE Kconfig option. Change-Id: I2b0c269ade84d72cffaf59a0b53e0d6e3a84b835 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31282 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28mb/google/poppy/variants/atlas: Update DPTF parametersPuthikorn Voravootivat
Preliminary dptf change for Atlas - Throttle charger using all temp sensors (not just ambient) - Throttle charger with higher priority than CPU - Update throttle temperature using data from surface thermistor in thermal chamber test BUG=b:113101335 BRANCH=None TEST=based on preliminary data from thermal chamber test Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/31628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-02-28mb/google/poppy/variants/atlas: Add tdp_pl1_override valuePuthikorn Voravootivat
Use 7w PL1 with DPTF throttle to enable better performance for atlas. BUG=b:113101335 BRANCH=None TEST=Recommend setting from thermal team. Build coreboot on atlas Change-Id: Idcf44f213259634a507a013b31b410ed322e9479 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/31627 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28src/soc/intel/braswell/southcluster.c: Config ISA DMA controllerFrans Hendriks
ISA dma controller is not configured. Add call isa_dma_init(). BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ib7af3f4ef6d6a29628bb2c27d32071be63ff6af2 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28soc/intel/braswell: Correct configuration of interruptsFrans Hendriks
The level/edge mode of PIRQ is not configured and i8259 PIC not initialized. Add calls to: - i8259_configure_irq_trigger() - setup_i8259() - write_pci_config_irqs() to correct the configuration of interrupts. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-28src/soc/intel/braswell/acpi/irqlinks.asl: Allow IRQ10 and 11 for all LNKxFrans Hendriks
IRQ10 and 11 are not available as _PRS in all LNKx ResourceTemplates. These interrupt numbers are added to all LNKx. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29287 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/x86/mtrr/mtrr.c:Avoid static scan false positiveRichard Spiegel
Static scan does not know the contents of the fixed MTRR descriptor, so it has no way to eval the result for variable num_ranges. If num_ranges is less or equal to 0, the for loop will not be entered, and the values of fixed_msrs will not be set. Asserting that num_ranges is greater than 0 ensures the loop enters at least once. BUG=b:112253891 TEST=build grunt Change-Id: Ieec0ac432c745bde4b1700539c266625da6cfd77 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28cpu/intel: Remove socket_BGA1284Nico Huber
Unused since the removal of `fsp_sandybridge`. Change-Id: Iea31e341c3df680ed48db4f8734d9d0bde120be3 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31646 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/intel: Rename socket_mPGA478MN to socket_pNico Huber
These marketing names are much easier to distinguish. My mnemonic: Socket M => up to Merom, Socket P => up to Penryn. Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31645 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/intel: Remove models 69x and 6dxNico Huber
These came for the Socket 479 which is not supported anymore. Change-Id: I0cf7ece028baa6750b79f54d615e93e452aff2e1 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31644 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28cpu/intel/socket_m: Remove models 69x and 6dxNico Huber
These sneaked in and were never supported by this socket (nor expected in the notebooks that have it). Change-Id: Iaeaf1d3bba213da56c7841cf6182e013626b8ca2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28cpu/intel: Rename socket_mFCPGA478 to socket_mNico Huber
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN, the successor of the socket that was meant. The official name of this socket is mPGA478MT. But "Socket M" is much easier to distinguish. Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28cpu/intel: Remove `socket_mPGA478`Nico Huber
Doesn't look like it could be used. Change-Id: I8074df12d062bd15f2388b367b3698c9d3b7b5b6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28mb/google/hatch: Add GPIO programming for GPP_C0 to GPP_C7Maulik V Vaghela
coreboot did not program all GPIOs from C0 to C7 correctly which are SMBUS GPIO. Some of the GPIOs are left in default mode which is native function but we need to configure as GPIO mode and provide proper configuration as per schematic. After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not getting idle due to GPIO configuration and CSME was not getting power gated due to SMBUS. BUG=b:123702553 BRANCH=none TEST=Check on hatch board. CSME was not getting power gated for s0ix. After applying this patch CSME is power gated now Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-28soc/intel/cannonlake: Disable ACPI mode on BS_DEV_INIT exitFurquan Shaikh
Change ac8c60e (soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_init) moved disabling of ACPI mode to pmc_soc_init to keep it more aligned with the behavior on other Intel SoCs. However, as the PMC device is hidden, it never gets enumerated and so init function does not get called for it. This change moves the call to disable ACPI mode to exit of BS_DEV_INIT instead. BUG=b:126016602 TEST=Verified that: 1. pmc_set_acpi_mode is actually getting called. 2. EC panic event gets logged to eventlog correctly. Change-Id: Ie7025e322fa0abc21367a520184a4c7741eba1e6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31633 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28google/kukui: Add RTC initializationRan Bi
Initialize RTC at ROM stage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I9d9c68755e8a6ac65dd794211e6ccf06e5057567 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-02-28mediatek/mt8183: Add RTC supportRan Bi
This patch implements RTC initialization. 1. initialization dcxo 2. rtc clock using dcxo 32k 3. export RTC_32K1V8_0 to SOC, export RTC_32K1V8_1 to WLAN 4. rtc register initialization 5. refactor the driver common part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Icccb9360a507fcbfd865b107cd3630e71c810d55 Signed-off-by: Ran Bi <ran.bi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-28vendorcode/intel/fsp/fsp2_0/cml: Add FSP header files for CometlakeMaulik V Vaghela
Adding header files for FSP for cometlake platform version 1034 Change-Id: I734316445dda5b1feb4098ce3c58b6dd8ce2d272 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-28mb/intel/saddlebrook: Fix 2nd DIMM slotKyösti Mälkki
Assumed broken during review and rebase. The SPD at address 0x52 will appear at index 1. Change-Id: I213853d2b981294554d8d1b254da476905a41c13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-28intel/spi: Switch to native PCI config accessorsKyösti Mälkki
Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-28intel/spi: Fix use of __SIMPLE_DEVICE__Kyösti Mälkki
Fix cases of using ENV_SMM where __SIMPLE_DEVICE__ should be used instead. Change-Id: I385c82767a87ff7a47466a200488fae9fc8b863d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-02-28soc/intel/cannonlake: Add PCH series check for CML LP PCHMaulik V Vaghela
TEST=Verify PM_STS1 value is is not 0xFF. Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31434 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device IDSubrata Banik
This patch adds CML-U 2+2 SA DID into systemagent.c and report platform. Change-Id: I2e882a560dd0a1e96d6e1405735c6f7389c0db5a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31638 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-28soc/intel/skylake: Remove redundant PM emulation timer macrosSubrata Banik
This patch removes duplicate pm timer emulation macros from soc directory and makes use from common code msr.h Change-Id: I6ec347e7464f785862e855817ec8308e3d207bb1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31610 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27flapjack: use sku_id 0 for un-provisioned boardYH Lin
Instead of using 2, 0 is now used for non-CBI provisioned board or corrupted CBI board to confrom to the sku encoding. BUG=b:123676982 BRANCH=kukui TEST=test with un-provisioned board to verify the sku_id. Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce Reviewed-on: https://review.coreboot.org/c/31623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27console: Split loglevel for fast and slowKyösti Mälkki
For fast CBMEM console use minimum BIOS_DEBUG level. For other consoles, Kconfig and/or nvram settings apply. Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27console: Refactor printk() varargs prototypesKyösti Mälkki
Change-Id: I816641c2223c3079ad9c95c1380d4b250898ef93 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27ec/google/chromeec: fix the error status passingYH Lin
Various instances of google_chromeec_command() can return non-zero number (both positive and negative) to indicate error -- fixing cbi_get_uint32() and cbi_get_string() so they follow the same convention. BUG=b:123676982 BRANCH=kukui TEST=build with kukui/flapjack configurations Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I7f0a8a61d01d942cba57036a17dd527fdbbf940c Reviewed-on: https://review.coreboot.org/c/31585 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27rtc: Fix rtc_calc_weekdayTim Wawrzynczak
This function appeared previously unused (called only from rtc_display, also unused), but it returned an incorrect weekday. Change the algorithm to use Zeller's Rule, a well-known algorithm for calculuating weekdays. Change-Id: Ibce6822942f8d9d9f39c2b6065cd785dca9e8e09 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/31557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-27mb/google/hatch: Initialize GPIO_PCH_WP early in bootRizwan Qureshi
Initialize GPIO_PCH_WP early in boot. Update cros_gpios[] array with GPIO_PCH_WP information. Also, Configure recovery mode GPIO as virtual since hatch does not have one. BUG=b:125943273 Change-Id: I0b7e6dbf9229941aca4952965fb54f07457dccae Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27mb/google/hatch: Select SD_PWR_EN Active high configRizwan Qureshi
Hatch implements active high SD_PWR_EN and requires a workaround in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same. BUG=b:123350329 Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi
SD controller in CNL-PCH provides a ability to configure the behavior of SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD "SdCardPowerEnableActiveHigh" to control the same. However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC card connector is always powered and may impact system power. This is because SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not inserted. Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and force the TX buffer to low in _PS3. And restore the pad mode to native function in _PS0. Hence add a Kconfig option to update the UPD, which the board can select based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround gets applied based on this config. BUG=b:123350329 Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31445 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffersRizwan Qureshi
Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers. BUG=b:123350329 Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27mb/google/hatch: update SD card detect GPIORizwan Qureshi
SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO, expose that GPIO for kernel to configure card detect IRQ. BUG=b:123350329 Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-27mb/google/cyan: fix RAM training on edgar variantMatt DeVillier
Adapted from Chromium commit 5351dc0d [Edgar: To set the RX ODT limit and dram geometry with RAMID detection] Several cyan variants require memory init parameters be passed to FSP for handling of specific Micron modules; without these, RAM init will fail when loading training data from the MRC cache, and boot will halt. This was missed when I upstreamed edgar along with the other cyan variants, so add the required memory init parameters for edgar as per its source Chromium branch. Test: build/boot on edgar board with affected Micron memory modules, verify boot successful with populated MRC cache. Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31615 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27soc/cavium/cn81xx: Drop VBOOT_RETURN_FROM_VERSTAGEPatrick Rudolph
To support measured boot, drop VBOOT_RETURN_FROM_VERSTAGE. The SoC has enough CAR space to support a separate verstage. Tested on OpenCellular Elgon. Change-Id: I18022000f6f05df89d3037896ef627070bfcca06 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/31568 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-27soc/intel/cannonlake: Disable ACPI mode as part of pmc_soc_initFurquan Shaikh
PMC initialization on Cannon Lake happens earlier in the boot sequence than other SoCs because FSP-Silicon init hides PMC from PCI bus. As ACPI disabling was done as part of PMC init, it was being called earlier than what other SoCs do. This resulted in a different order of events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it ended up clearing EC events (which happens as part of ACPI disabling in SMM) before logging any events of interest that happen during mainboard initialization. This change moves the call to disable ACPI to pmc_soc_init just like other SoCs to keep the order of events more aligned. BUG=b:126016602 TEST=Verified that EC panic event gets logged to eventlog correctly. Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-26Add missing u8 eos[2] declaration to struct smbios_type38Lukasz Siudut
Each smbios entry should be followed with two null bytes. In other structures it's done by adding `u8 eos[2]` extra bytes at the end, it was omitted in type38 (IPMI) though. This change fixes this - tables decodes nicely: ``` IPMI Device Information Interface Type: KCS (Keyboard Control Style) Specification Version: 2.0 I2C Slave Address: 0x10 NV Storage Device: Not Present Base Address: 0x0000000000000CA2 (I/O) Register Spacing: 32-bit Boundaries ``` Signed-off-by: Lukasz Siudut <lsiudut@fb.com> Change-Id: I8efea9612448f48e23e7b2226aea2a9f3bc21824 Reviewed-on: https://review.coreboot.org/c/31482 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26soc/amd: Remove defined but unwritten functionsRichard Spiegel
There are functions defined on headers with no code written for. They probably existed earlier, were removed and forgot in the headers. Remove functions from headers if there's no actual code written for. BUG=b:123564495 TEST=Build grunt. Change-Id: Ia6a12e22a0944351c455dc2c3b534f09a258bd7b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-26mb/gigabyte/ga-h61m-s2pv: fix cosmetic thingsAngel Pons
Remove unneeded options, note where usbdebug is, reorder devicetree and clean up dsdt. Tested, board still boots. Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/31558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-26ACPI: Fill asl_compiler_revision field left emptyElyes HAOUAS
Change-Id: I1075e872e5cb1990bd330b88bb03322ab9338e86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-26ec/google/chromeec: Clarify return value of google_chromeec_commandDaisuke Nojiri
This patch clarifies the definition of google_chromeec_command. Currently absence of the definition isn't causing any problem because wrapper APIs check 'ret != 0' or wrapper APIs check 'ret < 0' for an interface which returns only negative error codes. However, there is a chance that a new wrapper API will be addedl which check 'ret < 0' to catch errors, assuming other interfaces behave the same. Or existing wrapper APIs will be broken as soon as they're compiled for another interface. BUG=chromium:935038 TEST=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I2ce7109b5f2a1d5294f167719730bc1f039ba03f Reviewed-on: https://review.coreboot.org/c/31613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26flapjack: get sku_id from ec (cbi)YH Lin
On flapjack, retrieve the board information via CBI interface. Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id used prior to the readiness of cbi. BUG=b:123676982 BRANCH=kukui TEST=provisioned cbi info and verify the sku_id. Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc Reviewed-on: https://review.coreboot.org/c/31586 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26soc/cavium/cn81xx: Enable RNG for DRAM initPatrick Rudolph
The Cavium DRAM init might use the RNG for pattern generation. Initialize it before running DRAM init. Tested on OpenCellular Elgon. The RNG generates non identical numbers. Change-Id: I886f920e9941793fb76b56cc5a24a42e23b082e0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/31567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-26mediatek/mt8183: Modify I2C source clockQii Wang
This patch change i2c source clock to TOPCKGEN. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I49e0acda22dba449d0873a95ba5fae79a9cef569 Signed-off-by: Qii Wang <qii.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-02-26soc/intel/cannonlake: Update GPIO definitions for Virtual GPIORizwan Qureshi
Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC. Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-26acpi: Sort the reported APIC-IDs in the MADT tableWerner Zeh
coreboot performs MP-Init in a parallel way. That leads to the fact that the order, in which the CPUs are woken up, can vary from boot to boot. The creation of the MADT table just parses the devicetree and takes the CPUs reported there as it is for creating the single local APIC entries. Therefore, the OS will see different order of CPUs. There are CPUs out there (like Apollo Lake for example) which have shared caches on core-level and if the order is random this can end up in assigning cores to different tasks or even OSes (in a virtual environment) which uses the same cache. This in turn will produce performance penalties across these distributed tasks/OSes. Though there is a way to discover the core- and cache-topology it will in the end be necessary to take the APIC-ID into account. To simplify it, one can achieve the same output by sorting the APIC-IDs in an ascending order. This will lead to the fact that CPUs that share a given cache will be reported right next to each other in the MADT. Change-Id: Ida74f9f00a4e2a03107a2124014403de60462735 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-26commonlib: Add Bubble sort algorithmWerner Zeh
Add an implementation for Bubble sort. For now, only integers can be sorted in an ascending or descending order. It can be later simply extended to cover other datasets like strings if needed. The reasons for choosing bubble sort are: * it is a simple algorithm * bubble sort is stable, i.e. it does not exchange entries which are not needed to be sorted as they are already in order Change-Id: I2c5e0b5685a907243b58ebe6682078272d316bf6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-26soc/intel/common: Include cometlake PCH IDsRonak Kanabar
Add cometlake specific PCH IDs Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-25security/vboot: Add measured boot modePhilipp Deppenwiese
* Introduce a measured boot mode into vboot. * Add hook for stage measurements in prog_loader and cbfs. * Implement and hook-up CRTM in vboot and check for suspend. Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25cpu/x86/smm: Add qemu's SMM-Revision LevelPatrick Rudolph
The SMI handler on qemu returned early, due to missing SMM-Revision Level support. Add the ID qemu uses, which is AMD64 compatible for qemu-system-x86_64. Fixes booting tianocore payload with SMM variable store on qemu. Change-Id: I978b94150cfc49a39c2a0818eb14a649850e451d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-25src/device/Kconfig: Change default VESA mode from 117h to 118hMike Banon
Change default VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) from 117h (1024x768 64k-color (5:6:5)) to 118h (1024x768 16.8M-color (8:8:8)) mode. This provides console output at Lenovo G505S even if e.g. GRUB is the payload, while it is unlikely to cause any downsides for the other boards. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ia348199bbd430532b1399706dd84490c9680b5f5 Reviewed-on: https://review.coreboot.org/c/31595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-25ACPI: Enum only used ACPI tablesElyes HAOUAS
enum contained redundant names and wasn't exhaustive anyway. Change-Id: I4d74ff61c555c5953932efbd7edccfd3157cb5be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-25soc/cavium/common: Make ecam0_get_bar_val commonPatrick Rudolph
Move ecam0_get_bar_val into the common folder and make it public. Compile it for romstage and ramstage. To be used by romstage PCI code. Tested on OpenCellular Elgon. Change-Id: I18b1ede56795bf8c1f9476592291b8ea610eccd4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/31566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-25sb/amd/hudson/acpi: Fix illegal object referencesElyes HAOUAS
Issue spotted using IASL 20190215 on mainboard GIZMOSPHERE_GIZMO2: "Object is created temporarily in another method and cannot be accessed" Change-Id: I1e4ca2c765083db3a27e415d3a69bef0912a606b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-25ec/google/wilco: Fix ACPI power status eventsDuncan Laurie
This change fixes the power status events for AC and battery events from the EC. The register that was being used is not returning the expected information. BUG=b:125472740 TEST=enable ACPI debug in the kernel and verify that AC and battery insert/remove are detected properly. Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-25AGESA vendorcode: Define libagesa rule just onceKyösti Mälkki
No reason to keep this rule in per-family directory. Change-Id: I6bfc9a277674077774c4cb398f8add5e4fa99c69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31509 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25soc/amd/common: Fix AmdLateRunApTask()Kyösti Mälkki
Third parameter ConfigPtr of the callout is of type AP_EXE_PARAMS and needs to be passed back to AGESA with AmdLateRunApTask() call. Change-Id: I1dad64b955b53bd19363737665235f95aa3d451e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/27277 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25vendorcode/siemens: Cache currently opened hwi file nameWerner Zeh
On every call of hwilib_find_blocks() the CBFS file will be mapped and the contents are parsed to get the offsets for every single block. This is not needed if the CBFS file name is the same for the different calls. This patch adds a storage for the currently opened CBFS file name in CAR_GLOBAL and checks on each call if the file to open is already open. If yes, the file will not be mapped again which saves execution time. Test=Booted mc_tcu3, mc_bdx1 and mc_apl1 and verified that hwinfo.hex is only mapped once across several following hwilib_find_blocks() calls. In addition a test was done to ensure that files with different names get mapped correctly. Change-Id: Id69e0f6c914c2b8e4551fd8a4fb7d452d176afb3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-24mb/emulation/qemu: Fix fw_cfg file loadingPatrick Rudolph
The change bcd84fe "mb/emulation/qemu-i440fx: change file handling" introduced a regression where it loads only 4 bytes of the ACPI and SMBIOS table, instead of the whole table. Load the whole ACPI and SMBIOS table. Tested on Qemu using GNU/Linux. Change-Id: Ibacbf7caab9be5f181c12e9dd39a2893b13cf6c9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31593 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24soc/intel/common: Include cometlake SA IDsRonak Kanabar
Add cometlake specific SA IDs Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-24soc/intel/common: Include cometlake CPU IDsRonak Kanabar
Add cometlake specific CPU IDs Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2019-02-23arch/x86/smbios.c: Remove duplicated 'processor_upgrade'Elyes HAOUAS
Change-Id: I3500a648631c91f3a0812c7e661440743ed6a1e1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-23drivers/intel/fsp2_0: Update dependency of USE_FSP_REPOMaulik V Vaghela
USE_FSP_REPO used to rely on SOC_INTEL_COMMON_CANNONLAKE_BASE which was getting selected for cometlake soc also. Since FSP is not yet upstreamed for cometlake, compilation was failing due to FSP was not found. So limiting USE_FSP_REPO option to coffeelake and whiskeylake soc only and excluding for cometlake. Change-Id: I5e5d5a9fdf3f5d3e79922e97719e8491aa514cef Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-02-23soc/intel/cannonlake: Make few more whitespace proper in MCH nameSubrata Banik
CB:31547 fixes few whitespace error. Here is few more whitespace clean up. Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-22arch/arm64: Add PCI config support in romstageKyösti Mälkki
Change-Id: I9cc3dc51764f24b986434080f480932dceb8d133 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22mb/google/hatch: Enable wake from trackpadShelley Chen
For some reason, wake does not currently work from GPP_D21, but IRQs are working fine from that gpio. Thus, we have to switch IRQ to GPP_D21 and wake to GPP_A21, which was previously used for IRQs from the trackpad. Additionally, we need to use two gpios for irqs and wake source at the moment because of b:123967687, where FSP is locking down PCR and configuring ITSS. We need to configure the wake source gpio as inverted and the IRQ gpio as non-inverted until the bug is resolved. BUG=b:121212459 BRANCH=None TEST=run evtest with trackpad Use trackpad with ChromeOS UI and make sure it reacts as expected. Run powerd_dbus_suspend and press trackpad and make sure DUT wakes. Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22drivers/cavium: Add UART PCI driverPatrick Rudolph
Add UART PCI driver in cavium/common/pci. Tested on opencellular/elgon. The UART is still initialized and usable in Linux. Change-Id: I0fa2f086aba9b4f9c6dba7a35a84ea61c5fa64e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-22mb/google/poppy/variants/atlas: move WiFi wake to GPP_B7Caveh Jalali
The latest rev. of the atlas board moves the WiFi wake source from WAKE# to GPP_B7. The original GPP_A0 in the device tree is just wrong. This also reconfigures DW1 to the GPP_B group so we can use GPP_B7 as a wake source. GPP_B7 is still configured as a no-connect in gpio.c, so this doesn't actually enable WiFi wake. We'll follow up with another patch to set up GPP_B7 properly on boards that support it. BUG=b:122327852 BRANCH=none TEST=atlas still boots Change-Id: I1816500dd0ab6186fd51aa6945faf73d00c152fe Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22vboot: fix STARTS_IN_BOOTBLOCK/_ROMSTAGE logicJoel Kitching
Fix up the logic of when to include VBOOT2_WORK symbols on x86, which are only needed when VBOOT_STARTS_IN_BOOTBLOCK is enabled. Also correct the value of the __PRE_RAM__ macro in the case that VBOOT_STARTS_IN_ROMSTAGE is selected. In this case, DRAM is already up and verstage should not be considered pre-ram. BUG=b:124141368, b:124192753 TEST=Build locally for eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x TEST=make clean && make test-abuild BRANCH=none Change-Id: Ie51e8f93b99ab230f3caeede2a33ec8b443e3d7a Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/31541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22mb/ocp/monolake: Fix booting issuesLukasz Siudut
We experienced booting issues during FSP-M phase. Applying fix that was introduced for wedge100s - 817994c1bec (mb/ocp/wedge100s/romstage: Workaround broken platform state) - helped and systems started to boot properly. Signed-off-by: Lukasz Siudut <lsiudut@fb.com> Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab Reviewed-on: https://review.coreboot.org/c/31435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from ↵Jeremy Soller
devicetree Tested on system76 galp3-c Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d Reviewed-on: https://review.coreboot.org/c/31535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22soc/intel/cannonlake: Add ASL function for setting pad modeRizwan Qureshi
Add a function in gpio ASL library to set pad mode. BUG=b:123350329 Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-22symbols.h: Add macro to define memlayout region symbolsJulius Werner
When <symbols.h> was first introduced, it only declared a handful of regions and we didn't expect that too many architectures and platforms would need to add their own later. However, our amount of platforms has greatly expanded since, and with them the need for more special memory regions. The amount of code duplication is starting to get unsightly, and platforms keep defining their own <soc/symbols.h> files that need this as well. This patch adds another macro to cut down the definition boilerplate. Unfortunately, macros cannot define other macros when they're called, so referring to region sizes as _name_size doesn't work anymore. This patch replaces the scheme with REGION_SIZE(name). Not touching the regions in the x86-specific <arch/symbols.h> yet since they don't follow the standard _region/_eregion naming scheme. They can be converted later if desired. Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-22rockchip/rk3399: Fix BL31 bootmem regionsJulius Werner
The BL31 on RK3399 is split into multiple segments... the majority goes into DRAM, but small parts must be put into SRAM and PMUSRAM. With CB:31123 only the DRAM part was added to memlayout, so the SRAM parts will not be correctly marked in bootmem and BL31 loading fails the selfload check. This patch adds the remaining regions to fix the problem. Change-Id: Ia0597216c08512c47361a1dc0beb34d022a8994f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/31538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ting Shen <phoenixshen@google.com>
2019-02-22soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD nameSubrata Banik
Change-Id: I33a50e9fc90162c7cb2aa7fbc3887efe9c6ebcde Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/31547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-22Revert "src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260"Duncan Laurie
This reverts commit 3afb84a24583f5dee9fb407f11b32253d59392bf. Reason for revert: This is causing issues with the PCIe link and the system is unable to enter S0ix. Until it can be fixed in coreboot revert the change here that is not working properly. BUG=b:124264120 Change-Id: Ia20da9ab560ca35950b4a916667f51e0f541b382 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31559 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22mb/google/hatch: Make EC software sync enabled by defaultScott Collyer
EC software sync had been disabled because BIOS was not bundling a useful EC image. This is no longer required. This CL removes that change so EC software sync is enabled by default. BUG=b:124208414 BRANCH=None TEST=Tested with a system that have a different RW image and verified that this image was overwritten to the one bundled in the BIOS and that the EC was running its RW image. Signed-off-by: Scott Collyer <scollyer@chromium.org> Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5 Reviewed-on: https://review.coreboot.org/c/31537 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21cpu/intel/common: Add newline to set_feature_ctrl_lock() outputMatt DeVillier
Without newline, if IA32_FEATURE_CONTROL already locked, next console line will be concatenated. If run on a multiple CPUs, you get multiple lines concatenated. Change-Id: I5b73ae4cb045973fa3ce07f4d93fda0caadf78eb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21mediatek/mt8183: Support gpio eh and rsel setting for I2Cjg_poxu
The setting of these registers are only for i2c pin. BUG=b:80501386 BRANCH=none TEST=Boot correctly on Kukui Change-Id: I518ca07645fe55aa55e94e4f98178baa0b74a882 Signed-off-by: jg_poxu <jg_poxu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/30974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-21timestamp: Move timestamp_should_run() callKyösti Mälkki
Old location caused spurious error messages when called from APs, where timestamp_add_now() should do nothing. Moving the test also makes get_us_from_boot() usable from APs (assuming cache coherency). Change-Id: Ice9ece11b15bbe1a58a038cda3d299862e6f822b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31524 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21soc/intel/cannonlake: SoC specific microcode update checkRonak Kanabar
For CFL and WHL, Microcode is being loaded from FIT. Both supports the PRMRR/SGX feature. If This is supported the FIT microcode load will set the msr (0x08b) with the Patch id one less than the id in the microcode binary. This results in Microcode getting reloaded again in bootblock and ramstage. Avoid the microcode reload by checking for PRMRR support. CFL and WHL CPU die are based on KBL CPU so we need to have this check, where CNL CPU die is not based on KBL CPU so skip this check for CNL. BUG=b:124126405 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955 Reviewed-on: https://review.coreboot.org/c/31492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-02-21sb/intel/bd82x6x: Fix default IRQ mappingNico Huber
The default mapping was probably copy-pasted from a random board and disabled some interrupts (by implicitly clearing some register bits). We provide a new default mapping with some reasoning, that tries to be most compatible (i.e. avoids to use PIRQ E-H that are not shareable on some boards). The following functions had their interrupt pin disabled before: o SATA 2 (explicitly, no board seems to enable the device) o PCIe Root Port #4, #6-#8 (probably by accident) PIRQs used before this change: A-D, F and H. After this change: A-D. Change-Id: I33f82702ea9c1b9c22ce14f01ee630dbf6203362 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/31498 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21ACPI: Correct asl_compiler_revision valueElyes HAOUAS
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21SMBIOS: Fix bios versionElyes HAOUAS
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21mb/roda/rk886ex/acpi/superio.asl: Fix copy-paste error on "COMB"Elyes HAOUAS
Error spotted using IASL 20190215: "Object is created temporarily in another method and cannot be accessed" Change-Id: I139c5c7b33671e7ed0c04c06fb290e001e57a687 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21mb/roda/rk9/acpi/superio.asl: Fix copy-paste error on "COMB"Elyes HAOUAS
Error spotted using IASL 20190215: "Object is created temporarily in another method and cannot be accessed" Change-Id: I7da9dcd68f5eec6383de7370bc8ab35f96a90c06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-21soc/intel/cannonlake: Add field to identify single channel memoryShelley Chen
Variants of Hatch need to accommodate single channel DDR. Also, removing const modifier as we'll need to set these fields incrementally now. For the single channel configuration, we set MemorySpdPtr10 to 0. For the dual channel configuration, we set MemorySpdPtr10 to MemorySpdPtr00. BUG=b:123062346, b:122959294 BRANCH=None TEST=Boot into current boards and ensure that we have 2 channels as expected Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31262 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-21src/soc/intel/cannonlake: Add PsysPmax settingGaggery Tsai
This patch feeds PsysPmax setting to FSP through UPD and adds a psys_pmax member in chip information so that we can set PsysPmax through DT. The PsysPmax needs to be set correctly mapping to maximum system power. Otherwise, system performance would be limited due to the default PsysPmax setting in FSP is only 21W. BUG=None BRANCH=None TEST=Set psys_pmax to an example value eg 101 in DT && put debug code in FSP to print the PsysPmax value before sending to Pcode, ensure the setting is correctly programmed. Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/31505 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20src/soc/intel/cannonlake: Add _DSM methods for LPIT tableLijian Zhao
This patch adds the _DSM method 5 and 6 for entering and exiting S0ix. The _DSM method gets injected into DSDT table and called from kernel. LPIT table is hardcoded in this patch but the proper way to implement is to use inject_dsdt to make the _DSM methods available for soc's to implement. Calling the LPIT table from mainboard here so that with the current implementation the platforms which do not have lpit support throw compilation error. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db Reviewed-on: https://review.coreboot.org/c/31101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-20sb/intel/i82371eb/fadt: Fix compilation on x86_64Patrick Rudolph
Change-Id: I8997910ff003a4d0c97656cb1e9a4342230ac51a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-20drivers/spi/spi_flash.c: Avoid static scan false positiveRichard Spiegel
Static scan-build indicates a possible invalid return from function spi_flash_cmd_erase(). The root cause is because the scan believes it's possible for offset to be above the end address in the first pass, thus not setting a value for variable ret. Assign initial value of -1 to variable ret to make checker happy. BUG=b:112253891 TEST=build grunt Change-Id: If548728ff90b755c69143eabff6aeff01e8fd483 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-20walkcbfs: Only compile on x86_32Patrick Rudolph
The current implementation was designed for x86_32, so don't attempt to compile it on x86_64 until it is fixed. Fixes compilation error on x86_64. Change-Id: Ibd87dc2979f6d45a988119c06c5f9e61b3e86171 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/31467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-20drivers/intel/wifi: Add support for Harrison Peak (HrP) 9560 moduleSubrata Banik
Add HrP 9560 module device ID (0x02F0) into device/pci_ids.h file. TEST=HrP module is getting detected during PCI enumeration Change-Id: Id0a8a7a8cf7c665bd49f27b1c50d41d26a3274ce Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/31475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-20sifive/hifive-unleashed: Drop unneeded console_tx_flush()Kyösti Mälkki
Every printk() call already does console_tx_flush() so there should not be anything in transmit buffer when we return from console_init(). Change-Id: Iff2927c02d2c8031907620a056782bb014f20162 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31369 Reviewed-by: Xiang Wang <wxjstz@126.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20mb/google/sarien/variants/sarien: Adjust TP/TS I2C CLK to meet specChris Zhou
After adjustment on Sarien EVT Touch Screen CLK (Elan): 389.7 KHz Touch Screen CLK (Melfas): 377.7 KHz Touch Pad CLK: 385 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope with sarien. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d Reviewed-on: https://review.coreboot.org/c/31476 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-19soc/intel/common: Add whiskeylake celeron v-0 supportLijian Zhao
New whiskeylake v-0 stepping have changed the graphics device id from 0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the CPUID was changed from 806EB to 806EC, include that as well. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6 Reviewed-on: https://review.coreboot.org/c/31433 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 11:41:06 +0000