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2022-10-10nb/intel/i945/raminit.c: Fix formatted printElyes Haouas
Change-Id: I7122988a1c88175a2e72c11bb95bfa434ce48ff2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68104 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10mb/amd/birman: Add framework for morgana crb birmanMartin Roth
birman is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I4b16854c954949217a76c3d4f04ddc4001f64337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10soc/amd/common: Remove buildtime error for unknown cpuMartin Roth
This is not critical functionality and doesn't need a build-time error. Having it as a build time error causes a chicken & egg issue where the chipset needs to be added before it can be added to this file, but the header file fails the build because the chipset is unknown. It's not practical to exclude these files from the new platform builds because the PSP functionality is thoroughly embedded into the coreboot structure. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ib02bbe1f9ffb343e1ff7c2bfdc45e7edffe7aaed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-10soc/amd/morgana: Add initial commit for new SoCMartin Roth
This is an initial framework for the Morgana SoC. TODOs have been added to the files for both customization and commonization. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: If92e129db10d41595e1dc18a7c1dfe99d57790cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68195 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-08soc/amd/mendocino/psp_verstage: Remove TODO commentKarthikeyan Ramasubramanian
PSP verstage has been successfully enabled and this makefile looks good. Hence removing a TODO comment. BUG=b:239090306 TEST=Build Skyrim BIOS image. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic3cd55171fd1e4d74fac72f0b0b92dc80e533b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-08mb/google/skyrim: Create frostflow variantChao Gui
Create the frostflow variant of the skyrim reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:240970782 BRANCH=None TEST=util/abuild/abuild -p none -t google/skyrim -x -a make sure the build includes GOOGLE_FROSTFLOW Signed-off-by: Chao Gui <chaogui@google.com> Change-Id: I937e6562094968824e73bfa20390b3ec8b24dfa0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-10-08mb/prodrive/hermes: Write reset cause regs to EEPROMAngel Pons
Write the value for reset cause registers to the EEPROM for debugging. Change-Id: I827f38731fd868aac72103957e01aac8263f1cd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67483 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-08mb/prodrive/hermes: Add part numbers to SMBIOSAngel Pons
Adjust the EEPROM layout to account for two new fields: board part number and product part number. In addition, put them in a Type 11 SMBIOS table (OEM Strings). Also, rename a macro to better reflect its purpose. Change-Id: I26c17ab37859c3306fe72c3f0cdc1d3787b48157 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67759 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-08vc/amd/fsp: Add Morgana FSP vendorcodeMartin Roth
Initial commit of the FSP-specific code for the Morgana SoC. This is just an initial framework and still needs to be updated to match the Morgana FSP. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ic53c59404f96c73c55eb2648113c5ced26d6e20c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08vc/amd/fsp: Make common directoryMartin Roth
The common directory is for files that shouldn't change, or shouldn't change much between platforms. These will be removed from other directories and used in upcoming commits. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I37ed98a67b066598fdebcc5b034e64dc639fda7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-10-08mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbonKevin Chiu
Enable DRIVERS_GENESYSLOGIC_GL9750 for lisbon BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I74cd634700b2de16ae471e0a738b67a14fd82a50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68168 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07ec/starlabs/merlin: Add EC related files for Alder Lake boardsSean Rhodes
Add EC memory layout and Q events for Intel Alder Lake based boards, the "StarBook Mk VI" and "StarFighter Mk I", which both use the ITE 5570E. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8cea386ba91d076084002738fe7041834deea311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-07mb/prodrive/hermes: Factor out serial reading logicAngel Pons
Add the `eeprom_read_serial()` function to read serials from the EEPROM. Note that there's only one buffer now: this means only one serial can be accessed at the same time, and the buffer needs to be cleared so that it does not contain old data from other serials. Given that the serials are copied one at a time into SMBIOS tables, having one shared buffer is not a problem. Change-Id: I5c9781e4e599043be756514cfd6dd86dedcf580c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67275 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07mb/prodrive/hermes: Prevent SGPIO cross-powering 5V railAngel Pons
The PCH's SGPIO pads are connected to a buffer chip that is powered from the always-on +3V3_AUX rail. For some cursed reason, when the SGPIO pads stay configured as SGPIO when a Poseidon system shuts down, voltage from the +3V3_AUX-powered buffer chip will leak into the +5V rail through the SATA backplane. Just pulling the SGPIO pads low before the system powers off stops the +5V rail from being cross-powered. This issue has only been observed in S5, but it's very likely other sleep states are affected as well. Thus, always pull the SGPIO pins low before entering ACPI S3 or deeper because the power supply will turn off in these states as well. TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered after going to S5. We measured 0.17V on our system, but voltages as high as 0.6V were measured on other systems. Verify that unplugging the SGPIO cable going to the SATA backplane results in the +5V rail voltage dropping to 0V, which indicates that the voltage leakage is exclusively coming from the SGPIO and SATA backplane. Finally, make sure that the +5V rail voltage drops to 0V after going into ACPI S5 with this patch applied and the SGPIO cable connected. Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07soc/intel/apollolake: Add UFS InterruptSean Rhodes
According to Intel document number 336561, GLK has UFS (0x1d), so add the PCI interrupt. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07soc/intel/apollolake: Remove SD Card interrupt for GLKSean Rhodes
According to Intel document number 336561, G, SD Card (0x1b) does not exist on GLK, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07mb/siemens/mc_ehl2: Use preset driver strength for SD-CardMario Scheithauer
The intention of predefining driver strength is to avoid that the OS SD-Card driver changes this setting. Change-Id: I02fdac94462da1cd77f8dc972faf16f28d94c946 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-07soc/intel/ehl: Set Ethernet controller to D0 power stateMario Scheithauer
To be able to change the MAC addresses, it is necessary that the controllers are in D0 power state. As of FSP MR3, Intel has set the controllers to D3 power state at the end of FSP-S TSN GbE initialization. This patch sets the state back to D0 before the programming of the MAC addresses. Test: - Build coreboot with FSP MR4 for mc_ehl2 mainboard - Boot into Linux and check MAC addr via 'ip a' Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07mb/google/nissa/pujjo: Change TPM I2C freqeuncy to 1 MHzLeo Chou
Change the TPM I2C freqeuncy to 1 MHz for pujjo. BUG=b:249953707 TEST=On pujjo, all timing requirements in the spec are met. Frequencies: pujjo - 987.80 kHz Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: If99b5022a9b67e9c63c440a1e398d56bb2c467e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-07mb/google/nissa/var/yaviks: Config I2C frequencyWisley Chen
Update parameters for all I2C devices. After applied this patch, the measured the I2C frequency meets spec BUG=b:249953708 TEST=FW_NAME=yaviks emerge-nissa coreboot flash and measure the all I2C devices 1. I2C0 (TPM): 980.6 Khz 2. I2C1 (TouchScreen); 392.6 Khz 3. I2C3 (Audio): 394.9 Khz 4. I2C5 (Touchpad): 391.6 Khz Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I33c2891f17bc3c572bbfcbf30bbbdef9eb850ce7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-07soc/amd/{CZN,MDN,PCO}: Fix building with only single RW regionMatt DeVillier
apu/amdfw_a was only getting added to CBFS when VBOOT_SLOTS_RW_AB was selected, but needs to be added in the RW_A only case as well (VBOOT_SLOTS_RW_A). Since VBOOT_SLOTS_RW_AB selects VBOOT_SLOTS_RW_A, we can guard amdfw_a and _b separately and both will be added in the RW_AB case. TEST=build google/zork with VBOOT_SLOTS_RW_A or VBOOT_SLOTS_RW_AB selected, ensure amdfw_a and amdfw_b are added to correct CBFS regions as appropriate. Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68126 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-07soc/amd/{stoney,picasso}/Kconfig: Fix guarding of amdfwMatt DeVillier
apu/amdfw should be restricted to the RO region only when building with VBOOT + any RW region (RW_A or RW_A + RW_B); it is not tied to ChromeOS in any way. Fix guarding to match newer AMD platforms (eg, CZN/MDN). TEST=build google/zork without CHROMEOS, with VBOOT_SLOTS_RW_A Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68125 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-07soc/intel/alderlake: Support Raptor Lake VR Fast VMODEJeremy Compostella
RaptorLake introduces the support of the Voltage Regulator Fast Vmode feature. When enabled, it makes the SoC throttle when the current exceeds the I_TRIP threshold. This threshold should be between Iccmax.app and Iccmax and take into account the specification of the Voltage Regulator of the system. This change provides a mean to: 1. Enable the feature via the `vr_config->enable_fast_vmode'. If no I_TRIP value is supplied FSPs picks an adapted I_TRIP value for the current SoC assuming a Voltage Regulator error accuracy of 6.5%. 2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip' field. These new fields are considered independent from the other `vr_config' fields so that the board configuration does not have to unnecessarily supply other VR settings to enable Fast VMode. Information about the Fast VMode Feature can be found in the following Intel documents: - 627270 ADL and RPL Processor Family Core and Uncore BIOS Specification - 724220 RaptorLake Platform Fast V-Mode - 686872 RaptorLake Lake U P H Platform BUG=b:243120082 BRANCH=firmware-brya-14505.B TEST=Read I_TRIP from the Pcode and verify consistency with a few `enable_fast_vmode' and `fast_vmode_i_trip' settings. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-07mb/google/skyrim: Override SPI flash bus speedKarthikeyan Ramasubramanian
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version where required schematics update is done. BUG=b:245949155 TEST=Build and boot to OS in Skyrim with 100 MHz SPI bus speed. Perform warm and cold reboot cycles for 100 iterations each. Observe that the boot time improved by ~115 ms compared to 66 MHz SPI flash bus speed. At 66 MHz: 508:finished loading body 538,319 (83,806) 11:start of bootblock 1,196,809 (624,777) 14:finished loading romstage 1,236,905 (39,163) 970:loading FSP-M 1,237,056 (37) 15:starting LZMA decompress (ignore for x86) 1,237,073 (17) 16:finished LZMA decompress (ignore for x86) 1,358,937 (121,864) 8:starting to load ramstage 2,010,304 (0) 15:starting LZMA decompress (ignore for x86) 2,010,312 (8) 16:finished LZMA decompress (ignore for x86) 2,067,181 (56,869) 971:loading FSP-S 2,078,232 (7,999) 17:starting LZ4 decompress (ignore for x86) 2,078,253 (21) 18:finished LZ4 decompress (ignore for x86) 2,084,297 (6,044) 90:starting to load payload 2,316,933 (5) 15:starting LZMA decompress (ignore for x86) 2,316,947 (14) 16:finished LZMA decompress (ignore for x86) 2,339,819 (22,872) Total Time: 2,464,338 At 100 MHz: 508:finished loading body 515,118 (59,364) 11:start of bootblock 1,115,043 (566,110) 14:finished loading romstage 1,146,713 (29,697) 970:loading FSP-M 1,146,865 (38) 15:starting LZMA decompress (ignore for x86) 1,146,881 (16) 16:finished LZMA decompress (ignore for x86) 1,249,351 (102,470) 8:starting to load ramstage 1,900,568 (1) 15:starting LZMA decompress (ignore for x86) 1,900,576 (8) 16:finished LZMA decompress (ignore for x86) 1,956,337 (55,761) 971:loading FSP-S 1,967,357 (7,930) 17:starting LZ4 decompress (ignore for x86) 1,967,377 (20) 18:finished LZ4 decompress (ignore for x86) 1,972,925 (5,548) 90:starting to load payload 2,205,300 (6) 15:starting LZMA decompress (ignore for x86) 2,205,313 (13) 16:finished LZMA decompress (ignore for x86) 2,227,087 (21,774) Total Time: 2,349,804 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5e8db22151fbc2db1f9e81b3644338348160736d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-10-06smbios: Add API to generate SMBIOS type 28 Temperature ProbeErik van den Bogaert
Based on DMTF SMBIOS Specification 3.5.0 Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com> Change-Id: I710124ca88dac9edb68aab98cf5950aa16c695d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67926 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06treewide: use predicate to check if pci device is on n-th busFabio Aiuto
use function to check if pci device is on a particular bus number. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I4a3e96381c29056de71953ea2c39cd540f3df191 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68103 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06treewide: use predicates to check for enabled pci devicesFabio Aiuto
use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06include/device/device_util.c: add predicates for pci devicesFabio Aiuto
add functions to check whether a device is enabled pci device or a pci device on a specific bus number. TEST: compile and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I3257c8404017372f6cdd9f6cf9453502447343a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68101 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06mb/google/brya/var/mithrax: adjust I2C5 times for TPJohn Su
This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C5 to follow I2C specification. I2C_TCHPAD_SCL high period time is from 0.53 us to 0.6952 us. I2C_TCHPAD_SDA hold time is from 0.13 us to 0.4623 us. BUG=b:249031186 BRANCH=brya TEST=EE check OK with test FW and TP function is normal. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5977f0dbba8924cc8a1c72c36358d6ba6f2de940 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67920 Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-10-06mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization errorLeo Chou
Configure eMMC DLL tuning values for Pujjo board. BUG=b:241854926 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ic36c817fa546741e394668297ca43db3a45ee105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68095 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06mb/lenovo/t440p: Enable PCI 00:01.1 bridge for dGPUNico Huber
An optional dGPU can be connected to the second PEG bridge: -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller +-01.0-[01]-- +-01.1-[02]----00.0 NVIDIA Corporation GK208M [GeForce GT 730M] It's possible that the 01.0 bridge is never populated, but we have to leave it on anyway so 01.1 can be enumerated. Change-Id: Ieab7a7bf3b31b4ee9d9f12b5d827d866c87356e1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/kontron/bsl6: Set board type to mobile for memory configNico Huber
Given the embedded nature, the Halo SKU, SO-DIMMs and 1 DIMM per channel, `mobile` seems to come closest. Change-Id: Ia27f1e4dec0a0d06be3d8c08bfe82becd41a2149 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/google/nissa/var/pujjo: Disable stylus GPIO pins based on fw_configLeo Chou
BUG=b:250470706 TEST=Boot to OS on pujjo and check that stylus GPIO are configured based on fw_config. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I4218748cb06426a918d89f688599c652062ac78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68075 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06soc/intel/apollolake/acpi: Add PCIEXBAR to MCHCSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/google/skyrim: Fix SMMSTORE size, alignmentMatt DeVillier
SMMSTOREv2 requires 64k min size, 64k alignment. TEST=build skyrim with SMMSTOREv2 enabled Change-Id: I3501b6036df9ee1049a92e26a7b72e53b4604f60 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-06mb/google/guybrush: Fix SMMSTORE size, alignmentMatt DeVillier
SMMSTOREv2 requires 64k min size, 64k alignment. TEST=build guybrush with SMMSTOREv2 enabled Change-Id: I78cb873a5634c659067367260cc7063fbd60d77a Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-06soc/intel/meteorlake: Make use of is_devfn_enabled() functionSridhar Siricilla
The patch uses is_devfn_enabled() function to enable the TBT PCIe ports through FSP-M and FSP-S UPDs. Also, removes unused tbt_pcie_port_disable array member from soc_intel_meteorlake_config struct. TEST=Build coreboot for Google/Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie55e196bd8f682864b8f74dbe253f345d7184753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-06mb/starlabs/lite/glkr: Enable configuring Fast Charging on the Lite Mk IVSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I714867d455c4e0d01d6cb1cb9dc64669fb41100c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06ec/starlabs/merlin: Add support for enabling fast chargeSean Rhodes
The Lite Mk IV's can enable fast charging, with support up to 100W via USB-C PD 3.0. The default for this is disabled, as it can reduce battery life span. This patch adds the option to enable fast charging, by writing 0x01 to 0x18 in the EC space. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie01eb59d3f41b242190973fd9c58b1494320c12a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/starlabs/lite: Add variant specific cmos.layout and cmos.defaultSean Rhodes
Add variant specific cmos files, which avoid options like "FastCharge" existing in platforms that don't support such options. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04264cf72d47ef719acfd144d8bf9acb0ceccc11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06mb/starlabs/starbook: Add variant specific cmos.layout and cmos.defaultSean Rhodes
Add variant specific cmos files, which avoid options like "Thunderbolt" existing in platforms that don't support such options. This change also removes entries that were never used, including: * smi_handler * usb_always_on Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I359e5c5bbf29eb474f2d3bc42a8e80afc0a5d38a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06sb/intel/common/gpio.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Iba746431496b30daba098716337b688314eac283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/i82801gx/bootblock.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I61d4a188dc9526b71277c05dd317255fc9727414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/i82801gx/early_init.c: Include common/rcba.hElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I5d9bc4ae942ba171a5d3ef4f77da69398fbac692 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06lib/prog_loaders.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I00e9636fa49c402f38119ba0bfc85c8c193fec12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06lib/prog_ops.c: Add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibacf704d362eecea3f7216ffcb02c2ef6f9a6d8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06nb/intel/i945/memmap.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie5d7d1dd446428d12a2f904545682e8fb9cd82f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/pmbase.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie23472d45c8232f5c907ec1757a648fa1a27d533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/rtc.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibcd61e44f8e165627851e2c5325985f0765634b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06sb/intel/common/early_smbus.h: Add <device/pci_type.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-06security/memory/memory.h: Add <stdbool.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I908445b9f87b3db90527955116db22bbee674e1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-06nb/intel/i945/rcven.c: Sort includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I360e4f8ed3b87225a09c7cbb761c570a579771cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06nb/intel/i945/raminit.c: Clean up includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I94a81a30950cca6be5ba36a25f8bc6f87c2aad2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06device/device_const.c: Clean up includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7e84760566db5da7ff88dcbe9fb028ebcb390bdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/x86/pae/pgtbl.c: Clean up includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0ab39ff20b0fb59026063e064e20ce901c2985fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/68042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/intel/common/fsb.c: Sorte includes and add <stdint.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9b85836ac21da5b885a97f05e3973fb23a052fd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/intel/car/romstage.c: Clean up includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I84639389ac1066468b82bb13d684e5423b909fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06console/vtxprintf.c: Add <stdarg.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I221a2bdb19cc7d17265c69d3fe3e1dfb490e7186 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06console/printk.c: Add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I55412395071f0fccb839c40fefda998befaddebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06console/die.c: Add <stdarg.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I2ee8ef017d8a3409cbf47f1ed252a512dead224e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06console/console.c: Sort includes and add <types.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1d2d85ff8cfca58295117b5cb625cadfc9008311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06arch/x86/timestamp.c: Add missing <stdint.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6870fb9f3d41ef5dc6599e979ce0c890a1e145ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06arch/x86/mmap_boot.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I85e60c189c1ec1da5cf0e5b864447ef6f7b3f548 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/x86/smm/smm_module_loader.c: Clean up includesElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I36c54e62797e67c1732f8deaf8843daf35610e22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06cpu/x86/mtrr/mtrr.c: Add missing <stdbool.h>Elyes Haouas
Remove <stdint.h>, <stddef.h> and add <stdbool.h>. All of them are included through <types.h>. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If5296988c68302896e3676d7b80d0f133d5d4264 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06console/vsprintf.c: Add <stdarg.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I8c61f2a033f9630d3fa3eb5e364e6f38de5c7064 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-06soc/qualcomm: Update the wait time for checking PCIe link upShelley Chen
Currently, after the PCIe link is initialized, we wait 100ms every time the link is not up anymore. However, this causes significant delay. Assuming the first check is false, we'd like to increase the frequency of checks for the link to be up. Changing to check every 10ms instead. This seems to save about 90ms in the device configuration stage of bootup on herobrine. BUG=b:218406702 BRANCH=None TEST=reboot from AP console (on herobrine) prior to fix (from cbmem dump): 40:device configuration 919,391 (202,861) after fix (from cbmem dump): 40:device configuration 826,294 (112,729) Change-Id: Ic67e7207c1e9f589b34705dc24f5d1ea423e2d56 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: mturney mturney <quic_mturney@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2022-10-06soc/intel/cmn/gfx: Add missing CML-U IGD device IDsMichał Żygowski
Intel Core i5-10210U can have the following IGD Device IDs 0x9B21/0x9B41/0x9BAC/0x9BCA/0x9BCC according to Intel ARK. Some of these IDs were not present in coreboot source nor hooked to the common graphics driver. Add the missing IDs so that the graphics driver will probe on the mentioned processor and detect the framebuffer. TEST=Boot Protectli VP4650 with i5-10210U and see framebuffer is detected when using FSP GOP and libgfxinit. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iee720a272367aead31c8c8fa712bade1b6e53948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67975 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-05ec/lenovo/h8/acpi: Fix wrongly used operatorFelix Singer
Commit 37a89d519d4e ("ec/lenovo/h8/acpi: Replace Not() with ASL 2.0 syntax") mixed up boolean and bit-wise operators while replacing Not() with ASL 2.0 syntax. Thus, fix that. Built dsdt.aml of lenovo/x230 and differs, but it remains the same when this commit is applied after commit 37a89d519d4e. Change-Id: Ifa848aafb5480acaac4fabffcf90a3dbf5248e43 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66380 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-05mb/google/brya/var/brya0: use RPL FSP headersNick Vaccaro
To support an RPL SKU on brya0, brya0 must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for brya0 so that it will use the RPL FSP headers for brya0. BUG=b:248126749 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot brya0 to kernel. Cq-Depend: chromium:3893035, chrome-internal:4983198 Change-Id: I2dd84757532d734ad97b74ba960537d937fb313e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2022-10-05mb/google/brya/var/brya0: add new THERMAL FW_CONFIG fieldNick Vaccaro
Add a new THERMAL FW_CONFIG bitfield for describing power consumption category of SoC. BUG=b:250089101 TEST="emerge-brya coreboot chromeos-bootimage", flash and boot brya0 and skolas to kernel. Change-Id: Iba3bd87abd4c112ceff4bbe51a7cf9eae3a694f2 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-10-05mb/google/brya/var/skolas: sync brya0 and skolas FW_CONFIGNick Vaccaro
1) Make the skolas FW_CONFIG field defintions compatible with the brya0 FW_CONFIG field definitions to support skolas being a SKU of brya0, and in sync with the config.star definitions for the FW_CONFIG field for brya0 and skolas. - brya0 specific changes: 1) remove WFC_MIPI_OVTI5675 definition (was 1) 2) redefine WFC_MIPI_OVTI8856 from 2 to 1 3) define new WFC_MIPI_KBAE350 camera type as 2 - skolas specific changes: 1) remove WFC_MIPI_OVTI5675 definition (was 1) 2) redefine WFC_MIPI_OVTI8856 from 2 to 1 3) define new WFC_MIPI_KBAE350 camera type as 2 2) Add support back in for UFC_MIPI_OVTI5675 in brya0 now that FW_CONFIG defines are fixed. BUG=b:248126749 TEST="emerge-brya coreboot chromeos-bootimage", flash brya0 and verify it boots successfully to kernel and that WFC, UFC, and audio works on skolas and brya0. Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I3be26e0a05f4dc08e5dc3f6ef7b71bdd8fd4f859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2022-10-05mb/google/brya/variant/brya0: Add power limits for RPL SoCNick Vaccaro
Add the RPL CPU power limits to brya0's power limit table to support both the brya0 ADL sku and the new RPL sku. BUG=b:248126749 TEST="emerge-brya coreboot chromeos-bootimage", flash skolas with image-brya0.serial.bin and verify skolas boots successfully to kernel. Change-Id: I2ac067f98f1ff8f86cff0ed0e15010f454d9c91c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-10-05drivers/crb: Initialize Intel PTT control areaMichał Żygowski
On newer systems such as Alder Lake it has been noticed that Intel PTT control area is not writable until PTT is switched to ready state. The EDK2 CRB drivers always initialize the command/response buffer address and size registers before invoking the TPM command. See STEP 2 in PtpCrbTpmCommand function in tianocore/edk2/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c Doing the same in coreboot allowed to perform PTT TPM startup successfully and measure the components to PCRs in ramstage on an Alder Lake S platform. TEST=Enable measured boot and see Intel PTT is started successfully and no errors occur during PCR extends on MSI PRO Z690-A DDR4 WIFI. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia8e473ecc1a520851d6d48ccad9da35c6f91005d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63957 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-04soc/intel/alderlake: Fix UFS OCP fabric timeoutMeera Ravindranath
The delayed return of certain fetch instruction from memory to the UFS causes the OCP fabric to timeout on the transaction and become non-responsive. As recommended by the SoC and IP teams,program the OCP fabric register to avoid the timeout in the OCP fabric. This patch adds the following changes 1. Program the OCP fabric registers in the PS0 routine. 2. Move the ssdt contents of UFS to dsdt asl code to avoid duplication of UFS device creation BUG=b:240222922 TEST=Build and boot Nirwen UFS board, observe no system hang during Chrome PLT test. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-10-04mb/google/skyrim: Enable amdfw separationKarthikeyan Ramasubramanian
Select the config to separate the AMDFW binary from the verified boot section. BUG=b:203597980 TEST=Build Skyrim BIOS image and boot to OS with PSP verstage passing the hash table and PSP verifying the binaries against the hash table. Observe boot time improvement of ~120 ms while operating SPI bus at 66 MHz with PSP verstage enabled. Before this patch series: 508:finished loading body 1,978,053,432 (201,518) After this patch series: 508:finished loading body 7,948,797,849 (83,460) Change-Id: I78ec6d28b4c5fc40bdade47489d58180a54dee4d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Tim Van Patten <timvp@google.com>
2022-10-04mb/google/skyrim: Update Kconfig to point to SPLJon Murphy
ChromeOS requires a custom SPL table. Update Kconfig to point to the ChromeOS version of the SPL resident in the blobs directory. Bug=b:245727030 Test=Boots Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I70dcb19983c970283ee887b78a18c0668e83d4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67928 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04mb/msi/ms7d25: Populate SMBIOS product name based on CNVi presenceMichał Żygowski
MSI PRO Z690-A WIFI DDR4 and MSI PRO Z690-A DDR4 are basically the same boards, except the latter has no WiFi populated. Check the CNVi WiFi presence and return correct SMBIOS product name string. TEST=Check SMBIOS product name on both WiFi and non-WiFi variants in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5fedbce413dfb6a589a406d1e34e3e114ca6a40f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68078 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-03drivers/smbus: initialize SC16IS7XX I2C to UART converter chipHusni Faiz
This patch adds the functionality to initialize the sc16is750 i2c to uart converter chip with a 14.7MHz input clock to support 115200 baud rate. Change-Id: Ib31188b8c0f9b0ce9454da984e630eca9101d145 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-10-03mb/google/skyrim: Adjust Makefile to look for SPDJon Murphy
Adjust the Makefile to look for SPD source Makefile. The current SPD guard isn't set up correctly and is attempting to build the APCB with SPD when SPD isn't present. BUG=b:249988439 TEST=util/abuild/abuild -x -t GOOGLE_MORTHAL --verbose util/abuild/abuild -x -t GOOGLE_SKYRIM --verbose util/abuild/abuild -x -t GOOGLE_WINTERHOLD --verbose Change-Id: I9cf13acb1188309ea6a1e6bdacc37d80b01f70a8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68018 Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02soc/amd/(common,mendocino)/psp_verstage: Pass PSP FW hash tableKangheui Won
Copy AMD PSP fw hash table into memory, then pass it to the PSP. The PSP will use this hash to verify it's the correct firmware bundled with coreboot build and not replaced. BUG=b:203597980 TEST=Build Skyrim BIOS image with the hash table and boot to OS after PSP verified the binaries against the hash table. Change-Id: I84bea97c89620d0388b27891a898ffde77052239 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60291 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02soc/amd/mendocino: Add build rules to separate signed PSP/AMDFWKarthikeyan Ramasubramanian
Add build rules to separate signed PSP/AMDFW. Also add build rules to add the generated hash table containing SHA digest of individual PSP FW components into CBFS. This will allow verified boot to load and verify less components from SPI rom which means faster boot time. BUG=b:206909680 TEST=Build Skyrim with modified fmap and Kconfig Change-Id: If54504add72b30805b6874bee562e0b9482782b9 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67260 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02soc/amd/common: Add a config to keep signed AMD/PSP FW separatelyKarthikeyan Ramasubramanian
Enabling this config will put signed amd firmwares into SIGNED_AMDFW_[AB] region which is outside FW_MAIN_[AB]. Vboot only verifies FW_MAIN_[AB] so these regions will not be verified by vboot, instead the PSP will verify them. As a result we have less to load and verify from SPI rom which means faster boot time. BUG=b:206909680 TEST=Build Skyrim with modified fmap and Kconfig. Change-Id: If4fd3cff11a38d82afb8c5ce379f1d1b5b9adfbf Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59867 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02mb/google/brya/var/agah: Update NVVDD VR PGOOD GPP_E3Tarun Tuli
This pin was originally set as output in error. This should be a input to behave like GPP_E16 on the older variants. BUG=b:239721380 TEST=build Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ic0f793ff52adb425ae5378b88d2837bb9e58edd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-02mb/google/nissa/var/xivu: Add DPTF parameters for XivuIan Feng
The DPTF parameters were verified by the thermal team. BUG=b:249446156 TEST=emerge-nissa coreboot chromeos-bootimage Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ic7e0c73815dd02b97d89f94fab09a241b6279830 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-10-02mb/google/brya: Create lisbon variantKevin Chiu
Create the lisbon variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:246657849 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_LISBON Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ia31752765657054b28ea16b046b63c38a72f95bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-10-02drivers/ipmi: prepare for adding more interfacesSergii Dmytruk
De-duplicate common initialization code (self-test and device identification) and put it in a new ipmi_if.c unit, which is supposed to work with any underlying IPMI interface. Change-Id: Ia99da6fb63adb7bf556d3d6f7964b34831be8a2f Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-01mrc_cache: Update metadata signatureJulius Werner
CB:67670 recently changed the format of the MRC metadata header, but left the signature the same. That kinda defeats the purpose of having a signature which is to make a data structure recognizable (because now the same signature can refer to two different structures that cannot be otherwise distinguished). While we don't know of any use case where anything other than coreboot currently parses this data structure (other than a ChromeOS-internal utility that's about to be removed), it's probably better to still switch to a different signature for the new header format just to stay on the safe side (e.g. if we ever need to start parsing this somewhere else in the future). CB:67670 only landed a week ago so hopefully the old signature + new format variant hasn't had much time to escape into the wild yet. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ic08b23862720db832a08dc4c6818894492f43cc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68012 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30soc/rockchip/rk3288/clock.c: Remove trailing semicolonElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I0d03bd43b33570ee50f145ea6fd716c4072a11d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-30soc/nvidia/tegra210: Remove trailing semicolonsElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibdbd9ae90aa9683f0381d1a2458f6918ce4c0faa Reviewed-on: https://review.coreboot.org/c/coreboot/+/67967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-30soc/nvidia/tegra124/sor.c: Remove trailing semicolonElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I9563a7f6d37937a4951c5053dcfee140579098e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-30mb/google/oak/bootblock.c: Replace comma with semicolonElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4721d24aecd53c51c66c7d448b7c331d50a09712 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-30mb/google/gru/mainboard.c: Replace comma with semicolonElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibc257c2306351614669bd25ac83c24475f80fc6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-09-30mb/google/skyrim: move EC switch selection from ChromeOS to VbootMatt DeVillier
This is a vboot feature, not a ChromeOS one, and unless selected by vboot, compilation will fail in the non-ChromeOS + vboot build case. TEST=build/boot skyrim w/vboot, w/o ChromeOS Change-Id: If9a5343907457bf3319f045262fdddf7eae2f1cb Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67995 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30mb/google/guybrush: move EC switch selection from ChromeOS to VbootMatt DeVillier
This is a vboot feature, not a ChromeOS one, and unless selected by vboot, compilation will fail in the non-ChromeOS + vboot build case. TEST=build/boot guybrush w/vboot, w/o ChromeOS Change-Id: I3108bcc8dfeacd99c9f5d36bd915d590292fef00 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67994 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30guybrush: mark RO_GSCVD area unusedHimanshu Sahdev
This area relates to storing of AP RO verification information. CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and guybrush is using TPM_GOOGLE_CR50. Signed PSP verstage has the FMAP embedded. Since CB:67376 shifted the RO section up by 8K, they were misaligned. Hence marking this area as unused instead of removing the same to work around ChromeOS infrastructure shortcoming. Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Change-Id: Id852e5b5c1f777992a96a75143757f4df8d975b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67901 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30mb/prodrive/atlas: Add Kconfig option to enable SaGvLean Sheng Tan
It turns out that one can use Kconfig options to specify values for devicetree options, as long as the resulting expression is a compile time constant. Use this to configure SaGv for Atlas: enable it by default, but allow SaGv to be disabled manually for convenience when testing. Enabling SaGv makes MRC train the RAM multiple times, which takes a significant amount of time. For further info on SAGV on ADL, please refer to Intel Doc 655258 (Alder Lake Datasheet) section 5.1.3.2. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I3c6ac25d414122c408f2348d12dba8dce909e567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30soc/intel/adl: Add config option to enable FSP-S SATA test modeLean Sheng Tan
For further info on SATA test mode, please refer to this doc: https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/sata-mqst-setup-paper.pdf Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I6ef79fc5723348d5fd10b2ac0847191fa4f37f41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67410 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30soc/amd/common/psp_verstage/fch: use [read,write]8p to avoid typecastsFelix Held
Also add missing device/mmio.h include. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I03af0772c735cdc7a4e221770dc528724baa7523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67983 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30soc/amd/common/block/smbus/smbus: use [read,write]8p to avoid typecastsFelix Held
Also add missing device/mmio.h include. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f3f7ea36896c8e55c62acd93fe8fc4fb7c74b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67982 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>