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Change-Id: I335487ca1b17ab958c0d0238f425b92b430014ca
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I51dd9eb5a2fef5800670f981275139e932af2be0
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81493
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If68303cd59b287c8a5c982063b2ab75fd74898d6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
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Change-Id: Id604dc981d6ca0a8163b7477b7916210faa56a77
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I7071cbcc26e2080020e83b894cf4ac4ef46913c3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I2dae34441909f6135b95e7b017659ce4f4666b4e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: If2c2138ed3dc437b924297330805caa8c357853d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81460
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I140daa5b862ffd3a5b5468d7cb9dbdd81426855e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81459
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0203e77dd23fa026cd252abbda50f1e9f6892721
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I9ba061fe0b1396ccc1597e26685a6b4e312e3549
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I1bb4a052a4e74850660944b687c21e817eb437b2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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With SMM holding page tables itself, we can consider SMM support stable
and safe enough for general use.
Also update the respective documentation.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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When switching back and forth between 32 to 64 bit mode, for example to
call a 32-bits FSP or to call the payload, new page tables in the
respective stage will be linked.
The advantages of this approach are:
- No need to determine a good place for page tables in CBFS that does
not overlap.
- Works with non memory mapped flash (however all coreboot targets
currently do support this)
- If later stages can use their own page tables which fits better with
the vboot RO/RW flow
A disadvantage is that it increases the stage size. This could be
improved upon by using 1G pages and generating the pages at runtime.
Note: qemu cannot have the page tables in the RO boot medium and needs
to relocate them at runtime. This is why keeping the existing code with
page tables in CBFS is done for now.
TEST: Booted to payload on google/vilbox and qemu/q35
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80337
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When linking in page tables more place is needed. Size the bootblock is
top aligned, this has no impact the final size for existing setups.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I23f176d63d3c303b13331a77ad5ac6c7a19073d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This does the following:
- Top align the bootblock so that the only the memory needed gets used.
This might slightly reduce the time the PSP needs to decompress the
bootblock in memory
- Use a memory directive to assert that the 16bit code is inside the top
64K segment
- Use the program counter less. While the BDF linker is happy about
running the program counter backwards, LLD is not. There is no
downside to this.
- Use a symbol rather that the program counter for sections. LLD gets
confused when (.) is used along with '<': it places the section at the
start of the memory region, rather than at the program counter. Using
a variable name works around this.
- Use a 'last_byte' section to make sure the first instruction is at
0xfff0. Both the BDF and the LLD linkers seems to work well with this
code
TEST: Both BFD and LLD are able to link the bootblock
Change-Id: I18bdf262f9c358aa01795b11efcb863686edc79c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Most of the original secdata_tpm.c was TPM2-specific implementation.
Just moving the code around, with trivial tweaks:
- drop now unnecessary #ifdef directives from _factory_initialize_tpm()
- drop leading underscore from _factory_initialize_tpm{1,2}() (external
identifiers should not start with an underscore in C)
- drop unused <security/vboot/tpm_common.h> include and sub-includes of
tss.h which should be considered its part (so this isn't an indirect
inclusion)
- fixed formatting of RETURN_ON_FAILURE() which didn't have slashes
aligned no matter what tab width was used
Change-Id: I0090b748d7d3b2d76a941b87b5885682fd81c4fc
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81415
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This prepares the code for enabling both CONFIG_TPM1 and CONFIG_TPM2
during compilation, in which case actual TPM family in use can be
determined at runtime.
In some places both compile-time and runtime checks are necessary.
Yet in places like probe functions runtime state checks don't make sense
as runtime state is defined by results of probing.
Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69161
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No functional changes. Refactor code such that there won't be any
compiler or linker errors if TSS 1.2 and TSS 2.0 were both compiled
in.
One might want to support both TPM families for example if TPM is
pluggable, while currently one has to reflash firmware along with
switching TPM device.
Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Via an out parameter. This is needed to be able to dynamically pick TSS
implementation based on the information discovered on probing.
Change-Id: I5006e0cdfef76ff79ce9e1cf280fcd5515ae01b0
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69159
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0ce2b61329efede1ba8a02446610e3eb635ceedc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81462
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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For dram_type 21 the switch case in use_ddr4_params function falls to
default. This adds SPD_DRAM_LPDDR5X dram_type case to switch case block
for dram_type 21 in the function.
With this patch below NOTE will not be observed in the log:
[NOTE ] Defaulting to using DDR4 params. Please add dram_type check for 21 to use_ddr4_params
BUG=None
BRANCH=None
TEST=Boot brox SKU1/SKU2 and verify logs for default case
Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
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Testing on the unmatched shows the code no longer works completely
correctly; Linux has taken over the handling of misalignment
anyway, because handling it in firmware, with the growing
complexity of the ISA and the awkward way in which it
has to be handled, is more trouble than its worth.
Plus, we don't WANT misalignment handled, magically, in
firmware: the cost of getting it wrong is high (as I've
spent a month learning); the performance is terrible (350x
slowdown; and most toolchains now know to avoid unaligned
load/store on RISC-V anyway.
But, mostly, if alignment problems exist, *we need to know*,
and if they're handled invisibly in firmware, we don't.
The problem with invisible handling was shown a while back
in the Go toolchain: runtime had a small error, such that
many misaligned load/store were happening, and it was
not discovered for some time. Had a trap been directed
to kernel or user on misalignment, the problem would
have been known immediately, not after many months.
(The error, btw, was masking the address with 3,
not 7, to detect misalignment; an easy mistake!).
But, the coreboot code does not work any more any way,
and it's not worth fixing. Remove it.
Tested by booting Linux to runlevel 1; before,
it would hang on an alignment fault, as the
alignment code was failing (somewhere).
This takes the coreboot SBI code much closer to
revival.
Change-Id: I84a8d433ed2f50745686a8c109d101e8718f2a46
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81416
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, simply changing the wake event configuration to ANY does
not completely resolve the issue of inserting a pen not waking the
system. The pen actually needs to wake up the system both when plugged
in and when pulled out. This is because in the pen's GPP_F15
configuration, the original attribute is EDGE_SINGLE, which should be
changed to EDGE_BOTH.
BUG=b:328351027
TEST=insert and remove pen can wakes system up.
Change-Id: I1823afd0bcb86804227117d2d5def38788bc7387
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81441
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Create the yavista variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:321583226
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVISTA.
Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02
Signed-off-by: Hsueh Rasheed <hsueh.rasheed@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80342
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Fix compilation errors when compiled for x86_64.
Test: Booted on ibm/sbp1 to linux payload.
Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65
Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81280
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I2285d1bdaa2734658ca1a0cc58ef2294d90d333e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
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Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE
corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration.
BUG=b:329026602
TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up
using EC generated events like AC connect/disconnect.
Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Change-Id: I4a678b433e3e1a492e2a8e679caf75f4741317cb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81485
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ieaaba5b36796d97449896b8475744a21f01e93d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Change-Id: I2c8cc390bed3aef901d6ada19361c35928dfdb0c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81496
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id039ad885d2f08bc3fe09aca740a72a5820f7fcc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
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Change-Id: I6ece868184dd772fc2c3c472ae2172d1c34fb179
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81484
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of using some aritmetics that sometimes works, use the largest
alignment necessary (page tables) and align downwards in the linker
script.
This fixes linking failing when linking in page tables inside the
bootblock.
This can result in a slight increase in bootblock size of at most 4096 -
512 bytes.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I78c6ba6e250ded3f04b12cd0c20b18cb653a1506
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80346
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move it downwards allows for a larger bootblock, which comes in handy if
romstage or page tables are linked inside the bootblock.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib37846c0b039d89396839ffa6047b18bcc228e02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80347
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to preprocess linker scripts the target architecture needs to
be specified. With clang this needs to be set via a cli argument.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4340681e30059d6f18a49a49937668cd3dd39ce1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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fsp_mrc_version() function does not need to perform a CBFS access to
to get an address to the FSP-M blob as the caller,
do_fsp_memory_init(), already has it loaded. In addition to make the
code simpler, it avoids an unnecessary decompression of the FSP blob
if `FSP_COMPRESS_FSP_M_LZ4' or `FSP_COMPRESS_FSP_M_LZMA' are set.
TEST=Verified on Meteor Lake rex
Change-Id: If355b5811a09a0b76acc8a297db719d54caedc54
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81256
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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FSP2.4 and previous FSP versions have different FSP-T UPD
parameter settings.
Change-Id: I48384944ac69636cca2acd8169d3dd15f90362ec
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81313
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DDR support codes across generations are similar. Share the codes
to improve code reuse.
TEST=intel/archercity CRB
Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81219
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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This is just a start. We are playing catch up.
7 down, 70+ to go.
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Change-Id: I5dac8613020e26ec74ac1c74158fc9791553693f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Return statement is not useful in void function.
Change-Id: I8cf020de335e4da933b7bbdc27b7ac6f31afe885
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81430
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Return statement is not useful in void function.
Change-Id: Idb8e07f48043452b329d255fe457f00317c017ae
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81429
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds timestamp start/end entries around the eSOL
implementation to track the panel initialization time while rendering
the eSOL screen.
TEST=Able to build and boot google/omnigul.
555: started early sign-off life (eSOL) notification 643,694 (40)
556: finished early sign-off life (eSOL) notification 1,072,143 (428,449)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I51c04fc4bd2540b3f42e2f896178521d297ef246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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This patch adds timestamp entries for eSOL (early Sign-Off Life).
This is critical to tracking the panel initialization time while
rendering the eSOL screen.
TEST=Able to build and boot google/omnigul.
555: started early sign-off life (eSOL) notification 643,694 (40)
556: finished early sign-off life (eSOL) notification 1,072,143 (428,449)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I33f7f3a8622600ef23163faf45e2da7b96d6bbdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81386
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The memmap_early_dram struct is now only used inside the non-CAR
memmap.c, so move the struct definition there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id2bb3d3a9e01e9bae9463c582cb105b95c673a38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Only the VGA MMIO range used the VGA_MMIO_* defines, but instead of
using constants for the end of the region before that and the beginning
of the region after that, the VGA_MMIO_* defines can be used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45c3888efb942cdd15416b730e36a9fb1ddd9697
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If3424df80655a150f27c7296a5683b528873816b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Since the code for reporting the memory map below cbmem_top is basically
identical for all non-CAR AMD SoCs, factor this out into a common
read_lower_soc_memmap_resources implementation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id64462b97d144ccdf78ebb051d82a4aa37f8ee98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81389
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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The latest Clevo boards connect the TAS5825M to one of the I2C
connections instead of the SMBus connection. The I2C ops are compatible
with SMBus, so always use them.
Tested on system76/oryp6 (uses SMBus) and in-development system76/oryp12
(uses I2C3). TAS5825M init is successful and speaker output works.
Change-Id: I2233d6977fd460b53e27260cdfabe42e30b98041
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
|
|
Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs.
TEST=intel/archercity CRB
Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Since there's no code using those defines drop them.
TEST=intel/archercity CRB
Change-Id: I507b08a62ebeae14a1e63f4340b0592605a32477
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81369
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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To bring genoa_poc more in line with the other AMD SoCs, move the
reporting of the memory map up to cbmem_top from the openSIL-specific
add_opensil_memmap function to read_soc_memmap_resources. This is a
preparation for making this code common for all newer AMD SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic06282baa3bb9a65d297b5717697a12d08605d2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81388
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Other files in the commits that added these files were licensed under
GPL-2.0-only, and the project as a whole is GPL-2.0-only, so use that
as the license.
Change-Id: I6c1a7ba582f61f98069ebf3857a8b5bdc8588c3e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81421
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When the concerned chip.h file is included in a source file, it causes
compilation error saying unknown type name bool. Fix it by including the
stdbool.h file in the chip.h file.
BUG=None
TEST=Build Brox by including the chip.h file in one of the source files.
Change-Id: I4159e2c281c3e89dc45555ce38ad8637a3bf8587
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Older parts do not have the menvcfg csr.
Provide a Kconfig variable, default y, to enable it.
Check the variable in the payload code, when coreboot SBI
is used, and print out if it is enabled.
The SiFive FU540 and FU740 do not support this register;
set the variable to n for those parts.
Add constants for this new CSR.
Change-Id: I6ea302a5acd98f6941bf314da89dd003ab20b596
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81425
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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Print that the MPIO chip of one of the MPIO-related PCI device functions
is unused and is skipped, if the type is IFTYPE_UNUSED and the
corresponding PCI device function isn't enabled. This allows to
differentiate between this case and the case where the type isn't
IFTYPE_UNUSED.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4fc28d39a229494b487b300b28f92bf3adad66f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
When the chip of one of the MPIO-related PCI device functions has the
type IFTYPE_UNUSED, there is no corresponding MPIO engine, so replace
'engine' with 'chip' in the warning.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f55a3f8e1d220d4eb7b0287d03b7af2e5d2889f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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Only report the port as present in the MPIO_PORT_DATA_INITIALIZER_PCIE
macro parameter when the device is enabled; otherwise report the port as
disabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieaa2af6c5ff3fc7e25992e7fdf14d37ee4a57d62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81342
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
|
Since we're already passing a pointer to the corresponding device to
per_device_config, we don't need to pass the chip_info as separate
parameter. Before moving the PCIe port function device below the MPIO
chip, the chip_info struct was from a different device, so that change
allows this simplification.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0466f7ad2f5c9874d45712fa9f89b978bd2a09bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
|
Move the gpp_bridge_* device functions that are bridges to the external
PCIe ports below the corresponding mpio chip. This avoids the need for
dummy devices and does things in a slightly more coreboot-native way.
TEST=PCIe lane config reported by openSIL is identical
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I7e39bf68d30d7d00b16f943953e8207d6fe9ef41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81340
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I7626fe9d4740e9f141a674fa457b0714fc38ed91
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Certain SSDs are not detected in the default time window, so
change this to 50ms to allow these SSDs to be detected.
Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81398
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The CPU port is not used so disable it.
Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Change-Id: I8dc80c5bdde61f3c2dc5c9dc67fbc752de7a103f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881.
This was originally assumed to be an FSP/Descriptor/PMC mismatch
but it turns out that the problem was coreboot incorrectly
detecting ASPM support on devices.
Revert so that a proper fix can be applied.
Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Adjust the size of the ME partition to match the descriptor
Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81394
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No variants were ever built with CNVi cards, so disable
this device.
Change-Id: I3725465eae0c7ade3dafa03add151353818ee761
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
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Different SoC generations might have different FSP header files. It is
recommended to put these uncommon header files in soc_util.h so that
Xeon-SP codes refer to soc_util.h to include them in a clean way.
TEST=intel/archercity CRB
Change-Id: Icfc20921efe00bc69b0c16c665f65f5baae4c309
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81229
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch is to add FspProducerDataHeader.h header file to support MRC
version Info in TWL.
BUG=b:296433836
Change-Id: Ie33c681676d2a699b7aec8185dbdb90555ef8fe2
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81037
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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ADL-N FSP uses 202111 Edk2. select UDK_202111_BINDING Kconfig for ADL-N
SoC.
BUG=b:296433836
TEST=Able to build and boot google/crassk.
Change-Id: If277ede4307515035389cd0e9d34c15cc80f278c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80274
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This fixes the warning when an integer is cast to a pointer of a
different size.
Change-Id: Ide2827ec1b86dcbd804be9f3269c6c968cb4257b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
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Remove those MSVC compiler defaults checks so that the GCC defaults for
wchar_t can be used with UDK_202111_BINDING Kconfig.
Compilation error:
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25:
error: static assertion failed: "sizeof (L\'A\') does not meet UEFI
Specification Data Type requirements"
src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/Base.h:807:25:
error: static assertion failed: "sizeof (L\"A\") does not meet UEFI
Specification Data Type requirements"
BUG=b:296433836
TEST=Able to build google/crassk with UDK_202111_BINDING.
Change-Id: Ib2716436a910b43a5e546afdedb9eec88c5da8c6
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81328
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Assign GPP_C0 and enable only the touchscreen. Before modification,
GPP_C0 supplies power to the touchscreen and sensor at the same time.
Now the hardware circuit has been modified, GPP_C0 supplies power to the
touchscreen alone. After the software is synchronously modified, when
the device enters suspend(S0ix), GPP_C0 will not enable VDD, which can
reduce the standby power consumption of the touchscreen when it is
suspended(S0ix), which is about 2.1mW.
BUG=b:304920262
TEST= touchscreen function workable
Change-Id: Ia06209aa8303be4fc0669c5d6e5d7a06e8e9ab99
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81265
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
|
|
Change-Id: I9b29233e75483cda6bf7723cf79632f6b04233b0
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Configure I2C0/1 timing in devicetree to meet timing requirement.
(THIGH(us) minimum is 0.6us).
Before:
I2C0 : THIGH(us) 0.595us
I2C1 : THIGH(us) 0.582us
After:
I2C0 : THIGH(us) 0.673us
I2C1 : THIGH(us) 0.666us
Change-Id: I79af4fde4eb08d4eb896794756a633701bebb755
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81348
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The previous value of 32MB was set to meet Google's ChromeOS reqs,
but hampers real-world performance in Linux/Windows, so increase it
to 128MB to match the "auto" default for the Picasso UEFI firmware.
TEST=build/boot Windows on google/zork (morphius), verify UMA set
to 128MB.
Change-Id: I8c6487a4cb8155f826d20fd3ceca87859829199c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81364
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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After final production, it's possible by setting particular
bit using DCFG the OEM/ODM locks down thermal tuning beyond
what is usually done on the given platform.
In that case user space calibration tools should not try
to adjust the thermal configuration of the system.
By adding new DCFG (Device Configuration) it allows the
OEM/ODM to control this thermal tuning mechanism. They can
configure it by adding dcfg config under overridetree.cb file.
The default value for all bits is 0 to ensure default behavior
and backwards compatibility.
For an example if Bit 0 being set represents Generic DTT UI
access control is disabled and Bit 2 being set represents DTT
shell access control is disabled.
Each bit represents different configuration access control
for DTT as per BIOS specification document #640237.
It also gives the provision for user space to check the current
mode. This mode value is based on BIOS specification document
number #640237.
BUG=b:272382080
TEST=Build, boot on rex board and dump SSDT to check DCFG value.
Also, verified the newly added sysfs attribute "production_mode"
present under /sys/bus/platform/devices/INTC1042:00 path.
Change-Id: I507c4d6eee565d39b2f42950d888d110ab94de64
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78386
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Bitfields with signed integers are not valid C code. This fixes
compilation with clang v16.0.6.
Change-Id: I0b2add2f1078a88347fea7dc65d422d0e5a210a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80638
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates a new tivviks variant, which is a Twinlake
platform. This variant uses Nivviks board mounted with the
Twinlake SOC and hence the plan is to reuse the existing
nivviks code.
BUG=b:327550938
TEST= Genearte the Tivviks firmware builds and verify with boot check.
Change-Id: Ia833a1dad45e13cd271506ade364b116c5880982
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81262
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Adds config-based guards for Usb4CmMode and CnviWifiCore UPDs, specific
to Twin Lake SoCs (SOC_INTEL_TWINLAKE).
Prevents compilation errors due to missing UPD definitions.
BUG=b:330654700
TEST=Able to build google/tivviks.
Change-Id: I6e0a9a7536df6295e23bf06003539e56bb98a311
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81376
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set FW_CONFIG bit 21 to enable ISH PCI device and define ISH main
firmware name so ISH shim loader can load firmware from file system.
ISH also need to be enabled if STORAGE_UFS is set.
BUG=b:280329972
TEST= Set bit CBI FW_CONFIG bit 21
Boot Brox board, check that ISH is enabled and loaded
lspci shows: 00:12.0 Serial controller: Intel Corporation Alder
Lake-P Integrated Sensor Hub (rev 01).
Change-Id: Iadc5108c62737d27642a6948c00b5c122541aaba
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80773
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
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Add IFTYPE_UNUSED as first element to the mpio_type enum. This allows
checking if the type was set in the devicetree, since the default will
now be IFTYPE_UNUSED. If the type is set to IFTYPE_UNUSED although the
corresponding PCI device function, a warning is printed and the PCI
device function is disabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85e2589c021b4f05662369fd551146b6f2fa0ad4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add an IFTYPE_ prefix to all elements of the mpio_type enum to have more
specific names.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81338
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the prefix of the elements of the mpio_engine_type enum from
ENGINE_ to IFTYPE_.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If81c5ea01ba147b71b423004a2199b348ffac99a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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With the last FSP submodule update for Elkhart Lake commit f8df905e7baf
("3rdparty/fsp: Update submodule to upstream master"), the binary name
was changed to FSP.fd.
Change-Id: Ibc87ea2744e971d58e9a402f7cf04ef3f316f3b8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This data is used by smm_region_overlaps_handler(). Callers use this
helper to determine if it's safe to read/write to memory buffers taken
from untrusted input.
coreboot SMI handlers must not be confused into writing over any SMRAM
subregion, which includes the TSEG_STAGE_CACHE and chipset-specific area
(sometimes, IED), not just the handlers.
If stage cache writes were permitted, this could compromise the
integrity of the S3 resume path.
The consequences to overwriting the chipset-specific area are undefined.
Change-Id: Ibd9ed34fcfd77a4236b5cf122747a6718ce9c91f
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80703
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS in brox Kconfig.
This enables a single binary for both SKU1 and SKU2. For SKU2, upon
boot from cold reset, it will disable the UFS Controller and then
trigger a warm boot.
BUG=b:329209576
BRANCH=None
TEST=Boot image on SKU1/SKU2 and check S0ix working.
Change-Id: Iabd0b3a83aa386e09310b671632368807a4018d4
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
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Change-Id: I314d726deaed30e69121126ba6834e4c7cafd090
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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The commit below uses USE_1G_PAGETABLES config flag instead of
the correct USE_1G_PAGES_TLB.
"commit ecbc243a45de3b7894e2fe6c8e22b5d07172274b
("cpu/x86: Add 1GiB pages for memory access up to 512GiB")"
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic19812bc1f90cbe7d3739c42a0314b3650e0501d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Update eMMC DLL settings based on Craaskov board.
BUG=b:318323026
TEST=executed 2500 cycles of cold boot successfully on all eMMC sku
Change-Id: I56f8329c28261c2bcae9d058da929be6763b293c
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Update touchpad and touchscreen I2C timing.
- Data hold time: 300ns - 900ns
BUG=b:328724191
BRANCH=firmware-nissa-15217.B
TEST=Check wave form and met the spec.
I2C1 (touchscreen) Hold time from 83.58ns to 413.87ns
I2C5 (touchpad) Hold time from 95.93ns to 425.27ns
Change-Id: I65fb1298f9e96ab0b63aba436f6a319f21b38925
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
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Adjust touchscreen power sequencing for eKTH5015M.
The INX touch panel (eKTH5015M) contains a pull-up register which causes TCHSCR_REPORT_EN pull-up abnormally from Z1 power on.Because the t25 must be at least greater than 20ms, TCHSCR_REPORT_EN is initialized to GPO_L in the early stage (romstage) to meet the spec.
BUG=b:328170008
BRANCH=firmware-nissa-15217.B
TEST=Build and check I2C devices timing meet spec.
[INFO ] input: Elan Touchscreen as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-ELAN0001:00/input/in4
Change-Id: I50f9c21ddee2bc9c1d313f63049cb587b4ae047a
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81135
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Improves user experience by highlighting a possibility of runtime
hangs caused by unsupported WB caching during NEM.
Recently we have encountered an issue on Intel platform and came to
know about the NEM logical limitation where due to cache sets are not
in power_on_two running into a runtime hang upon enabling WB caching.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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There are 2 ways of referring to linker symbols, as extern
u8[] or extern u8*. Only the former will be correctly
initiated into an immediate operand (a constant) to asm.
DECLARE_REGION defines reference in form of extern u8[].
Use DECLARE_REGION as a standard way for these references.
TEST=intel/archercity CRB
Change-Id: I5f7d7855592d99b074f7ef49c285a13f8105f089
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81097
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Drop RMRR entry for XHCI controller since it's not under BIOS control.
There's no USB-PS/2 emulation done in SMM, hence it's not needed.
TEST=intel/archercity CRB
Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81297
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
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Let ACPI DSDT figure out by itself if a stack is enabled.
Allows to drop uncore_fill_ssdt() on all platforms.
TEST=intel/archercity CRB
Change-Id: Ib9051d608147f2de228509ff6b13871ca3183979
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81273
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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As of now coreboot only supported one PCI segment group and thus the
MMCONF size had to be limited to 256 buses on ibm/sbp1. Since the
default FSP doesn't allow to disable unused IIO stacks a patched
version had to be used. Those unused IIO stacks consume lots of PCI
bus ranges, leaving no free buses for the secondary side behind PCI
bridges. The IIO disable mechanism doesn't work after ACPI G3 exit
and thus requires multiple reboots when the previous state was G3.
Since coreboot now supports multi PCI segment groups enable 512
MMCONF buses on 4S platforms by default and drop the IIO stack
disable UPDs on ibm/sbp1. This allows to boot faster without the
need for a patched FSP.
The use of multiple PCI segment groups might prevent legacy software
from working properly, however the only board where multiple PCI
segment groups are used uses u-root as default payload.
TEST=Booted on ibm/sbp1 to ubuntu22.04 using two PCI segment groups.
TEST=intel/archercity CRB
Change-Id: I4e6e5eca1196d4ab50e43b4b58d24eca444ab519
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add PCI enumeration support by reading the PCIeSegment reported in the
FSP HOB and add it when creating the PCI domain for each stack.
The PCI enumeration will be able to scan the additional PCI segment
groups and properly handle those devices.
TEST=Booted on ibm/sbp1 with multiple PCI segment groups enabled
to ubuntu 22.04.
TEST=intel/archercity CRB
Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79878
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For every PCI segment group generate a new SATC header.
Allows to generate proper ACPI code when multiple PCI segment
groups are enabled.
TEST=Booted on ibm/sbp1 with multiple PCI segment groups.
Properly generates multiple SATC headers.
TEST=intel/archercity CRB
Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Get used to this rate of change, SBI adds one new function a month,
on average, for the last 7 years.
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Change-Id: Iaad763464678d1921dfefdbee1e39fba2fe5585a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In DECLARE_REGION and DECLARE_OPTIONAL_REGION, a set of 3 variables
will be defined, that is the region 'base', 'end' and 'size'.
However, in many codes, the users will only selectively use 'end'
or 'size' instead of both of them, which will trigger compiler errors
for unused variables. This patch sets __maybe_unused attributes on
'end' and 'size' so that users do not need to use all of them.
TEST=intel/archercity CRB
Change-Id: Ia5ed183b2dd7a474ce51de47dbc1f9e3f61e5a41
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81209
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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