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authorSean Rhodes <sean@starlabs.systems>2024-03-21 14:36:58 +0000
committerFelix Held <felix-coreboot@felixheld.de>2024-03-22 16:20:47 +0000
commit185652e2731ffb714f0c07bb8dfdf18ac9a7aede (patch)
treea343434c54555e613f0e8724647cfaf6c434f6a9 /src
parent5827ffcdafbac04ac28e641c934a9c4478ca7a16 (diff)
Revert "mb/starlabs/starbook/{adl,rpl}: Disable GpioOverride"
This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881. This was originally assumed to be an FSP/Descriptor/PMC mismatch but it turns out that the problem was coreboot incorrectly detecting ASPM support on devices. Revert so that a proper fix can be applied. Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/starlabs/starbook/variants/adl/gpio.c8
-rw-r--r--src/mainboard/starlabs/starbook/variants/adl/romstage.c1
-rw-r--r--src/mainboard/starlabs/starbook/variants/rpl/gpio.c8
-rw-r--r--src/mainboard/starlabs/starbook/variants/rpl/romstage.c1
4 files changed, 8 insertions, 10 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
index 988e6defb7..b7c9a8ff34 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c
@@ -209,11 +209,11 @@ const struct pad_config gpio_table[] = {
/* D5: Not Connected */
PAD_NC(GPP_D5, NONE),
/* D6: Clock Request 1 PCH M.2 SSD */
-// PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
/* D7: Clock Request 2 Wireless LAN */
-// PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8: Clock Request 3 LAN */
-// PAD_NC(GPP_D8, NONE),
+ PAD_NC(GPP_D8, NONE),
/* D9: GSPI 2 FPS */
PAD_NC(GPP_D9, NONE),
/* D10: GSPI 2 Clock */
@@ -374,7 +374,7 @@ const struct pad_config gpio_table[] = {
/* H18: CPI C10 Gate */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19: Clock Request 4 CPU M.2 SSD */
-// PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
/* H20: Not Connected */
PAD_NC(GPP_H20, NONE),
/* H21: Not Connected */
diff --git a/src/mainboard/starlabs/starbook/variants/adl/romstage.c b/src/mainboard/starlabs/starbook/variants/adl/romstage.c
index 81f1ef3272..17629b460d 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/adl/romstage.c
@@ -35,5 +35,4 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 4);
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
- mupd->FspmConfig.GpioOverride = 0;
};
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
index 4b4f9ed91c..aba6dc8875 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c
@@ -209,11 +209,11 @@ const struct pad_config gpio_table[] = {
/* D5: Not Connected */
PAD_NC(GPP_D5, NONE),
/* D6: Clock Request 1 PCH M.2 SSD */
-// PAD_NC(GPP_D6, NONE),
+ PAD_NC(GPP_D6, NONE),
/* D7: Clock Request 2 Wireless LAN */
-// PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8: Clock Request 3 LAN */
-// PAD_NC(GPP_D8, NONE),
+ PAD_NC(GPP_D8, NONE),
/* D9: GSPI 2 FPS */
PAD_NC(GPP_D9, NONE),
/* D10: GSPI 2 Clock */
@@ -374,7 +374,7 @@ const struct pad_config gpio_table[] = {
/* H18: CPI C10 Gate */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19: Clock Request 4 CPU M.2 SSD */
-// PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
/* H20: Not Connected */
PAD_NC(GPP_H20, NONE),
/* H21: Not Connected */
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
index 085dbfcabb..e7e1c6a3d2 100644
--- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
+++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c
@@ -44,5 +44,4 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
}
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
- mupd->FspmConfig.GpioOverride = 0;
};