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The mainboard siemens/mc_apl1 uses an external I/O port for console
output. For this reason we need to activate the 8250 LPC UART.
Change-Id: Ib5616a116aec6135191bdce95f9f9566ce13d6f1
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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If there is an external 8250 UART, one needs to enable the appropriate
address ranges before console_init() is called so that the init sequence
can reach the external UART.
Furthermore FSPM needs different settings for an external UART port. For
this, the function fill_console_params() has to be adapted.
Change-Id: I62c7d0b54edd18acf793849aef352afbcaeb68b9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This device is no longer directly connected to the SOC so it
does not need to be enabled in coreboot.
BUG=b:35648259
TEST=build and boot on Eve
Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19728
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The touchpad frequency was still slightly above 400kHz so tweak
the timing values manually to get under the spec limit.
BUG=b:35583133
TEST=verified the bus frequency with a scope to be < 400kHz
Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19727
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. Add a separate devicetree file for soraka variant and add H1 node.
2. Enable H1 TPM for soraka.
BUG=b:36265511
Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19519
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
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TPM is on I2C bus 1. Fix that.
BUG=b:36265511
Change-Id: I7fb696ca7281a0c099dd325d794dd4551cf20a53
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19710
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that device detects SSD
Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
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PCR_BASE_ADRESS may be zero if SOC Kconfig didn't define the non zero
default value.
TEST=Remove the PCR_BASE_ADDRESS config in Apollolake Kconfig file and
build.
BUG=None
Change-Id: I396aa1a3e89507c90e17229a986de5d2c0887c9c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.
Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Program C3/C7/C10 interrupt response time for all cores.
Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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disable_turbo function can be used to disable turbo mode
on each processor by settings MSR 0x1A0 bit 38.
This option will help to perform some quick test
without enabling turbo mode.
Change-Id: If3e387e16e9fa6f63cb0ffff6ab2759b447e7c5c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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They do 64bit accesses, and gcc does the necessary fix ups to handle
32bit values as zero-padded 64bit values.
clang, however, isn't happy with it.
Change-Id: I9c8b9fe3a1adc521e393c2e2a0216f7f425a2a3e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/19661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I5fcc83328441ccfb34ee63a7406d26e393633c21
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/19685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I0eff29b74d7df331dcbf2c25799eaae4911e54fc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ic2df7fb1e4a3d3c52561b949c4b359ea59824387
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19664
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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And don't link it. It's for ROMCC.
To make code happy that uses the ROMCC interface read_option(),
read_option_lowlevel() is ported to mc146818rtc.c along with
a message to use get_option() instead.
Change-Id: I54ea08de034766c8140b320075d36d5e811582fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Start-point is Gigabyte GA-G41M-ES2L.
This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.
Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).
Tested but fails:
* DDR3 (not implemented in coreboot).
Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.
Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not
supported). Should fix coverity issue 1375009. Remove a redundant
line that uses the variable `gfxsize` out of its scope and move the
variable declaration. Make sure the variable is always initialized,
drop unneeded error-handling for `get_option()` and sanitize the
read value instead.
Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19680
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This board features a PATA port.
TESTED PATA drive works in SeaBIOS and OS.
Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.
For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down
on mainboard, change internal pull up to none.
BUG=b:37998248
TEST=Boot up into OS and enter s0ix.
Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19577
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add macro to config GPIO IOSTERM bits.
BUG=b:37998248
Change-Id: I178f6d3055d4620cb3c895245c40f324383873ad
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19576
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.
* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*
TEST=Build and run on Galileo Gen2
Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Delay for a while after the switch operations to let the card recover.
TEST=Build and run on Galileo Gen2
Change-Id: I938e227a142e43ed6afda80d56af90df0bae1b05
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Probe RAM to find its size instead of hardcoding 1024M.
Also properly export it to memory map.
Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I99d0bd7d9b897a10edce35316e095e0223522c54
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: clang
Reviewed-on: https://review.coreboot.org/19656
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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from FSP release V030_61
Change-Id: I5ecba08de851ee2e362f9ac31e1fa8bf3dfceebb
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19605
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`cardF[n]` should indicate whether the DIMM in channel n is of
raw card type F. However, `cardF[1]` was initialised with the
value meant for `cardF[0]`. This patch results in the correct
initialisation of `cardF`.
Tested on a Lenovo T400 containing two DIMMs: one of raw card
type F and the other of raw card type B. Before the patch, the
system would not boot. After the patch, the system boots with all
of the memory functional.
Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This results in raminit_receive_enable_calibration.c producing
no errors or warnings with checkpatch.
The issues fixed are:
ERROR: that open brace { should be on the previous line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Tested by compiling after making the changes.
Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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APU2 exposes a LPC header which can be used
in conjunction with a LPC TPM module.
Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/18523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/18522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove overrides that set platform defaults or insane values.
Change-Id: I11d1c7155bf1c7f9298f60638a6c2f3b128f3fe8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
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This mainboard contains an external RTC chip RX6110 SA. Enable usage of
this chip and set some initialization values to device tree.
Change-Id: I5aceb4401f0bb059ef893dfe7d157716c82e4a76
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This driver enables the usage of the external RTC chip RX6110 SA
(http://www5.epsondevice.com/en/products/i2c/rx6110sab.html) which is
connected to the I2C bus. The I2C address of this device is fixed. One
can change parameters in the device tree so that the used setup can be
adapted to match the configuration of the device on the mainboard.
Change-Id: I1290a10c2d5ad76a317c99c8b92a013309a605d6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The EC doesn't support it.
Change-Id: Id2964002406a5fcf992f0ffc3627e3f66a2bb13f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The thinkpad-acpi driver uses the UCMS (CMOS) ACPI method to control the
ThinkLight from the Operating System. This patch adds partial support for
that method, enough to enable or disable the ThinkLight:
echo on >/proc/acpi/ibm/light
echo off >/proc/acpi/ibm/light
With the original BIOS the UCMS method exposes a wide range of values
through a generic /proc/acpi/ibm/cmos interface. With the changes suggested
in this patch that interface is also exposed but only accepts the commands
to enable or disable the ThinkLight; all other commands are ignored.
This change would potentially benefit all currently supported Thinkpad
models, I only have an X201 available for tests though.
Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066
Signed-off-by: Stefan Ott <stefan@ott.net>
Reviewed-on: https://review.coreboot.org/19644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I05f768c67542770e65279a562c05225b84edca40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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- set GPIO_183 to high level for enabling the power of SD card
- delete all GPIOs for JTAG interface because they lead to problems with
Lauterbach debug hardware
Change-Id: I24bfff479601933c43e3dcbfa3baa49510831703
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations’ Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Promote DRVR_CAP_8BIT from controller specific to controller independent
TEST=Build and run on Galileo Gen2
Change-Id: I51e4c990d3941a9f31915a5703095f92309760f1
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Fix bug detected by coverity to handle the zero capacity case. Specific
changes:
* Reduce loop count by one to handle zero capacity case
* Use structure instead of dual arrays
* Move structures into display_capacity routine
Coverity Issues:
* 1374931
* 1374932
* 1374933
* 1374934
TEST=Build and run on Galileo Gen2
Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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s230u seems only have two sata ports: one for the 2.5in hdd and one for
msata. map 0x11 (port 0 & 4) enables hdd but not msata, and map 0x5
(port 0 & 2) enables both.
Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Remove unused field in generic SD/MMC controller data structure.
TEST=Build and run on Galileo Gen2
Change-Id: I7169dca07509a6f2513d62b593742daf764010b2
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Is only present on the P45 subtype of chipset.
Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Tested against a lenovo-manufactured tpm 1.2 module:
a /dev/tpm0 visible inside GNU/Linux, but there is no menu items in
SeaBIOS' interface, which seems a common issue of SeaBIOS on ivb boards.
Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19521
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This replaces the custom environment controller handling in the it8728
driver with the common library.
It also updates the two existing boards with hwm register settings in
their devicetree config so they better match their vendor BIOS fan
control settings.
Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/19293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I53ed687dc49524e001889f091825b2cc530546a3
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I92c654d59f1642bcd7c95de80dcc641bf816b542
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add PCI configuration code support for intel/common/
block/uart module.
Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=None
TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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According to "Intel ® 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.
Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18515
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This disables VGA cycles on IGD when an external VGA device is
found. This allows PCI or PCIe devices to be the 'main' VGA device if
found, while the IGD is still available.
TESTED on ga-g41m-es2l: SeaBIOS shows payload on external GPU while
linux (4.10) can use both as a framebuffer simultaneously without any
extra configuration.
Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) dropped mtrr_check while re-organizing
code. Add the check back after MTRR setup is performed.
BUG=b:36656098
TEST=Verified that MTRR check is done after setup on poppy.
Change-Id: I440405c58c470ffa338be386d84870635530a031
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Configure the SD controller to handle the SD card slot.
* Galileo supports a removable SD card slot.
* Set SD card initialization frequency to 100 MHz.
* Set default removable delays.
* Build SD/MMC components by default
TEST=Build and run on Galileo Gen2
Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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With change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) to perform CPU MP init before FSP-S init, MTRR
programming was moved to be performed after CPU init is done. However,
in order to allow callbacks after MP init, PARALLEL_MP_AP_WORK needs
to be enabled. Since this option was not selected, MTRR programming
always failed in ramstage for Skylake / Kaby Lake mainboards.
BUG=b:36656098
TEST=Verified 2500+ cycles of suspend resume on poppy.
Change-Id: I22a8f6ac90ba35075ff97dd57bab66c129f3e771
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The SD/MMC test support consists of:
* Add Kconfig value to enable the SD/MMC test support.
* Add Kconfig value to enable the logging support.
* Add SD/MMC controller init code and read block 0 from each partition.
* Add logging code to snapshot the transactions with the SD/MMC device.
* Add eMMC driver for ramstage to call test code.
* Add romstage code to call test code.
* Add bootblock code to call test code.
TEST=Build and run on Galileo Gen2
Change-Id: I72785f0dcd466c05c1385cef166731219b583551
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add below code support under intel/common/block:
* SMBus read/write byte APIs
* Common SMBus initialization code
Change-Id: I936143a334c31937d557c6828e5876d35b133567
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.
Intel ® 4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.
Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The southbridge_clear_smi_status() is not used. Remove it.
Change-Id: Ia358c6aca93630753ac4b59b6fc86b1ea1eb9ca6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The southbridge_trigger_smi() and southbridge_clear_smi_status()
functions are unused. Remove them.
Change-Id: I86994191a63cbf515bc330433ef7c3f79a39936e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Enable SAR and DSAR for reef.
BUG=b:37612675
TEST=`emerge-reef coreboot`
Change-Id: Ie0a59f8fcc9fb104328ee6d276ecab4193ec8eb8
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://review.coreboot.org/19579
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide a failing get_wifi_sar_limits() to allow SAR Kconfig
options to be selected without relying on CHROMEOS which currently
has the only code to provide SAR data.
Change-Id: I1288871769014f4c4168da00952a1c563015de33
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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The device ids changed names between patches. Fix them to
not break the build any more.
Change-Id: I1d74d95ec6b516c4d8354a714b2b302557743fe0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19600
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: coreboot org <coreboot.org@gmail.com>
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Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Only cs 0 is considered valid.
Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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tis_close() must be called after tis_open() otherwise the locked
locality isn't released and the sessions hangs.
Tested=PC Engines APU2
Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/19535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
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This patch performs apollolake specific XDCI
controller initialization.
Change-Id: I4649bffe1bb90d7df6a72b5334793bf8f0fdbaeb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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XDCI MMIO offsets definitions are not alike between
various SoCs hence provided "soc_xdci_init" function
to implement SoC specific initialization.
Change-Id: I9cbc686a00c26b92be2847b6bd6c2e5aa5a690f7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Change-Id: Iccb6b6c8c002701d17444fcf62ec11315e5aeed9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Change-Id: I33d92a173055ea18b8675c720f01dd5bc77befa3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Change-Id: Ic92d17b2819c39997bbffff8293c937f3f73776b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The AP sends the Cr50 a request to enable the new firmware image. If
the new Cr50 image was found and enabled, the AP expects the Cr50 to
reset the device in 1 second.
While waiting for the Cr50 to reset, the AP logs a newly defined event
and optionally shuts down the system. By default the x86 systems power
off as shutting those systems down is not board specific.
BRANCH=gru,reef
BUG=b:35580805
TEST=built a reef image, observed that in case cr50 image is updated,
after the next reboot the AP stops booting before loading depthcharge,
reports upcoming reset and waits for it.
Once the system is booted after that, the new event can be found
in the log:
localhost ~ # mosys eventlog list
...
7 | 2017-03-23 18:42:12 | Chrome OS Developer Mode
8 | 2017-03-23 18:42:13 | Unknown | 0xac
9 | 2017-03-23 18:42:21 | System boot | 46
...
Change-Id: I45fd6058c03f32ff8edccd56ca2aa5359d9b21b1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Add host of PCI device Ids for IPs in Intel platforms.
Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Provide a common function to issue reboot commands to the EC.
Expose that function for external use and use it internal to
the module.
BUG=b:35580805
Change-Id: I1458bd7119b0df626a043ff3806c15ffb5446c9a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19573
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
|
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Use names instead of magic values.
No functional change.
Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Use defines instead of magic values.
No functional change.
Change-Id: Idc90f254d7713f96a6e8b0389e34d860f461d9d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Use register name instead of hex values.
No functional change.
Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Use register name instead of hex value.
No functional change.
Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This patch adds the eMMC as one of the thermal sensor under DPTF.
Also, updates few comments for better interpretation and mapping.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/19524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This reverts commit 39b633b26d6d4cf185fbbdd5a256d0665409bd5b.
Commit was accidentally pushed too early and broke the tree.
I'll repush the original.
Change-Id: Iaca6d43cc8fc0959565d5d151a330c0c7ba38309
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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TEST=Boot from scarlet, and mipi panel work
Change-Id: Id5f81867ea50f72cc0bc13074627134e0dc198ba
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The current implementation is incorrect and is
actually disabling the ports. Fixes that.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
SATA SSD.
Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19553
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Turn on device 1c.0 in order to enable devices
under it.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=Boot from NVMe
Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19533
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This is required to ensure that SCI is generated whenever a host event
is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs,
eSPI SCI is generated which results in kernel handler reading host
event from the EC and thus causes the wake pin to be de-asserted.
BUG=b:37223093
TEST=Verified that wake from mode change event works fine in suspend
mode and there is no interrupt storm for GPE SCI after resume.
Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jenny Tc <jenny.tc@intel.com>
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soc/i2c.h does not need to be included in this compilation unit.
Change-Id: Ife11642d2e69af7235c93fc54bba38853b046169
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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According to Yang York the FSP is responsible for switching the CPU into
high frequency mode (HFM). For an unknown reason this is not done for the
BSP on my platform though the APs are switched properly.
This code switches the CPU into HFM which makes sure that all cores are in
high frequency mode before payload is started.
It should not harm the operation even if FSP was successful in switching
to HFM.
Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove struct skylake_i2c_config from chip.h since it is not used
anymore.
Change-Id: Icde4b7af5b9c31020099c1a6372a6867827f61ae
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Currently native video init works on port HDMI1 (wired to the
on-board DVI-D socket) , HDMI3 (the on-board HDMI port), and the VGA
port, both text mode and fb mode.
Every ports works on GNU/Linux.
Tested against an IVB cpu (i7-3770T).
Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/19522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The checkreset() function checks if raminit previously
succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a
hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the
system BOOT_PATH_RESET path will be taken. This boot path can only
successfully initialize memory if the system was reset from a state
where raminit succeeded, which is not the case here.
This can be fixed by issuing a cold reset instead of a hot reset.
Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fetched from vendor DSDT.
Change-Id: Ib74408802e977d9caabcb815c9cbd06bd8dbe395
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kevin Keijzer <kevin@librepractice.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Remove the code that was enabling the keyboard backlight at boot
since this is not desired behavior for this device.
BUG=b:35581264
TEST=build and boot on Eve and ensure keyboard backlight does
not turn on when booting but can still be enabled in the OS.
Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied
to SUSACK# in the schematic and and is intented to be used in Deep Sx
so it should not be configured for GPIO mode.
BUG=b:35581264
TEST=build and boot on Eve platform, test that Deep S3 and Deep S5
are still functional. (this change should have no visible effect)
Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This changelist adds the 48Khz 2ch 16bit NHLT configuration for the
Maxim 98927 speaker amplifier codec.
BUG=b:35585307
TEST=manual testing to ensure speaker output is functional on Eve board
Change-Id: Ieda988b557ecefdace5f81b474a952af56e69315
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19548
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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