| Age | Commit message (Collapse) | Author |
|---|
|
Comments stating that this was mainboard-specific were very wrong.
Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Why use a Rube Goldberg machine to write and then read one register?
Change-Id: I282c12f162b5ae69c40729903c09ae81a14c9761
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Other platforms do this as well. It will ease refactoring on follow-ups.
Change-Id: I643982a58c6f5370c78acef93740f27df001a06d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
|
|
The "normalized" boot mode is only used in a single place, so there's no
need to use a variable. Also, reword the associated comment, which seems
to be unnecessarily vague: the hardcoded assumptions are inside the MRC.
Change-Id: I260d10f231f5de765d2675416d7047717d391d8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
|
|
The `chipset_type` parameter is ignored.
Change-Id: Ia3d217178cc9caabf232b3a59f505229cc03135f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
|
|
There's no need to repeat the same values over four variants.
Change-Id: Ifc4a9961fe9c87f15a6039e6e478682fab5b0bb7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
|
|
Files are identical for all southbridges, except bd82x6x. We will take
care of that in subsequent commits.
Change-Id: I38e5d440e188d26f8997bc22a956187b728487ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43157
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Files are identical between all three southbridges, and differ for PCH.
Change-Id: Ic6a926af675bda3db3a5795df9e8f490caf3ebf4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43156
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reduces the differences between ACPI for these three southbridges.
Change-Id: If49bad776ebc98cab439f8ea6942471520c476a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43155
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It does nothing special, so why have it in the first place?
Change-Id: I27aff0ed67e9c69ab78050d35b49f6e26924d31a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43174
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This was silently commenting out the line after it.
Change-Id: I2714090b8f99193ace420ad02e2d42b324349c9e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: Ibc0988c4c86f7ffef8692ff3cf3ebd92235156b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43168
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove some unneeded newlines, add some commas for consistency and
relocate comments to match the code.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: Ibf6904246ee47dffdb5fa2e24cc7a230f439c7e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43178
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use C-style comments, drop unneeded newlines, add missing commas for
consistency and relocate a comment to match the code.
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: I37fffb60944c35dfb5e0491bb023babfcf2c6a73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43177
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Ibb9b627de85eb09bdc977af55880366e4e49f3ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Use C-style comments, drop an unneeded newline, add missing commas for
consistency and relocate a comment to match the code.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I3f91d1b57eb5530c8adcf5f682e73747435f0d47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43172
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: I089f14dce6e3fdebcfdee126a2023ef028a01805
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Use C-style comments. Also drop some unnecessary newlines.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: Icd33a326cc7d9ead765e2b32e7dea237bd76fd4f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Make the APOB size & base generation the same as all the other command
line arguments to amdfwtool.
BUG=None
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id78383d87bc98dd2c859c75585266411c226f950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This was specifically needed for vboot with psp_verstage, but adding
it to always be built into bootblock if needed like memcpy & memset
makes sense.
TEST=Build & boot trembyle
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Finally enable psp_verstage for zork.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This isn't needed for psp_verstage, and causes build failures if
included.
BUG=b:158124527
TEST=Build & boot Trembyle with psp_verstage
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I63942ad896d205c327d65bb8083da817b972962b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42808
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Check for the workbuf in bootblock if psp_verstage is being used.
BUG=b:158124527
TEST=Build & boot Trembyle with psp_verstage
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42810
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We can't set the SMI or SCI flags in psp verstage, so skip them.
TEST=Build
BUG=b:154142138
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42765
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The timestamp functionality is not yet added for psp_verstage, so
temporarily remove it until that's completed. That work is being
tracked by bug 154142138.
BUG=b:154142138
TEST=Build & Boot psp_verstage on trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I020619e3615ce92dedbe868104d2bfd83cb7caa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The AMD firmware package created by amdfwtool contains pointers to the
various binaries and settings. When these are moved to the RW-A & RW-B
regions, the packages need to be recreated for the new addresses.
TEST=Build & boot trembyle. See that we're booting from the correct
region.
BUG=b:158124527
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
The AMD firmware package created by amdfwtool contains pointers to the
various binaries and settings. This means that we need different copies
of the package in each region.
This change allows for the different files in each of the 3 vboot
regions.
BUG=b:158124527
TEST=Build trembyle; see the correct versions of the files getting
built into the RW-A & RW-B regions.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45ff69dbc2266a67e05597bbe721fbf95cf41777
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This adds the psp_verstage userspace application and the location of
the shared memory area to the amdfw binary tables.
BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
|
|
This is the main code for building coreboot's verstage as a userspace
application to run on the PSP. It does a minimal setup of hardware,
then runs verstage_main. It uses hardware hashing to increase the speed
and will directly reboot into recovery mode if there are any failures.
BUG=b:158124527
TEST=Build & boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I45380e0c61e1bb7a94a96630e5867b7ffca0909c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42064
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
1. Enable HDA Pci device in devicetree
2. Enable I2C4 in devicetree and fill ACPI information
3. Pass correct IRQ GPIO for headset jack
BUG=None
BRANCH=None
TEST=Audio playback and recording works on Waddledee.
Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41765
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The smm_setup_structures() calls placed GNVS address into
register %ebx. Old code on i82801dx used these low memory
addresses.
Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42426
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
BIC uses LPCflash utility to flash FW, it uses LPC to send the
bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used
to send BIC image for in-band update support.
TEST=Use LPCflash utility to flash BIC FW on YV3 successfully.
[root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin
Update Bridge IC Firmware from LPC
Deltalake linux utility ver:1.01
build time: Feb 11 2020 14:30:55
Processing image file: Y3BRDL_D06.bin
.. of size 206968 (0x00032878) bytes
.. file will be padded to a 64-byte size
.. with DEBUG Enabled
Generating CRC-32 for file.
Done (0x4e3905a3).
iBytesRead (0x00007c00).
Discovering LPC boot loader.
Discovered @ 0x3f8.
Configuring LPC boot loader.
Configured @ 0x00000600.
Sending header block.
Sent.
Loading firmware into target.
Sending 31744 bytes ...............................
Sending 31744 bytes ...............................
Sending 31744 bytes ...............................
Sending 31744 bytes ...............................
Sending 31744 bytes ...............................
Sending 31744 bytes ...............................
Sending 16512 bytes .................
Load complete.
Update done!
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
BUG=b:155002684
TEST=build drawcia, and check touchscreen can work
Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Enable long mode in SMM handler.
x86_32 isn't affected by this change.
As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR (which enables long mode support) to previous value.
NOTE: This commit does NOT introduce a new security model. It uses the
same page tables as the remaining firmware does.
This can be a security risk if someone is able to manipulate the
page tables stored in ROM at runtime. USE FOR TESTING ONLY!
Tested on Qemu Q35.
Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43152
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The host bridge register definitions haven't changed from Sandy Bridge
to Haswell, according to the datasheets. However, coreboot's ACPI code
is not the same. Looks like Haswell values are wrong, so correct them.
Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
romstage
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value. By default it would start the timer and
trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.
Tested on OCP Delta Lake.
Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
|
In romstage get the config from BMC IPMI and update the IIO accordingly.
Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation
register values are expected.
Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
|
|
BUG=b:155002811
TEST=build drawcia, and check touchpad can work.
Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42922
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds a new variant called Pompom that is identical to Lazor
for now. Also reorder variants alphabetically while we're here.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I5a0f297413765bce8353d5a781f0f67446de4e7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also
update memory map HOB definition file accordingly.
The CPX-SP soc code is updated to direct FSP log to SOL.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The tlbimvaa operation (invalidate unified TLB by MVA, all address
space identifiers) is only available on armv7 processors that support
Multiprocessing Extensions. When used on processors that do not support
the extensions it causes an "undefined instruction" exception.
This patch changes the MMU table entry filling code to use the tlbimva
(invalidate unified TLB entry by MVA and address space identifier)
operation for invalidating TLB entries, which is supported on all armv7
processors.
As address space identifiers are not used in TLB entries in coreboot
(all entries are set as global), these two operations can safely be
used interchangeably. The ASID value supplied to the operation is not
checked for global TLB entries.
More information as well as the data formats for the tlbimvaa and
tlbimva operations are detailed in the "ARM Architecture Reference
Manual ARMv7-A" edition, issue "C.c" page B4-1747.
TEST: Booted Beaglebone Black (my current in progress port)
Change-Id: Ie7dfb4adab20dc7eecb1b20aa2ee6355215a1521
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
ec_fill_dptf_helpers() is used to generate all of the "helper" methods
that DPTF requires. A system with a Chrome EC is typically in charge
of fan PWM control as well as battery charging, so if DPTF needs to
manipulate those, then it requires Methods provided by the EC.
BUG=b:143539650
TEST=compiles
Change-Id: Ib30072d1d0748b31bcab240a0fd0e2f12d34aaa4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41894
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
A fairly common thing in ACPI is notifying a device when some kind of
device-specific event happens; this function simplifies writing this
pattern.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0f18db9cc836ec9249604452f03ed9b4c6478827
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42102
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Intel Dynamic Tuning Technology is the name of a PCI device on some
Intel SoCs. This minimal PCI driver is only used now for SSDT generation
on TGL devices.
Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When converting to override trees in commit c1dc2d5e68 (mb/lenovo/t60:
Switch to override tree), some device nodes were missed. These are
essential, as `chip` configuration data is always tied to device
nodes. The resulting `static.c` contained multiple copies of the
`chip` configuration structs, but the wrong ones were hooked up.
The therefore missing configuration of the clock gen led to general
instability, especially with SMP under Linux (probably due to the
attempt to enter lower C states on an idle core). Passing `maxcpus=1`
to the Linux kernel served as a workaround.
Change-Id: I6c26d633d1860cf9a5415994444e75ae1c2e59ad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43150
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change disables Thunderbolt PCIe root ports bus master before
handing over to payload in order to mitigate the threat from the
unauthorized external DMA. In this state, the PCIe root ports would
be considered as trusted to not forward any DMA transactions to
downstream endpoint devices.
BUG=b:141609884
TEST=Verified PCIe resource has been allocated properly and USB behind
Thunderbolt dock is enumerated successfully.
Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Specify how hexstrtobin.c processes the strings of odd length.
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Ie8cd8fb93d7dab08c5e7f28fc511b6381f5ad13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43089
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update GPIOs since Vilboz hardware design
follow schematic V3.2, so gpio.c is unnecessary.
BUG=b:157744136
BRANCH=NONE
TEST=flash the bios to vilboz DUT and test touchpad function
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I575f8b233b56185f3281ad7127bc274bda5ea801
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42986
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
At this moment, Vilboz board version is 1 and it
according to v3+ schematics, however WiFi power enable
is active high. This change sets
VARIANT_MIN_BOARD_ID_V3_SCHEMATICS for Vilboz as 1
and VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW as 2.
BUG=b:160547115
BRANCH=None
TEST=flash the bios to vilboz DUT and test WIFI module
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I9699bb839a801ab7d14c38b971ec28e3a322a997
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Two usb Type-C ports under the actual mux device. Each port has its own
ACPI device entry. These nodes are the ones that the USB Type-C
port/connector device will refer to in order to configure the mux.
TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP
board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42953
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Windows definition
There was a review comment for Chromium Linux ov2740 driver that
Windows driver already set the HID as INT3474 and suggested to have
the same value for Chrome.
The upstreamed Linux driver code has INT3474 as HID and this patch is
to set the same HID in ACPI configuration.
https://patchwork.kernel.org/patch/11540753/
BUG=b:160334865
BRANCH=none
TEST=User-facing camera should work with the driver which set the HID
as INT3474
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I10e98d32899f31d91c1cc7ddfa099af73d8aef37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43006
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Volteer world-facing camera has a privacy LED and it is supposed
to be turned on only when the camera is being used. But the LED
is always on and this is to fix the issue.
RCAM_SNR_PWR_EN (RearCAMera_SeNsoR_PoWeR_ENable) GPIO, which
controls the world-facing camera LED, was not in the power-up
and power-down sequence definitions and this caused the issue.
BUG=b:160341981
BRANCH=none
TEST=Build and boot volteer proto 2 board. Start a camera app
and check the world-facing camera LED is only turned on only when
the camera is working.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I564690baffddfdd0f998525992643aaf16ba4b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42985
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
\_SB.DPTF.IDSP adverties to the DPTF daemon which policies the
implementation supports. Added a new acpigen function to figure out
which policies are used, and fills out IDSP appropriately.
Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
DPTF has several options on how to control the fan (fine-grained speed
control, minimum speed change in percentage points, and whether or not
the DPTF device should notify the Fan if it detects low speed).
Individual TSRs can also set GTSH, which is the amount of hysteresis
inherent in the measurement, either from circuitry (if analog), or in
firmware (if digital).
BUG=b:143539650
TEST=compiles
Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change adds support for emitting the PPCC table, which describes
the ranges available as knobs for DPTF to tune. It can support min/max
power, min/max time window for averaging, and the minimum adjustment size
(granularity or step size) of each power limit. The current implementation
only supports PL1 and PL2.
BUG=b:143539650
TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change adds support for generating the _FPS table for the DPTF Fan
object. The table describes different levels of fan activity that may be
applied to the system in order to actively cool it. The information
includes fan speed at a (rough) percentage level, fan speed in RPM,
potential noise level in centibels, and power in mA.
BUG=b:143539650
TEST=compiles
Change-Id: I5591eb527f496d0c4c613352d2a87625d47d9273
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change generates the DPTF TCHG.PPSS table in the SSDT. This table
describes different charging rates which are available to use. DPTF
can pick different rates in order to passively cool (or not) the
system.
BUG=b:143539650
TEST=compiles
Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This patch adds support for DPTF Critical Policies, which are consist
of Method definitions only. They are `_CRT` and `_HOT`, which are
defined as temperature thresholds that, when exceeded, will execute a
graceful suspend or a graceful shutdown, respectively.
BUG=b:143539650
TEST=compiles
Change-Id: I711ecdcf17ae8f6e653f33069201da4515ace85e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This patch adds support for emitting the Thermal Relationship Table, as
well as _PSV Methods, which together form the basis for DPTF Passive
Policies.
BUG=b:143539650
TEST=compiles
Change-Id: I82e1c9022999b0a2a733aa6cd9c98a850e6f5408
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This change adds support for generating the different pieces of DPTF
Active Policies. This includes the Active Relationship Table, in
addition to _ACx methods.
BUG=b:143539650
TEST=compiles
Change-Id: Iea0ccbd96f88d0f3a8f2c77a7d0f3a284e5ee463
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
In this DPTF implementation, the participant device objects are written
into the DSDT with only minimal Names attached (_HID/_ADR, _STA, _UID,
PTYP, and _STR). All other Methods & Names will be written into the
SSDT. If a device is not used in any policy, then its _STA is set to
return 0 ("off").
BUG=b:143539650
TEST=Compiles.
Change-Id: Ief69a57adce9ee0b19056ce6a11ed8a5b51b3f87
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
For both Tiger Lake and Jasper Lake, add the DEVFN for Image Processing
Unit (IPU) to soc_acpi_name, which is set to return "IPU0".
Change-Id: Ib11be5be7fbaec688d8788945a3bcab3f8d834a1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42878
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a minimal PCI driver for Intel's IPU, this allows devices to be
added underneath it in the devicetree.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I531b293634a5d40112dc6af7b33fedb5e13f35e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42812
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add PCI IDs for Intel's Image Processing Unit (IPU) for TGL & JSL
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I71dc95a6692e82ca25b0252b4f0789ee059df89f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42811
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds support function to parse entries in the devicetree to
generate PowerResource entries for the MIPI camera.
Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41624
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds support function to add STA function which returns an
external variable.
Change-Id: I31755a76ee985ee6059289ae194537d531270761
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42245
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change updates mipi_camera driver to handle CIO2 device type.
Change-Id: I521740524bc1c4da3d8593f011a033542e4a872c
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42470
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change updates mipi_camera driver to add PLD section to SSDT.
Change-Id: If65b9cbabca95e9645d8e5023ce7fd78b0625d1e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42469
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change updates mipi_camera driver to add DSM section to SSDT.
Change-Id: Ic60e972b6aebad171a7b77fe0d99781693adfb20
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42468
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change updates mipi_camera driver to handle camera sensor.
Change-Id: I581c9bf9b87eac69e88ec11724c3b26ee5fa9431
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42467
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds support in mipi_camera driver to handle NVM and VCM
device types.
Change-Id: I24cb7f010d89bc8d14e0b4c8fe693ba6e9c68941
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42466
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change updates the mipi_camera driver to handle acpi_name based on
device_type, if acpi_name is not set in the devicetree and moves some of
the common code to separate methods.
Change-Id: I15979f345fb823df2560db269e902a1ea650b69e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
update telemetry value for SDLE test result.
BUG=b:152922299,b:152369472
TEST=emerge-zork coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42999
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on schematic and gpio table of terrador, generate gpio settings
and overridetree.cb for terrador.
BUG=b:156435028,b:151978872
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Verify that the image-terrador.bin is generated successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42302
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds memory parts used by variant terrador to
mem_list_variant.txt and generates DRAM IDs allocated to these parts.
Added memory
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E
BUG=b:159195585,b:152936481,b:156435028
TEST="emerge-volteer coreboot chromeos-bootimage", flash terrador and
verify terrador boots to kernel.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41995
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL:
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E
BUG=b:159195585,b:152936481,b:156435028
TEST=build.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Diffentiate Lazor and trogdor build configuration
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42730
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Instead of directly reading ABAR without any checking, do like i82801ix
and treat it as a resource. This prevents problems if ABAR is not set.
Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code
isn't even being tested. So, throw it into the bitbucket before it rots
any further. If anyone needs that code ever again, it's in git history.
Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Enable HotPlug for the PCIe root port that the SD express is on so the
OS can re-train the link without needing a reboot if it goes down
unexpectedly at runtime.
BUG=b:156879564
BRANCH=master
TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in
linux that it is identified as a HotPlug capable root port
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42897
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig.
Change-Id: I617f332b80c534997e06a91247d1be90a85573be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Even with previous platforms, these entries were not
utilised for raminit.
Change-Id: I9a9a1a292bad8c4c89cbacb826c80f4098cae00f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
A regression sneaked in with 18a8ba41cc (arch/x86: Remove RELOCATABLE_
RAMSTAGE). We want to call load_relocatable_ramstage() on x86, and
cbfs_prog_stage_load() on other architectures. But with the current
code the latter is also called on x86 if the former succeeded. Fix
that and also balance the if structure to make it more obvious.
TEST=qemu-system-x86_64 boots to payload again.
Change-Id: I5b1db5aac772b9b3a388a1a8ae490fa627334320
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43142
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
CB:43090 renamed con to conn to avoid issues when building on Windows.
CB:42905 introduced more uses of the old name.
Adapt the latter to comply with the former.
Change-Id: I723141add5452fc541f67cb8591793f2d64cc231
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43141
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
PS/2 keyboard and mouse devices are declared twice in the DSDT, once
in mainboard and once in southbridge. It would appear in Windows
Device Manager as two PS/2 keyboards and two PS/2 mouses, all with
resource conflicts. This change drops the declaration from mainboard.
The issue was discovered when this setup was copied for p8z77-m and
being boot tested.
Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41225
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As the booting the system can be delayed for a noticeable amount of
time, often 60 seconds is the default, this is not a debug message.
Chose log level BIOS_INFO.
Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
|
|
p3b-f suspend code is going to use it.
Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Bring DRB7 OpRegion and top-of-memory indicator inside NB device.
Use more concise ASL 2.0 syntax for TOM calculations.
Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Only two mainboard groups use this southbridge:
emulation/qemu-i440fx: Nothing creates or consumes this ACPI path.
asus/p2b: It only fills the (mostly static) PIIX4E PM/SMBus I/O
resources, which are being declared in DSDT.
It is not doing anything useful and causes ACPI errors in Linux
kernel[1][2], so it has to stop.
[1] https://review.coreboot.org/c/coreboot/+/38601
[2] https://review.coreboot.org/c/coreboot/+/38304
Change-Id: I770047610e02c08191613b57c989b3bc1d464684
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
We always have it, no need to support opting-out.
For PLATFORM_HAS_DRAM_CLEAR there is a dependency of ramstage
located inside CBMEM, which is only true with ARCH_X86.
Change-Id: I5cbf4063c69571db92de2d321c14d30c272e8098
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on schematic and gpio table of voxel, generate gpio settings
and overridetree.cb for voxel.
BUG=b:157879197,b:155062762
TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage
Verify that the image-voxel.bin is generated successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Currently, the telemetry settings are not for the pollock platform
and might causethe power and performance issue. so applied the Pollock
reference board settings to Dalboz to improve the performance,
and the values need to be updated after the SDLE test finished.
BUG=b:157961590,b:152922299
TEST=Build.
Change-Id: I0da5b81afaa5814c13ec0257dc0eb3471be94c29
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2228257
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Apply the default USB2 phy tuning parameter for Zork family
BUG=b:155132211
TEST=Build, verified the default value been applied on trembyle
and the USB2 device works well.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I1f00b04173796d70147e232bafa405487b0761e1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength.
BUG=b:156315391
TEST=Build, verified the tuning value been applied on Trembyle.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I3d31792d26729e0acb044282c5300886663dde51
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The USB-C SBU and HSL orientation configuration depends on the USB
daughterboard used on the system. This patch adds an additional
configuration for supporting passive USB daughterboards using "probe"
directives to select the appropriate configuration at runtime.
BUG=b:158673460
TEST=verified active USB DBs enumerate at USB3 speeds in linux
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
