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2023-12-18mb/google/rex/var/karis: Enable audio BT offloadTyler Wang
BUG=b:312099281 TEST=Build and boot to Karis. Verify the config from serial logs. w/o this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 0 [SPEW ] BT Interface = 1 ``` w/ this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 1 [SPEW ] BT Interface = 1 ``` Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-18soc/intel/mtl: Adaptively disable 3-strike error for QS siliconSubrata Banik
This patch provides a way to mask the 3-strike error on Intel Meteor Lake SoC platform across pre-prod and prod SoC. This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types. Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error. BUG=b:314883362 TEST=Disable the 3-strike on google/screebo with QS silicon. Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-18src/lib: Add memory/time saving special case for ramstage cachingPatrick Georgi
When caching the ramstage for suspend/resume, we copy the entire image as it resides in RAM. The last part of that, CONFIG_HEAP_SIZE bytes, is the heap that will be reinitialized when the ramstage is started again. As such, copying doesn't make sense and complicates HEAP_SIZE configuration (because it needs to fit the space-constrained cache location) and costs time and space. Therefore, skip the heap. Side notes: - When building with ASAN, program.ld indicates that it will allocate some more space after the heap. This is not a problem, we just copy an ASAN-sized copy of the heap. - Heap use is managed in src/lib/malloc with statically allocated variables. Because ramstage is cached before it's executed, these values will be reset to their compile-time default values, too. Change-Id: I6553dc8b758196f2476af2e692c0421d0fa2b98e Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79525 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-17vc/intel/raptorlake: Update header files from 4301_01 to 4435_00Kulkarni, Srinivas
Update header files for FSP for Raptor Lake platform to version 4435_00, previous version being 4301_01. FSPM: 1. Options changed for Ppr Enable 2. Add 'Ppr Run Once' and 'Post Package Repair' UPD's FSPS: 1. Add 'CpuPcieRpTestForceLtrOverride' UPD MemInfoHob: 1. Structure updated BUG=b:315234533 Kit: https://www.intel.com/content/www/us/en/secure/design/confidential/ software-kits/kit-details.html?kitId=793230 Cq-Depend: chrome-internal:6786881, chrome-internal:6787635 Cq-Depend: chrome-internal:6719974, chromium:5125983 Change-Id: I65b8a4b6c72f7ae3fff1ee6d073311d154cd6b69 Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-17nb,sb/amd/pi/*/pci_devs: drop unused BUS0 defineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ce8ac00c015e34375c6b3c70496c97e2fe455bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-17mb/google/nissa/var/anraggar: Disable SDCard controllerWeimin Wu
1. Anraggar doesn't support SDCard, so disable SDCard contorller. 2. Not disabling it will cause can't enter S0ix on first suspend. BUG=b:313585586 TEST=1. check lspci 2. can enter S0ix on first suspend Change-Id: Ie4747d9c5d6ae93d29ef78b629855e0dd320c4db Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-17mb/google/skyrim: Add and use APCB configuration dataMatt DeVillier
This file is identical to the copy currently found in the blobs repository; it is simply being relocated for consistency and since it does not need to be in an external repo. BUG=none TEST=build/boot skyrim Change-Id: I352f58e0d3965356f3282a2653c6c11b44853857 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-17mb/google/guybrush: Add and use APCB configuration dataMatt DeVillier
This file is identical to the copy currently found in the blobs repository; it is simply being relocated for consistency and since it does not need to be in an external repo. BUG=none TEST=build/boot guybrush Change-Id: Ice4cbaccca13e9c4ae246fdcde5c89aa2086f1e1 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-12-17mb/google/zork: Add and use APCB configuration dataMatt DeVillier
This file is identical to the copy currently found in the amd_blobs repository; it is simply being relocated since it is mainboard specific and does not need to be in an external repo. BUG=none TEST=build/boot morphius Change-Id: Ia78fcd065fbf4d5ba6ec4edc3f8f937badf66ecc Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79591 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-17mb/google/brox: Disable EC/PD SW SyncShelley Chen
For initial debugging, we want to disable SW syncing. Will re-enable in the future. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage run gbb_utility --get --flags <image> make sure that it returns 0xa39 Change-Id: I865e9585ab37d1328a0ff54c6343cdad2c02220c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79569 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Short <keithshort@chromium.org>
2023-12-16sio/nuvoton/npcd378: Fix ACPI errorsRiku Viitanen
In commit 0a0945c6a211 (sio/nuvoton/npcd378: Use acpi_device_path_join), some oversights were made. Instances of "strconcat(scope, ..." should be replaced with "..._join(dev->bus->dev, ..." instead of "..._join(dev, ...". On HP 8200 USDT, this fixes ACPI error like this on resume from S3: ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.LPCB.SIO0.L040.RMFG], AE_NOT_FOUND (20230628/psargs-330) ACPI Error: Aborting method \_GPE._L08 due to previous error (AE_NOT_FOUND) (20230628/psparse-529) ACPI Error: AE_NOT_FOUND, while evaluating GPE method [_L08] (20230628/evgpe-511) RMFG seems to be a typo of PMFG made in that same commit. Change-Id: Ifffa7ad72cfdb644c8b5147132a5fd56511ed33b Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-16mb/amd/onyx: rename to onyx_pocVarshit Pandya
Even though this mainboard is called 'Onyx', the openSIL implementation and the corresponding coreboot integration is only a proof of concept that isn't fully featured, has known limitations and bugs, and is not meant for or ready to being productized. Adding the proof of concept suffix to the name should point this out clearly enough so that no potential customer could infer that this might be a fully functional and supported implementation which it is not. Change-Id: I157a8fffdc2a8543465fe8d444ac87f3f417389f Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77896 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-16vc/amd/opensil: add _POC suffix to SOC_AMD_OPENSIL_GENOAFelix Held
The openSIL code for the Genoa SoC is only a proof of concept, so change the name of the Kconfig option to include this code in the build from SOC_AMD_OPENSIL_GENOA to SOC_AMD_OPENSIL_GENOA_POC to clarify that this is code that isn't intended or ready to be productized. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If91cdaa7c324426964bba2de2109b6c38482fab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79574 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-16soc/amd/genoa: rename to genoa_pocFelix Held
Even though this SoC is called 'Genoa', the openSIL implementation and the corresponding coreboot integration is only a proof of concept that isn't fully featured, has known limitations and bugs, and is not meant for or ready to being productized. Adding the proof of concept suffix to the name should point this out clearly enough so that no potential customer could infer that this might be a fully functional and supported implementation which it is not. Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-16mb/google/{rex,ovis}: Decrease EPP to 45% for MTL performance expectationSukumar Ghorai
The default EPP is set at 50%, which is deemed insufficiently aggressive for meeting the MTL performance expectations in balance_performance mode. # cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference balance_performance # iotools rdmsr 0 0x774 0x0000000080003f06 EPP=45% is giving the required performance in MTL. # iotools rdmsr 0 0x774 0x0000000073003d06 NOTE: Kernel changes are necessary to ensure that the EPP (Energy Performance Preference) configured in the BIOS is not overwritten: https://patchwork.kernel.org/patch/13461932 BUG=b:314275133 TEST=Build and boot. Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79386 Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-16mb/google/nissa/var/uldren: Reduce boot time for non-touchscreen skuDtrain Hsu
Non-touchscreen sku will set related GPIOs to NC. If touchscreen enabled in overridetree for non-touchscreen sku, the boot time will be 6-7s. Set touchscreen probed to TOUCHSCREEN_UNKNOWN for reduce boot time from 6-7s to under 1s. BUG=b:316434359 BRANCH=firmware-nissa-15217.B TEST=Boot time (cbmem -t) from 6,460,972 to 922,844 Change-Id: I016ce762f726b7624bd060284f74f0992cb129b6 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-12-16soc/amd/genoa/fch: add fch_init_acpi_portsFelix Held
Make sure that the APMC SMI command IO port is configured to what coreboot expects and enable the SMI generation for the APMC SMI command port. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4fc259dea125a16556a01b80a3d5e6fb476044a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79531 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15soc/amd/stoney/northbridge: Remove dead codeArthur Heymans
All the resource on the host bridge are fixed resources and therefore have the IORESOURCE_STORED flag set, so the body of this function which configures IO or MEM ranges is never reached. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1839f030a4a365e5bc1cdaa3cf37cdf9ca382ff8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79385 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15acpi: Add support for WDAT tableMarek Maslanka
This commit lays the groundwork for implementing the ACPI WDAT (Watchdog Action Table) table specification. The WDAT is a special ACPI table introduced by Microsoft that describes the watchdog for the OS. Platforms that need to implement the WDAT table must describe the hardware watchdog management operations as described in the specification. See “Links to ACPI-Related Documents” (http://uefi.org/acpi) under the heading “Watchdog Action Table”. BUG=b:314260167 TEST=Mock the acpi_soc_fill_wdat function for a specific platform/soc and enable ACPI_WDAT_WDT in the kconfig. Check if the build passes successfully. Change-Id: Ieb82d1f69b2b7fffacfd2928bc71f8ff10498074 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2023-12-15mb/google/brya: Enable FSP UPD LpDdrDqDqsReTrainingBora Guvendik
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:302465393 TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I301a6e43f2944ffbc63431393378ab8b23450032 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-15soc/intel/cmn/cpu: Introduce API to disable signaling 3-strike eventSubrata Banik
This patch introduces a new API to disable signaling the 3-strike event on Intel Meteor Lake C0 (QS) stepping and subsequent SoCs. This is necessary because the existing event handling mechanism is incompatible with the new hardware design. Disabling the 3-strike event registration prevents the 3-strike count from increasing, which addresses bug b:314883362. This issue can potentially lead to system instability. BUG=b:314883362 TEST=disabling the 3-strike event on a Google Screebo system with QS silicon. Change-Id: I15bd5a93da34d7f2a127c21c4cd8b5952926bccf Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79472 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15mb/google: Reduce DA7219 mic detect threshold to 200ohmTerry Cheong
The original DA7219 is designed to use a 500ohm mic detection threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be detected. Lower the threshold to 200ohm to match the new default value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets. BUG=b:314062160,b:308207450 Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-15rules.h: Clean up ENV_HAS_HEAP_SECTIONArthur Heymans
Commit ea2c1d3 "cpu/x86/smm: Remove heap" removed the ability to use heap in SMM, but the ENV_HAS_HEAP_SECTION macro was not updated appropriately. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5ae4a63a7bd1b27ae3e9c757aa8557f329aad0f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-12-15vc/amd: use 'openSIL' spelling in comments & help textFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I176182180f508a180726fca60064b16fad80e9d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-15soc/amd: drop fill_fadt_extended_pm_regsFelix Held
Call fill_fadt_extended_pm_io directly from the SoC's acpi_fill_fadt functions instead of calling fill_fadt_extended_pm_regs that only calls fill_fadt_extended_pm_io. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I442bc2801cf74c1d836d3b0d88f281bceb5122b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79529 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-15soc/amd/genoa: Hook up BERTArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ie21bf8d436de19c23ae2176bf8d061564cd5b9cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-15soc/amd/genoa: Hook up IVRS generationFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I0a6eaf43ab6da4bb4a0cc0bbefb5b75c206348f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-12-15soc/amd/genoa: configure FCH IRQ mappingFelix Held
Add the code to configure the FCH IRQ mapping registers and provide the IRQ name strings for each FCH IRQ mapping configuration register. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I282ae35ebc4d7754121ce4544b782e3cbe7e2256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-15mb/google/brya/var/dochi: Enable LpDdrDqDqsReTrainingMorris Hsu
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:302465393,b:315739133 TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1 Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-14lib: ramdetect: Add Kconfig PROBE_RAMNaresh Solanki
Previously ramdetect.c was compiled only for VENDOR_EMULATION. Hence add Kconfig option PROBE_RAM which allows board outside the scope of VENDOR_EMULATION to select and utilize probe_ram function to runtime detect usable RAM in emulation environment. PROBE_RAM is default selected if VENDOR_EMULATION is set so that existing boards under VENDOR_EMULATION scope are not affected. Other boards can explicitly select PROBE_RAM to use probe_ram. TEST=Build mb/arm/rdn2 with PROBE_RAM selected & make sure there is no any error. Also checked qemu-aarch64 build to make sure build is success. Change-Id: Id909ddaee6958cfa8a6c263a11f9a90d94710aa7 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-14mb/amd/onyx/mainboard: add FCH IRQ mapping tableFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab640551d6dd246884802ced948ff8c359d922a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79470 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14mb/google/rex/var/screebo: Change GPP_B14 from UP_20K to NONEKun Liu
Change GPP_B14 from UP_20K to NONE for compatible with DVT1 and DVT2 board BUG=b:272447747 TEST=enable usb OC2 function to ensure USBA work normal Change-Id: Ib7720980335660f423b3a74199ceedc113ec70df Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79431 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14mb/google/nissa/var/anraggar: Update DTT settings for thermal controlWeimin Wu
Update DTT settings based on the suggestion of the thermal. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I2296990062cadc05202e3d1ab90af04234bda885 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)Weimin Wu
1. Ref to SCH, LTE use USB3 Port3, enable it. 2. Explicitly define the use of USB3 Port1 & USB3 Port2. BUG=b:315061146 TEST=can pass PCIe Hardware Compliance Test Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Change code style for register usb2_portsWeimin Wu
Change code style to be compatible with Nissa's format: register "option" = "{ [0] = value /* comment */ ... }" to register "option[0]" = "value" /* comment */ BUG=none TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I60659bd44813173f9b984216473a0919c5f331b8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14soc/amd/genoa/domain: generate SSDT entries for domainsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iadc37f2724a9be43cad1f1934403ebabd5cca245 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-14soc/amd/genoa: Add basic ACPI supportFelix Held
- DSDT - MADT - SSDT CPUs Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0c86694ae83e9e6aa06a50a8a35bf2b24bc8ab65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76530 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14vendorcode/amd/opensil/genoa_poc: add opensil_fill_fadt_io_portsFelix Held
Add the opensil_fill_fadt_io_ports function to fill in the ACPI I/O ports in FADT that openSIL configured. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I154a162cc8e048cadab693c0755e96c71a62983c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76529 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14vc/intel/raptorlake: Updating the FSP v4301.01 headers to Standard pathKulkarni, Srinivas
Move the existing FSP 4301.01 headers for Raptor Lake out of subdirectory called 43101.01 to follow standard process. Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-13soc/amd/genoa/acpi: update soc.aslFelix Held
Add the missing parts in soc.asl. Compared to earlier versions of this, the includes related to S0i3 and DPTC were removed. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I89ecf469e44ca2a3b35c9fcf57c008ff29e7b9bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/79468 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13soc/amd/genoa/acpi/soc: add root bridges to DSDTFelix Held
Add the 4 root bridge devices using the ROOT_BRIDGE macro. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If405a90981e5c1fea51935c520800a245473317e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79467 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13mb/amd/onyx/dsdt: include acpi/dsdt_top.aslFelix Held
acpi/dsdt_top.asl provides some common functionality and needs to be included at the beginning of the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7b5ddce110b35ed65c6df6cc42995abe93a3ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79466 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13soc/amd/genoa/acpi: include globalnvs.asl in SoC codeFelix Held
Instead of including globalnvs.asl in the mainboard's dsdt.asl, include it in Genoa's soc.asl. This aligns Genoa with Cezanne and newer and also moves more SoC-common code to the SoC folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e3299a95e007188a4d9de824cfff8d25a778be Reviewed-on: https://review.coreboot.org/c/coreboot/+/79465 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13soc/amd/genoa: set up the non-FCH IOAPICsFelix Held
Apart from the IOAPIC in the FCH which is handled by amd_lpc_ops, there's one IOAPIC per PCI root which also needs to be initialized. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I38af5a194062e714827852e95f4e29b45311e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13soc/amd/genoa/domain: fix indentation in genoa_pci_domain_opsFelix Held
There's no need for the two additional spaces between the tabs and the '='. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6824e8c7ee870fc44c5efd70cc05677e9948a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79464 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13soc/amd/genoa/chip: add init & final functions and chip nameFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I00a567f417b1e22167923fc3193583138718dbbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/79463 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13soc/amd/genoa/include/amd_pci_int_defs: rename PIRQ index 0x60 and 0x61Felix Held
PIRQ_SCI is already defined as 0x10 and this also brings the definitions more in line with Phoenix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2ab954b379d2edd0167d7fb229557600cbc4e48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-13lib/jpeg: Replace decoder with Wuffs' implementationPatrick Georgi
To quote its repo[0]: Wuffs is a memory-safe programming language (and a standard library written in that language) for Wrangling Untrusted File Formats Safely. Wrangling includes parsing, decoding and encoding. It compiles its library, written in its own language, to a C/C++ source file that can then be used independently without needing support for the language. That library is now imported to src/vendorcode/wuffs/. This change modifies our linters to ignore that directory because it's supposed to contain the wuffs compiler's result verbatim. Nigel Tao provided an initial wrapper around wuffs' jpeg decoder that implements our JPEG API. I further changed it a bit regarding data placement, dropped stuff from our API that wasn't ever used, or isn't used anymore, and generally made it fit coreboot a bit better. Features are Nigel's, bugs are mine. This commit also adapts our jpeg fuzz test to work with the modified API. After limiting it to deal only with approximately screen sized inputs, it fuzzed for 25 hours CPU time without a single hang or crash. This is a notable improvement over running the test with our old decoder which crashes within a minute. Finally, I tried the new parser with a pretty-much-random JPEG file I got from the internet, and it just showed it (once the resolution matched), which is also a notable improvement over the old decoder which is very particular about the subset of JPEG it supports. In terms of code size, a QEmu build's ramstage increases from 128060 bytes decompressed (64121 bytes after LZMA) to 172304 bytes decompressed (82734 bytes after LZMA). [0] https://github.com/google/wuffs Change-Id: If8fa7da69da1ad412f27c2c5e882393c7739bc82 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Based-on-work-by: Nigel Tao <nigeltao@golang.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78271 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13drivers/uart/pl011.c Perform basic UART initNaresh Solanki
Configure UART baud rate, Line Control register as 8n1 with FIFO enable and enable UART TX and RX. Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-12-13drivers/ipmi to lib: Fix misspellings & capitalization issuesMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I926ec4c1c00339209ef656995031026935e52558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13mb/google/brox: Generate RAM ID for supported memory partIvy Jian
Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-023 WT:B 2 (0010) BUG=b:311450057,b:315913909 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-12soc/amd/genoa/chipset.cb: add missing non-transparent PCI bridgesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d5efa948e8bd993ca4b5af80f664db687b8a766 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12mb/amd/onyx/devicetree: enable more PCI devicesFelix Held
Early versions of CB:76519 had more devices enabled in the chipset devicetree which shouldn't necessarily be enabled in the chipset devicetree. Enable most of those in the Onyx mainboard's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieeb96755a007a5ca70e4c31df09325835bb8ef47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-12soc/amd/genoa/chipset.cb: disable IOMMU devices by defaultFelix Held
Disable the IOMMU PCI devices in the chipset devicetree. In order for the IOMMU devices on the Onyx mainboard still be enabled, enable them in the mainboard devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12soc/amd/genoa: Parse APOB for DRAM layoutFelix Held
Use the xPRF call to report holes in memory and report those regions as reserved. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5605499e39931e1a1592318310112666f8a0f144 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12vendorcode/amd/genoa: Parse APOB for DRAM layoutArthur Heymans
Use the xPRF call to report holes in memory to report those regions as reserved. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If89b08a31a9b9f8e7d2959d1bc45e91763fe565b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78922 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12mb/amd/onyx: Add MPIO configMartin Roth
Add the device and chip entries for the various PCIe ports and MPIO lane configuration. Below each PCIe bridge device with an external PCIe port on the mainboard, an MPIO chip is added that provides the corresponding MPIO configuration for this external PCIe port. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8563c5a07eb8fd8ff9dd4e7b63fc9a7d485b1316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78921 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12soc/amd/genoa: Add opensil MPIO chip filesArthur Heymans
Add the openSIL MPIO chip driver that allows specifying the MPIO lane configuration in the mainboard's devicetree instead of having this configuration in a separate port descriptor C file. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1d408a7eff22423612bc5eb9bfebaf0d86642829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76520 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12vendorcode/amd/opensil: Add SATA configurationArthur Heymans
For now, we'll use a hard-coded SATA controller configuration that should work in most cases instead of making everything configurable via devicetree settings. In the process of scrubbing opensil for public release SATA became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib37a081c0be4fdd2785e1dca70f376b967ce4462 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76518 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12mb/amd/onyx: Add USB configurationMartin Roth
Drive board specific USB configuration from the coreboot devicetree into the opensil input block. In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I62eefe1061446612168dd27e673a2742903456c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78920 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12vendorcode/amd/opensil: Add USB configurationMartin Roth
Drive board specific USB configuration from the coreboot devicetree into the opensil input block. In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic41f57f3208aebb3a8b42f70cf558de50fa4de24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78919 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12soc/amd/genoa/chip.h: drop unneeded xhci2_enableFelix Held
Genoa has no XHCI2 controller, so drop this devicetree option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b995bb1c0cf0032be25ab215333bc966427f7ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/79454 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12arch/arm64/armv8/Makefile.inc: Add clang -target for .ld CPPArthur Heymans
When preprocessing the linker script the target arch needs to be specified. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id18af3da93d2d06a2ebb83eddd03377c9026c8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/78443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-12-12mb/google/rex/var/screebo: Increase PL1 max value from 15W to 25WKun Liu
Adjust PL1 max value from 15W to 25W BUG=b:314263021 TEST=emerge-rex coreboot Change-Id: I4122a13d7e33c736299c1a759ec51f7a3b29340f Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79377 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-11ec/google/chromeec: Provide ec_sync wake optionMark Hasemeyer
The ACPI spec defines keywords for the GpioInt and Interrupt resources to specify whether a given pin is wake capable. Some boards are using the ec sync interrupt pin to wake the system so the CREC _CRS needs to be updated accordingly. Provide a new macro that allows a board to specify whether its ec sync pin is wake capable. BUG=b:243700486 TEST=Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined Change-Id: I483c801ff0fee4d3ce0a3b2fc220e0bd9356a612 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2023-12-11soc/amd/genoa/chipset.cb: add missing '_' in gpp_bridge_3_bFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22b9b6781f516b96724b67d1321dd71b98e0e0e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11soc/amd/genoa: Add USB configurationArthur Heymans
Drive board specific USB configuration from the coreboot devicetree into the opensil input block. Add USB OC pins to chipset.cb In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I506547a7abbb643d3e982e44a92f33b45cd739e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11soc/amd/genoa/chipset.cb: enable dummy functionsFelix Held
Enable the dummy function 0 that don't have an alias in the chipset devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I607245c587a544007fd714f64901cbb50014612f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-11mb/google/nissa/var/quandiso: Tune P-sensorRobert Chen
Update proximity sensor tuning value from dedede/kracko tuning. Remove GPIO override to use the configuration from nissa baseboard: - GPP_B5 ==> SOC_I2C_SUB_SDA - GPP_B6 ==> SOC_I2C_SUB_SCL BUG=b:310050220 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11soc/amd/common/data_fabric: pass PCI segment group to domain codeFelix Held
Return the PCI segment group number from data_fabric_get_pci_bus_numbers via pointer argument so that amd_pci_domain_scan_bus can handle the PCI segment group numbers once coreboot supports more than one PCI segment group. For now, just print an error and return if the buses are on a PCI segment group other than 0. TEST=Mandolin still boots Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia53cda0ba656201c2197d05bc0d4a8fbbe8ad5d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-11soc/intel/meteorlake: Add entries to eventLog on invocation of early SOLSubrata Banik
This patch records early signs of user activity during CSE firmware synchronization or MRC (re)training events in the event log (ELOG_TYPE_FW_EARLY_SOL). These can be used to ensure persistence across global reset (e.g. after CSE sync) so that they can be later retrieved in order to build things such as test automation ensuring that we went through the SOL path/display initialized. BUG=b:279173035 TEST=Verified on google/rex, event shows in eventlog after CSE sync and/or MRC. Scenario #1: While performing MRC update 1 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2023-11-08 | Memory Cache Update | Normal | Success 3 | 2023-11-08 | System boot | 9 4 | 2023-11-08 | ACPI Wake | S5 Scenario #2: While performing CSE update/downgrade 11 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown 12 | 2023-11-08 | System boot | 13 Scenario #2: While performing both MRC and CSE upgrade 16 | 2023-11-08 | Early Sign of Life | MRC Early SOL Screen Shown 17 | 2023-11-08 | Early Sign of Life | CSE Sync Early SOL Screen Shown 18 | 2023-11-08 | Memory Cache Update | Normal | Success 19 | 2023-11-08 | System boot | 16 20 | 2023-11-08 | ACPI Wake | S5 Change-Id: Idfa6f216194fd311bb1a57dd7c86fe7446a3597c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78983 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-11soc/intel/mtl: Display Sign-of-Life message using FSP-MJeremy Compostella
Meteor Lake Firmware Support Package (FSP-M) for ChromeOS includes an pre-memory graphics driver which can be leveraged to display a text message thanks to the following FSP-M UPD (Updateable Product Data): - VgaInitControl (bitfield): Bit 0: Turn on graphics, setup VGA text mode and display `VgaMessage' text centered on the screen. Bit 1: Clear text and tear down VGA text mode and graphics before returning from FSP-M. - VbtPtr (address): Pointer to the VBT (Video BIOS Tables) binary. - VbtSize (unsigned int): Size of the VBT binary. - LidStatus (boolean): Due to limited resources at early boot stages, the text message is displayed on a single monitor. The lid status helps decide which display is the most appropriate. 0: Lid is closed: show the text message on the external display if available, do not display anything otherwise. 1: Lid is open: show the message on the internal display if available, use an external display if available otherwise. - VgaMessage (string): Text message to display. If the `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' flag is set, coreboot configures the UPDs above to display a text message during memory training and CSME update. The text message can be configured via the locale text mechanism using the `memory_training_desc' name. The `SOC_INTEL_METEORLAKE_SIGN_OF_LIFE' selects the LZ4 compression algorithm for VBT because LZMA decompression is not available in romstage by default and adding LZMA support increases the romstage binary size more than the VBT binary is reduced. BUG=b:279173035 TEST=Text message is displayed during memory training on a rex board Change-Id: I8e7772582b1895fa8e38780932346683be998558 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78244 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11soc/intel/cse: Add API to check if CSE Firmware update is requiredAnil Kumar
This patch adds a function to check if a CSE FW update is required during this boot. The function is expected to be used during use cases like Pre-Memory Sign of Life text display to inform user of a CSE Firmware update. Bug=279173035 TEST=build and boot on google/rex board. Call the function in romstage and confirm it returns True during CSE FW update and False otherwise Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: If5fae95786d28d586566881bc4436812754636ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/78243 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-11soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDsKilari Raasi
By default MarginLimitCheck and RMC UPDs are enabled in FSP which enables fast and cold boot retraining causing the boot time increase. So, disabling the same UPDs to fix it. Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11vc/intel/fsp/mtl: Update header files from 3323_86 to 3424_88Kilari Raasi
Update header files for FSP for Meteor Lake platform to version 3424_88, previous version being 3323_86. FSPM: 1. Add `MarginLimitCheck` UPD 2. Add pre-memory graphics UPDs i.e `LidStatus`, `VgaInitControl`,`VbtPtr`,`VbtSize`,`VgaMessage` 3. Address offset changes FSPS: 1. Add `Usb4CmMode` UPD 2. Address offset changes BUG=b:310108425 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I3f71cd739a607318fda06fa50d4a379d64857458 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78997 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-09arch/riscv/payload: Remove old RISC-V CSR namesLennart Eichhorn
LLVM/clang 17 removed support for CSR names that are no longer included in the RISC-V ISA Manual Privileged Specification since version 1.12. Related LLVM commit: https://reviews.llvm.org/D149278 Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132 Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-08vendorcode/amd/opensil: Set up resource manager input blockArthur Heymans
Tell the resource manager in openSIL to distribute the available IO and MMIO ranges across the different PCI root bridges. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0985712bc4e87b4068dea22bde1dfa371a6c47bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-08Makefile: Make vboot_fw.a a .PHONY targetJulius Werner
vboot_fw.a is built via a sub-invocation of make, but make is not able to track dependencies between different invocations. That means the toplevel make assumes that the vboot_fw.a target depends only on the dependencies explicitly listed in coreboot's Makefile (only config.h in this case), and thus assumes that if config.h didn't change it does not need to rebuild the library. This breaks incremental builds when files inside the vboot repository change. This patch marks the target as .PHONY so that it will always be rebuilt. The vboot Makefile's own dependency tracking will then ensure that on an incremental build we only rebuild the vboot sources that actually changed, so if nothing changed this will just add a simple and quick $(AR) call. Change-Id: I8bdd4e1589124914ba1e877e04b40ee709ea4140 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79375 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08Revert "nipperkin: Fix WLAN to GEN2 speed" & "Disable PSPP for WLAN"Zheng Bao
Updated Linux FW works with PCI gen3 speed and PSPP. This reverts commit 05c9a850fd21 ("mb/google/nipperkin: Fix WLAN to GEN2 speed") https://review.coreboot.org/c/coreboot/+/63593 and commit 76fddd963925 ("mb/google/nipperkin: Disable PSPP for WLAN") https://review.coreboot.org/c/coreboot/+/63722 The changes are overlapped and are reverted together. BUG=b:240426142 & b:228830362 The system is able to ran over 2500 cycles on Nipperkin with command suspend_stress_test -c 10000 --wake_min 10 --suspend_min 10 \ --nofw_errors_fatal The whole variant_update_dxio_descriptors is empty and is pushed back to weak function. Change-Id: Id207076542edc8ea0cabc6e02e29856c2b6803c7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-12-08acpi.c: Fix generating pointer to cb_tables located >4GArthur Heymans
Use the generic resource_consumer method which works for memory both above and below 4G. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1bc553b18d08cee502b765166227810f8e619631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76181 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-12-08mb/google/rex/var/screebo: set audio GPIO pins based on fw_configTerry Cheong
Enable BT offload when I2S option is selected for screebo. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/screebo. Fixes: https://review.coreboot.org/c/coreboot/+/77755 Change-Id: I7ebe8e28d35428ce2fb8129dc145fec9ac60f9da Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79378 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08mb/google/nissa/var/anraggar: Fix unrecogniz Type-C USB disk on depthchargeWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged, keep mainboard C port to conn0. BUG=b:312998945 TEST=can boot from external Type-c USB disk Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-08mb/google/brox: Update configuration for USB portsIvy Jian
Update brox devicetree based on the latest schematics. - Configure typeC to EC mux ports settings. - Configure USB2/USB3 ports settings. - Configure TCSS ports settings. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79391 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-07acpi: add missing device/device.h includeFelix Held
The device/device.h provides the definition for struct device used in those files, so include this header file to make sure that it's not only included indirectly via some other header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ff7cdbf0f53ada92adb53cf268e5feee9df4629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-06soc/amd/common: Move PCIe CLKREQ programming under fspMatt DeVillier
CLKREQ programming as currently implemented is completely dependent on FSP DXIO descriptors, so move under common/fsp/pci and rename the Kconfig to reflect the move. TEST=build google/{guybrush, skyrim, myst} Change-Id: I87b53d092ddc367b134c25949f9da7670a6a1d88 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-12-06vendorcode/amd/opensil: Add initial setup and API callsArthur Heymans
- First a console is set up for opensil. - After that a region in CBMEM is reserved and passed to opensil which will use it as a buffer for input/output information. - Finally opensil is called and the return value handled. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4833a5a86034a13e6be102a6b68c3bb54108bc9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-12-06mb/google/brox: Generate RAM IDs for two modulesIvy Jian
Add the support LP5 RAM parts for brox: 1. HYNIX LPDDR5 6400 2GB H9JCNNNBK3MLYR-N6E 2. MICRON LPDDR5 6400 4GB MT62F1G32D4DR-031 WT:B DRAM Part Name ID to assign H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:311450057 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Ib17f26a310435e37088191594863a645aa751440 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79392 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-12-06sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetreeFelix Held
Since the EHCI controllers in the PCH are always on the same device functions, the device operations can be statically assigned in the devicetree and there's no need to bind the EHCI device operations to the PCI devices during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I92ecc3607216fb2f31639db9628898c9ce81770d Reviewed-on: https://review.coreboot.org/c/coreboot/+/79171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-06sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetreeFelix Held
Since the XHCI controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the XHCI device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79170 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-12-06sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetreeFelix Held
Since the PCI bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the PCI bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79169 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetreeFelix Held
Since the SMBus controller in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the SMBus device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79168 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06commonlib/bsd: Use tabs instead of whitespacesVarshit Pandya
Change-Id: I05e7ba10e499ea1e824bdd6c87df05fc5a0864f8 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79400 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridgeFelix Held
Function 0 of the device that has the bridges to other buses is a dummy function that can be left enabled to not have to shuffle around the device function numbers when the first PCI bridge on that device isn't enabled. That dummy device function is however not a PCI host bridge, so change the comment from 'Dummy Host Bridge' to 'Dummy device function'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I6069205bd2e1cb0f75025e9f330afc50462e742a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79397 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06soc/amd/*/chipset.cb: don't call dummy device functions host bridgesFelix Held
Function 0 of the devices that have the bridges to other buses are dummy functions that can be left enabled to not have to shuffle around the device function numbers when the first PCI bridge on those devices isn't enabled. Those dummy device functions are however not PCI host bridges, so change the comments from 'Dummy Host Bridge' to 'Dummy device function'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ibddfdf558d84bc44434d718b86f41bd06044b22a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-06mb/google/rex/variants/deku: Enable CNVi PCI deviceEran Mitrani
BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I41a64252f08304ffc66fd782e54720252064ca49 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-06soc/amd/genoa/Kconfig: add CONSOLE_UART_BASE_ADDRESS defaultsFelix Held
Add defaults for the CONSOLE_UART_BASE_ADDRESS Kconfig symbol so that the SeaBIOS payload will know where the MMIO address of the UART is to build successfully without any additional user input during the build. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia05c3531cdbf3fd3e2e5f81b9d652f9dfef2111a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79395 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-06acpi/acpi_gic: Add GIC ITS subtableNaresh Solanki
Add support for generating GIC subtable ITS (Interrupt Translator Service). Change-Id: I1bcb3ad24de64cbba8aeef7ba7254d3157e0dc43 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-06acpi: Add IO Remapping Table structuresNaresh Solanki
Input Output Remapping Table (IORT) represents the IO topology of an Arm based system. Document number: ARM DEN 0049E.e, Sep 2022 Change-Id: I4e8e3323caa714a56882939914cac510bf95d30b Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-12-05acpi/acpi: make sure that table_ptr is non-NULL in acpidump_printFelix Held
While acpidump_print shouldn't be called with a NULL pointer as table_ptr argument, better add a check to not end up dereferencing the NULL pointer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic3cc103c8a47fb8c2fe4262236ea47013af27c4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/79393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-12-05sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetreeFelix Held
Since the LPC bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the LPC bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I366226be4aba75b98e45e4832bfe129fac14dbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/79167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 13:46:48 +0000