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PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced.
Just change the default value to 'y'.
Change-Id: Ie4248700f5ab5168bff551b740d347713273763c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking
support) to other client platforms. The SMRR MSRs are core-scoped on
Skylake and Ice Lake, at least. Older platforms do not support SMRR
locking, but now there's seven copies of the same file in the tree. A
follow-up will deduplicate smmrelocate.c files into common CPU code.
I cannot test Jasper Lake nor Elkhart Lake, but they should still work.
As per documentation I do not have access to, Elkhart Lake seems to
support SMRR locking. However, Jasper Lake documentation is unclear.
Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR
MSRs have the same value on all cores/threads (i7-8565U supports HT).
Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Pineview does not support PEG.
Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is a cosmetic change.
Make the formatting consistent with the rest of the tree.
Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Booted fine on the first try. Most things work properly, but I haven't
tested them thoroughly. Native raminit chokes with a DIMM in the second
slot, but the first slot works properly.
Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Returning an error on a failure to measure makes the system not
bootable.
Change-Id: Ifd20e543d3b30de045c0656eccdcc494c2fb10ce
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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There is going to be an upcoming board version for Drawlat/man and
Drawcia. Hence apply the override GPIO table without pad termination for
board versions 6 or 8 alone.
BUG=None
BRANCH=dedede
TEST=Build and boot to OS in Drawcia.
Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
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These files were automatically generated by the lpddr4 version of
gen_part_id.go.
BUG=b:178715165
TEST=Build
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3797ba6d52248961418000614a4f7885182521a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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These SPDs were generated by the lpddr4 version of gen_spd.go from the
global_lp4x_mem_parts.json.txt file.
BUG=b:178715165
TEST=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Looks like I forgot about trogdor-rev1 in CB:51004. Unlike rev0 (other
special case) or rev2 (works like CoachZ/Homestar), rev1 used the same
pin as Lazor and Pompom for EN_PP3300_DX_EDP. Apparently there are still
some people using these, so add in another special case for that.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7093aa63778d69fde240af3b0c62b97ac99c28dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51196
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The legacy DMA is not used by linux. This change frees up those IO
ports.
When FSP-S runs, it re-enables the legacy DMA IO region, so we need to
disable it again.
BOOTBLOCK: PMx00: 0xe3060bf3
ROMSTAGE - Before FSP: PMx00: 0xe3060bf3
ROMSTAGE - After FSP: PMx00: 0xe3060bf7
BUG=b:180949454
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51076
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Most devices are now disabled by default in the chipset. Enable the
iGPU and two XHCI controllers that are required to boot the board.
BUG=b:180528708
TEST=To be tested
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I54a4547217fb8e9f67fc0c8e1e36e96dfaae331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51095
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:180523962
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:180528708
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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1) Both SAR sensors had a UID of `2`, making them indistinguishable
2) No `device` underneath max98357a `chip`
Change-Id: Icf586229532819a7779652cbee73755b036dfbdc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The serirq enable bit defaults to true, so if we want it disabled, we
need to explicitly disable it.
BUG=b:180631748
TEST=Boot majolica and see spurious IRQ 9 gone.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Even though `device` entries are children of `chip` entries in the
devicetree source format, the chips in the translated C structures
are only hooked up to device nodes. Hence, to configure a chip in
a device- or overridetree, it always needs a `device` below it.
This should fix docking events for the X200 ThinkPad.
Change-Id: I561e7ae81f2e096a091868ce51daa1c8f66af067
Signed-off-by: Nico Huber <nico.h@gmx.de>
Found-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kevin Keijzer
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing.
BUG=b:180721202
TEST=builds
Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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For consistency with newer platforms, do this in pch.c instead.
Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Just call `fast_spi_cache_bios_region()` directly instead.
Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The MRC cache driver assumes BOOT_DEVICE_MEMORY_MAPPED=y already. This
is to ease factoring out common code across seven Intel platforms.
Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50951
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50950
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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RAM is not yet configured in bootblock. This function was copy-pasted
from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in
there can be removed as nothing else uses them.
Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done for consistency with newer platforms. Also clean up includes.
Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It only calls `smbus_common_init()`, so just call that directly.
Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Backport commit 03ed5bff5c (soc/intel/cannonlake: Move tco_configure to
bootblock), commit bb50c67227 (soc/intel/tigerlake: Move tco_configure
to bootblock) and commit 60c619f6a3 (soc/intel/jasperlake: Move
tco_configure to bootblock) to other platforms. This is for consistency.
Change-Id: I31fd0ceb67eacf30aefa457d757bf0d7f4cd7e87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's two instances of the same function, one for the bootblock and
another for romstage. Prefix them with the stage they are executed in.
Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50943
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to document 332691-003EN (SPT-H datasheet volume 2), the
hardware defaults to 0x44, which matches what newer platforms use.
Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The definitions are identical across seven platforms. Unify them.
Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done for consistency with newer platforms.
Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The iGPU is on the northbridge or system agent, not the southbridge.
Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Modify I2C3 setting to follow I2C specification (lower than 400kHz).
Original setting:
.rise_time_ns = 184
.fall_time_ns = 42
Change to:
.rise_time_ns = 110
.fall_time_ns = 34
BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Compute timings first, then display them. Drop unneeded comments, too.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45501
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr`
wrappers.
Change-Id: I7a6916e535fbba9f05451d5302261418f950be83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPR register's size field is given in whole MiB, so correct where it is
used to ensure the correct size multiple (KiB vs. MiB) is used with it.
Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling")
Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function returns true if any GPIO pad is programmed to route the
given IRQ to the IO-APIC. It does so by keeping track of which pads are
routed to IOxAPIC and looking this up in the new function.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This code will eventually support both ME 9.x and ME 10.
Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide.
Clamp any values that would overflow this field. Bits in TC_DTP already
get set when the tXP and/or tXPDLL values are large.
Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both files are equivalent. Drop Broadwell's ctdp.asl and use Haswell's.
Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Fill the ECC type in `struct memory_info` in romstage, and in SoC code.
The SMBIOS override is unnecessary, and this is not mainboard-specific.
Change-Id: I8370b3ee7d75914b895946b53923598adf87b522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are platforms that support error correction types other than
single-bit ECC. Extend meminfo to accomodate additional ECC types.
It is assumed that `struct memory_info` is packed to save space. Thus,
use `uint8_t` instead of an enum type (which are usually 4 bytes wide).
Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a method to disable decoding the legacy DMA IO ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
Measured I2C frequency just as below after tuning:
touchpad:372 kHz
audio codec RT5682:386.8 kHz
speaker AMP L:387.5 kHz
speaker AMP R:388.9 kHz
BUG=b:181342340
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ELAN touchscreen into devicetree for storo.
BUG=b:177389448
BRANCH=dedede
TEST=built storo firmware and verified touchscreen function
Change-Id: I0d9e5005928c6fda3d1f0ce8bd9ae135e4a04867
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50981
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds new soundwire device ALC1308
The codec properties are filled out as best as possible
with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
The unique ID is calculated from schematics by referring to ASEL[1:0]
strap settings. Datasheet of ALC1308 provides info about the mapping of
ASEL strap settings to unique ID
For example this device is connected to master link ID 1 and has strap
settings configuring it for unique ID 2.
chip drivers/soundwire/alc1308
register "desc" = ""Left Speaker""
device generic 1.2 on end
end
Bug=None
Test=Build and boot on TGLRVP.Extract SSDT and confirm that the entries for
PCI0.HDAS.SNDW are present for ALC1308
Test speaker out functionality
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ibf3f1d5c6881cbd106e96ad1ff17ca216aa272ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51042
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sathyanarayana Nujella
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:177834652
BRANCH=dedede
TEST=build kracko firmware
Change-Id: I360920f80f4ce5dcbcde25c433e23803fa72569b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This reverts commit d510b60f5b4eee6c165039be4acbe89ff25d8a4a.
This patch includes the DSDT ASL code for shadowmountain board.
BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch includes the ramstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SMBIOS type 17 asset tag. Use dimm locator as default value.
Tested=Execute "dmidecode -t 17" to check asset tag field is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I323e6b4cf6b11ede253d5a2a4bfc976a3f432b05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Currently, this function is only invoked for the SPI device through
common SoC code. Since both Intel Harcuvar and Scaleway Tagada have
enabled the SPI device in the devicetree, there's no need to use the
debug version of `pcidev_path_on_root`.
Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead, convert the struct to a union and pass in a pointer to it.
Tested on out-of-tree HP ProBook 6550b, still boots.
Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45367
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows booting without ME firmware, even though the 30-minute
auto-shutdown still happens. Without this patch, an HP ProBook 6550b
cannot get past the `setup_heci_uma` function call.
Change-Id: I446c02ac6034ede75cb873a2e676c40e4ef84b7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The PCIe device IDs for Ibexpeak are not in bd82x6x's pcie.c driver.
Thus, the code has always been dead code on Ibexpeak. Drop it.
Change-Id: Ide2b4af2a187ecf98f39a9c979646a7ed959c74f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51067
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Taken from document 322170-028 (5 series specification update).
Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues.
Without this patch, EHCI controllers had no IRQ assigned and there were
unexpected exceptions about NMIs. With this patch, the issues are gone.
Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brya’s chromeos.fmd contains a region for RECOVERY_MRC_CACHE,
but does not select HAS_RECOVERY_MRC_CACHE, so it’s unused.
BUG=b:174266035
TEST=Check MRC cache can allocate in recovery mode.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b83eec3dcf27bafde610a701e55f1371a5d4571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51081
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I667accd980da6384a7cc6a3f4eb7565b8b3b2400
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I3a67008d84da614e8c8cbfa681a0fdd19ff1d77f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexey Vazhnov <vazhnov@boot-keys.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Fetch second source factory cache configuration (SSFC) as an optional
element to the firmware config interface. Introduce a Kconfig so that it
can be enabled and used on required mainboards.
BUG=b:177055126
TEST=Build and Boot to OS in Magolor.
Change-Id: I81137406d21e77b5d58a33f66778e13cf16c85c7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51094
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As per CL:2641346, update GBB flag names:
GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW
GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW
BUG=b:179458327
TEST=make clean && make test-abuild
BRANCH=none
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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When the EC is reset on PLTRST this information will be lost, causing
system control interrupts to potentially stop functioning.
Change-Id: I137ef6c574a372601bc51f6e815158767acd0e1b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50489
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With this change NMI works in the kernel:
----------------
| NMI testsuite:
--------------------
remote IPI: ok |
local IPI: ok |
--------------------
Good, all 2 testcases passed! |
---------------------------------
See setup_lapic() for where this gets configured.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia391ec5a015d909462ff8aaf3cb047c6fd45fe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Follow elan's suggestion to configure IRQ as level trigger to prevent touchscreen lost
BUG=b:180778934
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I3aca0ad20791c989dec9e70d69d637b28c9cc043
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50417
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function should be using the RK_CLRSETBITS() macros to access the
special Rockchip write-mask registers, like the rest of our code. Also,
there were already existing bit field definitions for these bits that
should be used (although it makes sense to adjust them a bit to allow
passing in the channel number).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If1f5c06aabb16045d890df3bbd271f08a2cdf390
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51080
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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From JSL FSP v2376 "FirmwareVersionInfo.h" header file is
added and "FirmwareVersionInfoHob.h" is deprecated. This patch
adds support to display firmware version information using
"FirmwareVersionInfo.h" header file.
Changes included in this patch:
- Add Kconfig to select FirmwareVersionInfo.h
- Add code change to display firmware version info using
FirmwareVersionInfo.h header
No change in version info print format.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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This has been tested on the OCP Delta Lake platform.
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
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Add a weak variant routine to allow variants to perform any needed
initialization in ramstage.
BUG=b:178094376
TEST=none
Change-Id: I65dc1cdf15b68d9f2239e02fcb4b2c902d749378
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50827
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the missing PM initialization for Lynxpoint-H. There are some small
changes to Lynxpoint-LP, since some register writes are common among
both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to
Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values.
Without this patch, nearly all registers don't have the expected values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_E11 should be configured to be routed via APIC to avoid
p-sensor communication error in OS.
BUG=b:178465379
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected.
un-approach：
=> register address: 0x01 value: 0x00
approach:
=> register address: 0x01 value: 0x02
verify sx932x IRQ in "/proc/interrupts" loading as expected.
Change-Id: I7d639ec1f9b31b240475dc1c8025bf59ae1e8e0b
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50876
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the blipper variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:179648964
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BLIPPER
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Change-Id: I8e67521bd9ab05c257cb3d5d5d4cf506f258bfa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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New boards introduced to trogodor family.
BUG=b:180668002
BRANCH=none
TEST=make
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: If0f9b6c89198a882acae7191d08b166eb8c1dd71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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CB:50863 refactored the data_training() function to split out read gate
training into a separate function, but in the course of this forgot to
correctly initialize the local obs_err varible in the new function to 0.
This means that it will be used uninitialized, and when it happens to be
non-zero it makes the training process fail. Due to the convoluted
control flow in the function, it seems that GCC's static analyzer
couldn't pick up on this uninitialized use.
The whole variable is unnecessary anyway, all it's used for is to force
the function to return two lines below without doing anything with
side-effects in between. This patch removes the variable and simplifies
the code in all three training functions to avoid this uninitialized use
issue and make everything a bit more readable. (Also restore the
original pre-clang-format continuation line intendations for more
readability.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia475d64c06f2ec1bf9295742d173ce66717b821c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51079
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This causes the linux kernel to complain:
32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800
32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804
32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808
32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814
The linux kernel also verifies that the PM Timer block only uses IO
ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I53290226012d9f6c08c6adae0a633c7fd5702135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Stamp_boost 1640 parameter is too short to keep APU performance.
Restore parameter to 2500 then APU could have longer boost time (~3xxx sec)
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Change-Id: Ie08394d0b1a693f71336cb4cb6ce9528dfdce14b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Printing this in both bootblock and romstage is redundant, since the CPU
family and model aren't expected to change between bootblock and
romstage entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78b847c54c6cd3bfc2b947a579f4ba6b410fd2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Because the entries were formatted differently to the baseboard, the
devicetree overrides didn't work as intended, and all 5 entries from
the baseboard were included, and then the overrides were applied, but
the baseboard's entries were kept, so there were duplicate ACPI
entries, which causes errors when parsing the table.
Fixes: 5f30ae3714d ("mb/google/volteer: update thermal table for Eldrid")
BUG=b:181034399
TEST=compile, verify static.c is correct now
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the first version DPTF parameters. The TDP is down to 13w for acoustic concern.
BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test image and verified by thermal team.
Change-Id: I36f016530a61e3660938ce8d2948bb3b0f275d88
Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51030
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The headers added are generated as per FSP v2037.
Previous FSP version was v2037.
Changes Include:
- add BootFrequency, RMTBIT, RmtPerTask, RMTLoopCount and
MrcFastBoot UPDs in Fspm.h
- add EnableFastMsrHwpReq, VbtSize, CpuPcieComplianceTestMode,
LidStatus and PcieComplianceTestMode UPDs in Fsps.h
BUG=b:178461282,b:180627057
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I5496dfebc7b65a94abb31244ef2b400d89d6d444
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50914
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ide0e33826dd237bcd13f00400bbc8a08255b4f62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50945
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Broadwell has these devices, so add them to Lynx Point as well. This is
done in preparation to have Broadwell boards use Lynx Point ACPI code.
Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the first version DPTF parameters received from the thermal team.
BUG=b:177628854
TEST=cros build-ap --debug -b dedede --fw-name galtic
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia8e76d303db0add95e77693f15cad108fa92303b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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BUG=b:177399759
TEST=firmware_EventLog passed on asurada
BRANCH=none
Change-Id: I759f9030f525fa9e34ed542198a9dba8f25909f5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Rewrite early QPI initialisation to account for variables in the
register values. Trace replays did not capture these relationships.
Tested on out-of-tree HP 630, still boots.
Change-Id: I5d393e8222be286ab4d4dc074d85f721b07bbca4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49586
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7ed24e76df3c0542b04c0f072c1eaacceea4b71f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49965
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The device function is missing in the PCI device table in the PPR, but
is present in the hardware. Verified on a Mandolin board with PCO APU.
The corresponding ticket for the PPR is DESPCSOC-6667.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The PSP soft fuse bit 6 doesn't do what the comment above it says. See
NDA document #55758 for details.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic84cf6e1eee30af92cd700dc4bf78290143bf88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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DPR size is in MiB, but the range boundaries are expressed in KiB. In
addition, DPR and TSEG use the same attributes, so unify both regions.
Also improve a comment about DPR, since `is special` is uninformative.
Change-Id: I4479483e17890b5a4c39165138fa1c5f8215bc84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46987
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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