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2024-10-07soc/intel/alderlake: Hook up PCIe Power Management to option APISean Rhodes
Hook up PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUBSTATE to the option API. This provides users an easy way to disable power saving options that can limit performance. Change-Id: I2b06a7c734a4fd4073e86c668742ee35e1d79956 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81906 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07arch/x86: Remove CONFIG_DEBUG_NULL_DEREF_HALTMaximilian Brune
For more than 2 years the option has been unconfigurable. Since no one seems to have fixed that, the options seems to be not needed by anyone. So instead of making it configurable now, we can just as well remove it. Change-Id: I4055d497c7c23e148d2a09f216c7b910a9b3ea9b Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-10-07mb/google/fatcat: Add fatcatnuvo and fatcatite variantsPranava Y N
This patch adds "fatcatnuvo" and "fatcatite" boards to the fatcat Kconfig. BUG=b:369728249 TEST=Able to build fatcat/fatcatnuvo/fatcatite and verify the correct configs selected in coreboot.config Change-Id: Ice3f1d711426cb356c399de6390fef6f0e6bc748 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84648 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07mb/google/brya/var/glassway: Add audio codec ALC5650Daniel_Peng
1.Add AUDIO fw_config setting. 2.Add audio codec ALC5650 related settings for Gallida360 project. BUG=b:364798053 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I3761ca6d4cad18c74f5e1a056f0cb465dc4ac3ea Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-05soc/intel/pantherlake: Add FSP-S programmingJeremy Compostella
FSP-S UPDs are programmed according to the configuration (Kconfig and device tree) in ramstage. BUG=348678529 TEST=Hardware is programmed as desired and Intel Panther Lake reference board boots to UI. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84552 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-05mb/google/fatcat/var/fatcat: Rename audio codec optionsSubrata Banik
The new names include the `AUDIO_` prefix to clearly indicate that they are audio-related options. TEST=Able to build google/fatcat w/o any functional impact. Change-Id: Ia651c19f02423ee214a31168e2bd809e097ce8c2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-04mb/google/fatcat: change touchscreen fw_config name for THC I2CCliff Huang
use TOUCHSCREEN_THC_I2C instead of TOUCHSCREEN_THC0_I2C BUG=b:348678529 TEST=Able to build google/fatcat Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I689dd72a925c76ca6c2c9a941f4857daae20c943 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84652 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-04mb/google/fatcat: Add GPIO settingsJeremy Compostella
BUG=b:348678529 TEST=Boot google fatcat board till FSP memory training Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-04mb/google/fatcat/var/fatcat: Add FW_CONFIG for UFC and WFCSubrata Banik
BUG=b:348678529 TEST=Able to build google/fatcat. Change-Id: I4061b9b4c1e515e8c078c67f30f29eee87b84a66 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84645 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-03soc/amd/glinda/.../iomap.h: Update for glindaMaximilian Brune
Remove TODO after checking the addresses are still valid. source: PPR 57254 Rev 1.59 Table "Address Space Mapping under APB BUS" Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-10-03soc/amd/glinda/include/smu.h: Update mailbox register addressesAvinash Munduru
Signed-off-by: Avinash Munduru <AvinashMunduru@amd.com> Change-Id: I427186aa9f0fb0650b2ab8d6171a51a33edf2778 Tested-by: Avinash Munduru <Avinash.Munduru@amd.com> Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84384 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03soc/amd/.../amd_pci_int_defs.h: Update according to datasheetMaximilian Brune
HPET and MISC1/2 and registers are used interchangeably in the datasheets. Add an alias to emphasise that they refer to the same. source: PPR #57396 Rev 3.10 Table "ValidValuesTable: PCI interrupt index list" PPR #57254 Rev 1.59 Table "ValidValuesTable: PCI interrupt index list" PPR #57396 Rev 3.10 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map PPR #57254 Rev 1.59 FCH::IO::IntrMisc1Map and FCH::IO::IntrMisc2Map Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84574 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03soc/amd/*: Explicitly include static.h for config_of_socNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I9db5d80ca0a75ccff3b8e24db0ccbd6b36c84dcb Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-03mb/google/hatch/var/dratini: Add FP enableJon Murphy
Add FP enable/disable based on SKU ID for Dratini. This is meant to resolve a UMA issue with Dratini devices that had the FPMCU populated on non-fp devices. Since the FPMCU is present, and the firmware enables the power GPIO's based on variant, not SKU, the devices were reporting data on fingerprint errantly. BUG=b:354769653 BUG=b:200825114 TEST=Flash to Dratini, test FP. Disable test SKU, flash on Dratini, test FP. To test, run `ectool --name=cros_fp version` in the shell When enabled, the fpmcu fw version should be displayed. When disabled, an error should be displayed because the fpmcu is inaccessible. Change-Id: Ifc450f51b00b9c3b62268ce94884f5749a3e18c0 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-03acpi: Add IORT helper functionsNaresh Solanki
IORT table represents IO topology of an Arm based system for use with the Advanced Configuration and Power Interface (ACPI) Add helper functions for ACPI IORT table for: 1. ITS (Interrupt Translation Service) 2. SMMUV3 3. ID MAP 4. Named Component 5. Root Complex Based on document: DEN0049E_IO_Remapping_Table_E.e Change-Id: I7feaf306b5eea21bfc9a2e2a1a2c3ddc3c683c0b Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79404 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03soc/intel/pantherlake: Remove soc_info.[hc] interfaceJeremy Compostella
This commit removes the unnecessary layer provided by soc_info.[hc]. It was providing an abstraction which only was resulting in extra function calls without any added value as the returned constants are well identified and could be used directly. More importantly, and this is the actual selling point in my opinion, this extra indirection was preventing the compiler from detecting array overflows. BUG=348678529 TEST=Build is successful Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6986 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-03mb/starlabs/{lite_adl,byte_adl}: Don't select MAINBOARD_HAS_TPM2Sean Rhodes
This isn't required by these boards as they both use PTT. Change-Id: I66b3f614914e51116f3cabe457205fb6b3528387 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84629 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03mb/starlabs/*: Don't disable Turbo Boost in Power Saver profileSean Rhodes
Tested on 24.04, disabling Turbo Boost increases power consumption which doesn't align with the aim of the Power Saver profile. Change-Id: I19e8189ee6c44d19bf222c921429284ed1e1aa2a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84628 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03mb/starlabs/starbook/kbl: Disable DPTFSean Rhodes
Change-Id: I68b285ff098127b7becf4aa8736e66fd6b2c4a32 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/kbl: Remove PMC GPIO routingSean Rhodes
Change-Id: Ibb92d76f15be71ecb1e2187c7e235235585f8793 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/kbl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I5beda22208fe17338d4136f9d38fd50e55054b01 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/cml: Add USB ACPI to devicetreeSean Rhodes
Change-Id: I140d597750001ad22e2bb1b6971011d2b3bb2bbc Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84272 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/tgl: Add USB ACPI to devicetreeSean Rhodes
Tested on Ubuntu 24.04 by verifying dmesg output and that USB 2.0 and 3.0 devices are registered correctly. Change-Id: I803a23007f49ea45abc68421e867535081e31b3f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84271 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03mb/starlabs/starbook/tgl: Disable DPTFSean Rhodes
DPTF is not used on this platform so disable the PCI device. Change-Id: I763ab948a79e3a020c1b89c69c714dd0d8f54812 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84270 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-10-03mb/starlabs/starbook/tgl: Remove PMC GPIO routingSean Rhodes
These aren't used so remove them. Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/tgl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I6bab0a316ea7d0f7dfbf599e5c08517cee559635 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook: Move MAINBOARD_HAS_TPM2 selectionSean Rhodes
MAINBOARD_HAS_TPM2 should only be selected for the boards that have memory mapped TPMs. The ones that use Intel PTT don't need it. Change-Id: I02b5b0912afbd7c4634c208bb17db16d0ac7ba99 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/cml: Disable DPTFSean Rhodes
DPTF is not used on this platform so disable the PCI device. Change-Id: I7fa01936568108dd7707a3c2ea7041a1198533b5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84266 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03mb/starlabs/starbook/cml: Remove PMC GPIO routingSean Rhodes
These aren't used so remove them. Change-Id: I6b9cf29843047bff9a37f82b899ff1d10b206888 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-03mb/starlabs/starfighter: Add Raptor Lake StarFighter Mk I variantSean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 24.04 No known issues. https://starlabs.systems/pages/starfighter-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/google/fatcat: Add Panther Lake SOC supportSaurabh Mishra
- This patch update the original google/fatcat support added with Meteor Lake support as a workaround. - Add initial support to build google/fatcat for Panther Lake SOC - Add soc acpi file entry in mainboard dsdt.asl BUG=b:348678529 TEST=Build google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03stddef.h: Introduce nullptr constantElyes Haouas
GCC-13 introduced the nullptr constant. Use it when compiling with the C23 standard. Change-Id: I07db866bebfd25f1a60d18a3228ada2957500234 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83459 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/intel/cannonlake,skylake: Fix locking SMRAMMichał Żygowski
Intel TXT SINIT required the D_LCK bit set. Although coreboot tries to set it, the bit ws still clear. The D_LCK bit has to be set using I/O CF8/CFC cycle. TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled Change-Id: I03aff482b53ab7b0bcaccf18e47ad4c22b53583c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-02arch/x86: Shadow ROM tables into EBDAShuo Liu
For platforms without writable PAM-F segment support (e.g. some simics virtual platforms), put ROM table pointers (e.g. ACPI/SMBIOS low pointers) into EBDA. Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Change-Id: I2aac74708279813f9a848044d470fdc980ea4305 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2024-10-02soc/intel/meteorlake: Correctly set Usb4CmModeSean Rhodes
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set the UPD to match this to avoid the connection type being mismatched. If it's mismatched, the TBT port will timeout. TEST=Boot starbook/rpl and check TBT 4 dock is correctly identified. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add Reviewed-on: https://review.coreboot.org/c/coreboot/+/77567 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-02soc/intel/xeon_sp: Use MemoryMapDataHob to add high RAM resourcesShuo Liu
On GNR, there are CXL Type-3 memory windows covered under TOHM. The current 4GB to TOHM DRAM reporting doesn't work on GNR. Use MemoryMapDataHob to add high RAM resources as a generic mechanism for GNR and previous generation SoCs. TEST=Build and boot on intel/archercity CRB TEST=Build and boot on intel/beechnutcity CRB (with topic:"Xeon6-Basic-Boot") Change-Id: Ie5fbc5735704d95c7ad50740ff0e35737afdbd80 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84304 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/mt/mt8196/gpio_eint.c: Add assert messageArthur Heymans
This fixes the following warning with clang (18.1.6): src/soc/mediatek/mt8196/gpio_eint.c:259:44: error: '_Static_assert' with no message is a C23 extension [-Werror,-Wc23-extensions] 259 | _Static_assert(ARRAY_SIZE(eint_data) == 293); | ^ | Change-Id: I934b6d7ee8e8a0c204a4e328331c3ff3cd0f07de Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84618 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02mb/starlabs/starbook/cml: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I063062d875be61875da136228db06a39bc434833 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-10-02mb/google/brox/jubilant: Modify GPIO for WWANRen Kuo
The LTE module RW101R-GL provide a hardware pin to enable/disable WWAN RF function.The function is disabled in default and is controlled by the AT command.Therefore,set the WWAN_RF_DISABLE Pin to NC, and it has been pull-high by hardware desgin. BUG=b:368450447 BRANCH=None TEST= Build firmware and verify the WWAN on/off function in OS. Change-Id: I47a28342f67f99c5787077c48a01ddbaa77b5967 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-10-02drivers/tpm: Remove unused 2nd argument in FUNC methodSean Rhodes
The method "FUNC" allows 1 argument, so remove the incorrectly referenced and unused second arguemnt. This fixes: ToInteger (Arg1, Local1) Error 6006 - ^ Method argument is not initialized (Arg1) Change-Id: If5e402579a2caff169e12253e5d9c2c493902ec7 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-10-02arch/arm64: Add Clang as supported targetArthur Heymans
QEMU aarch64 boots to payload when compiled with clang. Change-Id: I940a1ccf5cc4ec7bed5b6c8be92fc47922e1e747 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74501 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/qualcomm/sc7{1,2}80: Increase early stages size for clangArthur Heymans
Clang builds slightly larger binaries so increase the section. The qcsdi is used for an external blob that is currently not in use so reducing the size is fine for now. Change-Id: Ide01233f209613678c5408f1afab19415c1071be Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-10-02soc/intel/pantherlake: Delete duplicated lineJeremy Compostella
BUG=348678529 TEST=Build successful Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6987 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84607 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02soc/intel: Deprecate SoC-specific global reset status configsSubrata Banik
This change removes the SoC-specific `FSP_STATUS_GLOBAL_RESET_REQUIRED_X` Kconfigs, as they are no longer necessary for handling FSP global reset requests. Previously, these Kconfigs were used to select a specific 32-bit reset status code. However, with the introduction of FSP 2.4 and 64-bit interfaces, the global reset status code can now vary between architectures. To address this, the FSP driver now sets the `FSP_STATUS_GLOBAL_RESET` config to a common default value (depending upon most commonly used global reset status code) based on the interface: - 0x40000003 for 32-bit FSP interfaces - 0x4000000000000003 for 64-bit FSP interfaces This default can be overridden if an FSP implementation uses a different status code (for example: Apollo Lake selects different FSP reset status code as 0x40000005). By removing the SoC-specific configurations, this change simplifies global reset handling and ensures compatibility across different FSP versions and platforms. Below table shows the relationship between Platform, FSP and FSP Global Reset Status: +-----------------+--------------+-------------------------+ | Platform | FSP | Global Reset Status | +-----------------+--------------+-------------------------+ | Alder Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Apollo Lake | 32-bit | 0x40000005 | +-----------------+--------------+-------------------------+ | Cannon Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Elkhart Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Jasper Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Meteor Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Sky Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Tiger Lake | 32-bit | 0x40000003 | +-----------------+--------------+-------------------------+ | Panther Lake | 64-bit | 0x4000000000000003 | +-----------------+--------------+-------------------------+ BUG=b:347669091 TEST=Verified FSP requested global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. w/ 32-bit FSP: ``` (Wdt) AllowKnownReset [FspResetSystem2] FSP Reset Initiated FSP returning control to Bootloader with reset required return status 40000003 FSPS, status=0x40000003 FSP: handling reset type, status=0x40000003 GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command ``` w/ 64-bit FSP: ``` (Wdt) AllowKnownReset [FspResetSystem2] FSP Reset Initiated FSP returning control to Bootloader with reset required return status 3 FSPS, status=0x4000000000000003 FSP: handling reset type, status=0x4000000000000003 GLOBAL RESET! global_reset() called! HECI: Global Reset(Type:1) Command ``` Change-Id: I32bdbf7ea6afa7d5e5f91ea96d887719d26a593f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84572 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-01soc/intel: Correct return type of fsp_get_pch_reset_status()Subrata Banik
The `fsp_get_pch_reset_status()` function returns a FSP reset status code. This change corrects its return type from `uint32_t` to `efi_return_status_t` to ensure consistency with the FSP API and prevent potential issues caused by type mismatch. This correction is necessary for compatibility with both 32-bit and 64-bit FSP interfaces. The change also updates all callers of this function in the Meteor Lake and Panther Lake SoCs to use the correct return type. Includes `fsp/api.h` to provide the `efi_return_status_t` definition. BUG=b:347669091 TEST=Verified global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84571 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01drivers/usb/acpi: Add a Power Resource for Intel BluetoothSean Rhodes
Add a Power Resource for Intel Bluetooth, that can reset the Bluetooth using the delay configured in the DSM. Change-Id: I3b25fd180e21100e3cb001fc6ba0da7f47b2ad12 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84146 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01soc/intel/common/cnvi: Add CNMT MutexSean Rhodes
Add "CNMT" Mutex, that will be used by the Bluetooth and CNVi driver. Change-Id: I607865458f925d6f4aa713e07cfa34e83b2e5c8f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84598 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01soc/intel/cannonlake: Fix USB port numbersMaxim Polyakov
It should be in HEX. Change-Id: I15a354bae414ad94a2f76030b3099179022b935c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84546 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01mb/starlabs/starbook/adl: Disconnect SCI/SMI GPIOsSean Rhodes
The platform uses eSPI so these are not needed. Change-Id: I507aa59fcf2540ae6170896a51aa952f5e73eee8 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83691 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01mb/ibm/sbp1: Add SMMSTOREPatrick Rudolph
Add SMMSTORE to the default FMAP to allow using UefiPayload on this board that requires a non-volatile variable store. TEST: Booted an UEFI compatible OS using EDK2 as payload. Change-Id: I32fb0a882c62e42da9f3caec54f8d33333fc8598 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01tree: Use boolean for dptf_enableElyes Haouas
Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84161 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30chromeec/ec_acpi: Define ACPI devices for USB-C ports using UCSIJameson Thies
Add support to define ACPI devices for USB-C ports using UCSI. When defining the typec configuration do not set mux/retimer information. cros_ec_ucsi does not support setting USB muxes. BUG=b:349822718 TEST=emerge-brox coreboot chromeos-bootimage. Boot to OS on brox, confirmed that there are ACPI devices for each USB-C port and cros_ec_ucsi correctly matched the ACPI devices ("ls -l /sys/class/typec" with an update to add an ACPI match table to the cros_ec_ucsi driver). Change-Id: Ie7c281fe2a7fab705d3c238dcc4be68c93afd652 Signed-off-by: Jameson Thies <jthies@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84404 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30device_util: Add support for GICv3 path in device path handlingNaresh Solanki
Change-Id: Ib4004c1f1b854a54dfdf9eaa7f25583dec947302 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79972 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30arch/x86: Configure EBDA through KconfigGang Chen
EBDA (Extended BIOS Data Area) is a memory area below 0xA0000 and one of the default areas where OS will scan ACPI RSDP pointer from. coreboot's default EBDA's starting address is 0xF6000, which is in PAM (Programmable Attribute Map) F-segment's scope. For some platforms without writeable PAM-F segment (e.g. some simics virtual platforms), corboot's default EBDA is not writable. Make DEFAULT_EBDA_LOWMEM, DEFAULT_EBDA_SEGMENT, DEFAULT_EBDA_SIZE as Kconfig items so that coreboot's EBDA could be relocated to a writable low memory place. Change-Id: Icd7ba0c902560f7d498934392685dc2af9c5ce09 Signed-off-by: Gang Chen <gang.c.chen@intel.com> Co-authored-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-09-30soc/amd/glinda: Update pci int defsMaximilian Brune
Update IRQs according to datasheet/PPR. source: PPR #57254 Rev 1.59 Table 137 Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84375 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/amd/glinda: Update gpp bridge naming schemeMaximilian Brune
This patch updates the naming scheme used for the GPP bridges. The naming scheme now matches what we also have on phoenix. Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-09-30mainboard/intel/beechnutcity_crb: Update full IIO configurationJincheng Li
Change-Id: I7f4f5406df8ff82b8d3052ff0f370c280967affd Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84319 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/amd/glinda: Update SCI mappingMaximilian Brune
source: PPR #57254 Rev 1.71 Change-Id: I5eaed888109b89c25bcf0ba91abefa7c36c1851b Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84381 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/amd/glinda/include/soc/smi.h: Update for glindaMaximilian Brune
It aligns the names in the datasheet with the one in the code. It also removes and adds some. Resource: Document 57254 Chapter 15.3.5 TODO it may very well be that I don't have the full truth, because most of these register just have a different name and some of these names like ESPI seem more recent that for example LPC. Change-Id: Iad848ff400ef80777d0cbb2b582b9b5fa8bf11f3 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-09-30soc/amd/glinda: Remove non-exisiting I2C definitionsMaximilian Brune
Glinda doesn't contain I2C4 and I2C5 like Mendocino it was copied from. Remove their definitions. Reference: Document 57254 Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-09-30mb/google/brya/var/bujia: Add Wifi SAR for bujiaShon
Add wifi sar for bujia. BUG=b:345364452 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I5a67f3723a9dc33793a5cd95f9a3a2596c3c1fc6 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84501 Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-09-30mb/google/kahlee/var/careena: Make sure bid isn't used uninitializedArthur Heymans
GCC with LTO cought this. Warning: src/mainboard/google/kahlee/variants/careena/variant.c:44:12: error: 'bid' may be used uninitialized [-Werror=maybe-uninitialized] 44 | if (bid == 7) | ^ src/mainboard/google/kahlee/variants/careena/variant.c: In function 'car_stage_entry': src/mainboard/google/kahlee/variants/careena/variant.c:24:18: note: 'bid' was declared here 24 | uint32_t bid; Change-Id: Ie732b5be5cd9dc0abaf1a5efe023bcb0738dba1d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84206 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: coreboot org <coreboot.org@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/mediatek/mt8196: Fix timer reset in BL31Jarried Lin
After reboot, the system does not need to serve pending IRQ from systimer. Therefore, clear systimer IRQ pending bits in init_timer(). For that to work, the systimer compensation version 2.0 needs to be enabled. TEST=Build pass and timestamp is not reset in ATF and payload BUG=b:343881008 Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59 Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83928 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-09-30drivers/i2c/at24rf08c: Disable DRIVER_LENOVO_SERIALS by defaultNicholas Sudsgaard
This should be the sane default, as having this option enabled when the AT24RF08C (Asset Identification EEPROM) is not present on the mainboard can cause SMBIOS table entries to become "*INVALID*". This can, for example, result in strange hostnames when an OS installer uses SMBIOS information to automatically generate one. On the other hand, the coreboot generated SMBIOS tables will at least always contain basic information. Therefore, this driver should be treated as an enhancement rather than a default. Currently, the following mainboards have this option disabled: - ThinkCentre M710s - ThinkCentre M700 / M900 Tiny - Haswell ThinkPads - ThinkPad T440p - ThinkPad W541 Therefore, we can remove this option entirely on these mainboards. Note that there may be other mainboards which do not have this chip present but still have the option enabled. However, this requires a more detailed investigation which would be out of scope of this change. TESTS=Timeless builds on lenovo mainboards produce the same binary. config INCLUDE_CONFIG_FILE default n Was temporarily added to `mb/lenovo/Kconfig` during these tests, as while the configuration does not change, the order of entries do. Therefore, technically producing a different binary when included. Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84544 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-30mb/google/nissa/var/riven: Add 2 memory parts and generate DRAM IDsDavid Wu
Add two new memory parts 1. K3KL8L80CM-MGCT (Samsung) 2. H58G56BK8BX068 (Hynix) BUG=None TEST=Run part_id_gen tool and check the generated files. Change-Id: I557b359d9e639f6c3fac4239eb28aa7e0bed4c0e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-30mb/starlabs/byte_adl/mk_ii: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: Ibb167b8dc379ca331812255c3e7e049556f2b57b Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-09-30mb/google: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This corrects the mismatch found in the verb tables of Monroe Chromebase and Link Chromebook. The verb data was not aligned to a multiple of 4, therefore an entry was repeated as padding. This was found due to the `_Static_assert()` from CB:84360 failing. TEST=Tested on LINK under Linux and Win11, audio working properly under both. Change-Id: Id377281af310642a6ba77e5a0002ca1dfca38827 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84414 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30mb/samsung/lumpy: Correct number of jacks in hda_verb.cNicholas Sudsgaard
The verb data was not aligned to a multiple of 4, therefore an entry was repeated as padding. This has not been tested. This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84395 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30libgfxinit: Allow to configure screen rotationNico Huber
This allows to configure a default screen rotation in 90-degree steps. The framebuffer contents will then be displayed rotated, by the same amount in the other direction; i.e. if you turn the screen to the left, the picture has to be rotated to the right to accommodate. This is only supported by libgfxinit from Skylake / Apollo Lake on (earlier GPUs didn't support the 90-degree steps anyway) and it only works with the linear-framebuffer option. Change-Id: Iac75cefbd34f28c55ec20ee152fe67351cc48653 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-30soc/intel/common: systemagent: Fix typo in HAVE_BDSM_BGSM_REGISTER help textPaul Menzel
regist*re*s → regist*er*s Change-Id: Ie5f5cb481f0fac335e592fd3f1f56d5462e37c1e Fixes: 2b0b2ef9a258 ("soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-09-30mb/google/brox/var/lotso: Fix goodix touchscreen power off sequenceKun Liu
Poweroff does not seem to use the ACPI _OFF function, but rather the smihandler. Creating variant_smi_sleep function for nami to handle the power off sequence during reboot/poweroff. BUG=b:364193909 TEST=emerge-brox coreboot Change-Id: I0108be4e5e7c0265aae0f16fd4e2b7cbe5936112 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84412 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30mb/google/brox/var/lotso: Update DTT settings for thermal controlKun Liu
Update DTT settings according to b:348285763#comment20 in order to increase the limit of the charging current to 3A. BUG=b:348285763 TEST=emerge-brox coreboot, and thermal engineer verifies OK. Change-Id: I24978afd819666f635c85f2be9b71d39e0a39f27 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84527 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30mb/google/brox/jubilant: Modify start-up timing for WWAN RW101R-GLRen Kuo
Modify start-up timing for WWAN RW101R-GL to follow spec: PWR_EN H H H FCPO# Tpr H H RESET# L Ton H Tpr: delay for Power stable (>0ms) Ton: delay for reset time (>20ms) BUG=b:349698817 BRANCH=None TEST= Build firmware and verify on jubilant with RW101R-GL Measure the start-up timing sequence to meet spec Boot up in OS, and confirm WWAN can connect to cell site Change-Id: I7aa3e7a172143ff1cebea7f48bda45d4fb2c77f7 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-28sconfig: Move config_of_soc from device.h to static.hNicholas Chin
Many sources include device.h and thus static.h, but many only need the function declarations and type definitions, not the compiled devicetree from sconfig. This causes many unnecessary recompiles whenever the devicetree is updated due to the dependency. Address this by moving the config_of_soc macro directly into the generated static.h header, as it seems to be the only line in device.h that actually requires static.h. For now, static.h remains included in device.h so that the build is not affected. Subsequent commits will include static.h directly into sources that actually need it, after which it can be dropped from device.h. Some statistics for C objects: Dell Latitude E6400 (GM45/ICH9): 669 total objects 181 depend on static.h 2 require static.h Dell Latitude E6430 (Ivy Bridge/Panther Point): 693 total objects 199 depend on static.h 3 require static.h Lenovo ThinkCentre M700 / M900 Tiny (Kaby Lake): 794 total objects 298 depend on static.h 23 objects require static.h MSI PRO Z690-A (WIFI) DDR4 (Alder Lake): 959 total objects 319 depend on static.h 25 require static.h The number of objects was determined by grepping the build log for calls to CC, the number of objects that depend on static.h was determined by grepping for calls to CC after touching static.h, and the number of objects that actually require the static.h related lines from device.h was determined by grepping for objects that failed to build after removing the static.h lines from device.h and running make with the --keep-going flag. Change-Id: I7c40135bf2815093b81e47201c38b7d0a6ac8fa8 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-09-28soc/intel/pantherlake: Add FSP-M programmingJeremy Compostella
FSP-M UPDs are programmed according to the configuration (Kconfig and device tree). BUG=348678529 TEST=Memory is initialized successfully and hardware is programmed as desired on Intel pantherlake reference board. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84443 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-28vc/intel/fsp: Update PTL FSP headers from dummy headers to v2382_01Ronak Kanabar
Update generated FSP headers for Panther Lake from v2382_01 Changes include: - Update FspmUpd.h, FspsUpd.h, MemInfoHob.h and FirmwareVersionInfo.h BUG=b:348678529 TEST=Able to build google/fatcat Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2020 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-27mb/google/fatcat/var/fatcat: add support for wifi sar tableYH Lin
Add wifi sar table support for fatcat. Bit 4-5 in CBI/FW_CONFIG is used to select different sar table (index 0 to 3). BUG=b:348678529 TEST=emerge-fatcat coreboot chromeos-bootimage Change-Id: I2d82f76d7c11378ee5c221a6b9621b4cba83720d Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-09-27soc/intel/pantherlake: Comply with the no typedef coding style ruleJeremy Compostella
As https://doc.coreboot.org/contributing/coding_style.html#typedefs states: "In general, a pointer, or a struct that has elements that can reasonably be directly accessed should never be a typedef". This commit makes the Intel Panther Lake SoC code comply with this by using explicitly `struct soc_intel_pantherlake_config' in the soc/intel/pantherlake code as I have been suggested to for the `fsp_params.c' files. The rule being the rule and consistency across a project matters more than personal preferences. The documentation lists five exceptions and none on them cover the use of `config_t' instead `struct soc_intel_pantherlake' but I believe it does not make the code better for the following three reasons: 1. It is repetitive, make the line longer and the code is in soc/intel/pantherlake so obviously the config_t data structure is the pantherlake soc configuration. 2. It makes re-usability from one generation to another unnecessarily harder. 3. This config_t abstraction is required for and used by some common block code anyway. Hence, we end-up with some code using `config_t' and other using the final structure which break the consistency of the code when the project in looked as a whole. BUG=348678529 TEST=Google fatcat mainboard compiles Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2021 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-27mb/hardkernel/odroid-h4: Add support for ODROID-H4 seriesDavid Milosevic
Add support for the ODROID-H4 family of boards. Tested on an ODROID-H4+ board, but all of them use the same PCB (with different components). The four SATA ports on the mainboard are provided by an onboard ASMedia ASM1064B PCIe-to-SATA bridge. Unlike other mainboards in the tree using an ASMedia ASM1061 or ASM1062 PCIe-to-SATA bridge, the ODROID-H4+ comes with a SPI flash chip for the ASM1064B and does not seem to have issues regarding PCIe power management (e.g. ASPM) or unusable SATA AHCI mode. The ODROID-H4 comes with a single 16 MiB SPI flash chip. The ODROID-H4+ and the ODROID-H4 Ultra feature Dual BIOS, consisting of another 16 MiB SPI flash chip and a 3-pin header to select between them. The board can be flashed internally or using a SOIC-8 clip, but the M.2 slot may need to be empty for the clip to fit. Working: - DDR5 SO-DIMM slot - All SATA ports on ASMedia ASM1064B PCIe-to-SATA controller - UART to emit spam - All video outputs (FSP GOP only lights up one output at a time) - All USB ports (on the Ethernet connectors and on EXT_HDR1) - M.2 M connector (PCIe only) - PCIe power management - Ethernet NICs - eMMC - HD audio codec and display audio - S3 suspend/resume - SeaBIOS <current version> - MrChromebox edk2 <current version> - Super I/O HWM on Linux (using out-of-tree it87 kernel module) - Booting Arch Linux from NVMe and SATA - Booting Windows 10 from NVMe Not working: - PECI: undocumented protocol and undocumented Super I/O - Resuming on Windows 10 BSODs with `VIDEO_TDR_FAILURE` Untested: - Fan curves: may need to lower the temperature limits a bit Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-09-27mb/google/brya: enable config DRIVER_INTEL_ISH_HAS_MAIN_FW for truloJayvik Desai
Trulo ISH uses the MAIN FW loaded by the kernel driver. This commit enables DRIVER_INTEL_ISH_HAS_MAIN_FW for trulo, which skips printing the ISH BUP version. BUG=b:360144613 TEST=Local build successful and tested on trulo by toggling the config. enabling this config skips printing the ISH version in cbmem. 1. CONFIG enabled ``` trulo-rev1 ~ # cbmem -c | grep ISH [INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin ``` 2. CONFIG disabled ``` trulo-rev1 ~ # cbmem -c | grep ISH [DEBUG] ISH version: 5.4.2.36864 [INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin ``` Change-Id: Ifebd563ec8ddb0378e1215a90396687857f3f71d Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84494 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-27driver/intel/ish: Add config to indicate the presence of ISH MAIN firmwareJayvik Desai
This commit introduces a new config DRIVER_INTEL_ISH_HAS_MAIN_FW to indicate that the Intel Sensor Hub (ISH) is using the ISH MAIN firmware. The ISH MAIN firmware is located in rootfs, hence we no longer need to store the ISH BUP version in the CSE partition. When this config is enabled, fetching the ISH BUP version from the CSE firmware partition is skipped. BUG=b:360144613 TEST=Local build successful and tested on trulo by toggling the config. Enabling this config skips printing the ISH version in cbmem. Change-Id: I6cacf7b44ce6895ecb96db295d184c7b7d5a872c Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84493 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-09-27mb/google/fatcat/var/fatcat: Add initial FW_CONFIGSubrata Banik
BUG=b:348678529 TEST=Able to build google/fatcat. Change-Id: I5c90aac4873dcc57e65e641656dca3a96f84d6b8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84543 Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-26soc/amd/glinda/chipset.cb: Add missing devicesMaximilian Brune
Source: Document 57254 Change-Id: I9675d45eba257e52d9a870a4cc153b925267f840 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-09-26mb/amd/birman*/devicetree_glinda.cb: Add usb3_port1Maximilian Brune
Change-Id: Ida2499d9894aa99f341c7a6ef2cd93b3f8ea61fe Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-26soc/amd/glinda/chipset.cb: Update for glindaSatya SreenivasL
This also updates the mainboards depending on it. Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84376 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-26mb/google/{nissa,trulo}: Add Vccin Aux Imon Iccmax default valueSimon Yang
Add default value in nissa and trulo devicetree.cb, ODM have to review the board design to follow RDC#646929 Power Map requirement. NOTE: The VccInAuxImonIccImax remains unchanged w/ and w/o this CL. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST='emerge-nissa coreboot chromeos-bootimage' Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83725 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-26mb/intel/archercity_crb: Enable native graphics initPatrick Rudolph
Enable the AST 2600 native graphics init driver to have a working UEFI firmware menu displayed over KVM. Change-Id: I2961576077ed3286df080cd09ffe68d835d8c3e7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-26drivers/aspeed/common: Add AST2600 supportPatrick Rudolph
Add support for AST2600 as found on Intel Archer City CRB by using the code found on Linux's ast drm driver. While on it do minor modifications found on the Linux drm driver that also affect the other ast chips. New log messages: [INFO ] ASpeed AST2050: initializing video device [INFO ] ast_detect_chip: VGA not enabled on entry, requesting chip POST [INFO ] ast_detect_config_mode: Using P2A bridge for configuration [INFO ] ast_detect_chip: AST 2600 detected [INFO ] ast_detect_chip: Analog VGA only [INFO ] ast_driver_load: dram MCLK=890316000 MHz type=3 bus_width=16 size=01000000 [ERROR] No header found [INFO ] ast_select_mode: Failed to decode EDID [DEBUG] Assuming VGA for KVM [DEBUG] AST: Display has 1024px x 768px [DEBUG] Using framebuffer 1024px x 768px pitch 4096 @ 32 BPP [INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32 [INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0x94000000 [INFO ] ASpeed high resolution framebuffer initialized TEST: Booted on Intel/ArcherCity CRB and used the UEFI firmware menu over KVM using native graphics init. Change-Id: I3d2d58d493706673c1b2ba4953967b1641bd6395 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-09-26vc/intel/fsp/fsp2_0/graniterapids: Update to formal FSP header filesJincheng Li
Change-Id: I6e94f44d50f2b53855adc1bb1cd6a1a5d9929003 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-09-26mb/ibm/sbp1: Update PCIe SBDF in commentNaresh Solanki
Update PCIe Segment, Bus, Device & Function for various IIO bridge devices. Change-Id: I01d164cf0717b3e817348e64e32478c2bb11a8b8 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-09-26soc/intel/ptl: Remove tcss_d3_hot_disable en config structure fieldJeremy Compostella
This commit drops tcss_d3_hot_disable chip config as FSP is not exposing the same purpose UPD anymore starting with Panther Lake SoC. BUG=b:348678529 TEST=Build for fatcat Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2024-09-25vc/amd/opensil: Move openSIL interface declarations to common headerNicolas Kochlowski
The declarations describing interface functions between SoCs and openSIL glue code are common for the stub and Genoa POC, and likely with future SoC openSIL implementations. Therefore, move these out of SoC-specific header files and into vc/amd/opensil/opensil.h. This change facilitates swapping out the stub for the actual openSIL glue code. Change-Id: Icc8783ddb868f9f0c4cd357245604313eadfe531 Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84428 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/brox/var/lotso: Add RTS522A vdd ctrl by GPP_A17Jian Tong
For next DVT build, hw adds this power ctrl. BUG=b:359409425 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84254 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/brox/var/lotso: Update cpu power limitsJian Tong
When battery not present, increase PL4 limit from 9 to 40. Get PL setting from internal thermal and power team. AC+DC/DC: PL1=15W PL2=25W PL4=114W AC ONLY: PL1=15W PL2=25W PL4=40W BUG=b:355094551 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Confirm on lotso EVT board, as expected. Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84202 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/brox/var/lotso: Generate RAM ID for H58G56BK7BX068Jian Tong
BUG=b:342929824 BRANCH=None TEST=boot to kernel success Change-Id: Ibc13137488948ec6cea1904b3964ffed4ff7ea7d Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84499 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/fatcat: Add HDA verb tablesJeremy Compostella
We use ALC256 as HDA codec on fatcat hence, added the verb table. BUG=b:348678529 TEST=Tested audio playback using HDA ALC256 codec on PTL reference board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d55 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84409 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/fatcat: Add memory settingsJeremy Compostella
BUG=b:348678529 TEST=Memory training is successful on google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d51 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84406 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-25mainboard/google/fatcat: Update SoC to Panther LakeSubrata Banik
This commit updates the fatcat mainboard to use the Panther Lake SoC instead of Meteor Lake. The changes include: - Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option. - Updating the `mainboard_update_soc_chip_config()` function to use the `soc_intel_pantherlake_config` struct. - Updating the devicetree to use the `soc/intel/pantherlake` chip. - Updating variant header files to reflect the SoC change. This update enables support for the Panther Lake SoC and its features on the fatcat mainboard. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mainboard/google/fatcat: Remove unused virtual GPIOsSubrata Banik
This commit removes the virtual GPIOs for recovery and write protection from the fatcat variant. These GPIOs are not utilized on the fatcat platform, and their removal simplifies the GPIO configuration and improves code readability. The `CROS_GPIO_DEVICE_NAME` macro is no longer applicable for Panther Lake SoCs. Future changes will introduce a suitable GPIO device name that meets the requirements of Panther Lake. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84536 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/brya: Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for vellSubrata Banik
Enable the SOC_INTEL_COMMON_BASECODE_RAMTOP Kconfig option for the google/vell mainboard. This option ensures improving the boot time on google/vell by 40ms in an average. BUG=b:352330495 TEST=Able to reduced google/vell boot time by 40ms. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iedfd346c62b1ac79796042dd3569d846007b8f10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>