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2024-03-12soc/intel/xeon_sp: Create CXL domainsShuo Liu
SPR CXL IIO stack is divided into 2 PCI domains. The 1st domain is a PCI domain with single bus number and PCIe RCiEPs (Root Complex Integrated End Points) on it. The 2nd domain is a CXL domain with remaining buses for CXL 1.0/1.1 end points and possible SR-IOV (Single Root IO Virtualizaton) VFs (Virtual Function) if any. TEST=intel/archercity CRB P.S. The SUT is not with CXL cards however we hope this refactor could be integrated first as an improvement of the design. Change-Id: I643bcfbae7b6e8cfe11c147cc89374bc6b4d5a80 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81099 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-11mb/google/brya: Create nova variantDavid Wu
Create the nova variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:328711879 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_NOVA Change-Id: Ie1cee43f0e2545288130bcc5152075603695c395 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-03-11vc/amd/opensil/stub: add stub MPIO driverFelix Held
Add a stub MPIO chip driver to the openSIL stub code, so that the devicetree entries needed for the MPIO chip can already be added to the mainboard's devicetree files. This driver won't do anything, but still allows the register settings in the devicetree to be set to make switching over to the actual openSIL code and the corresponding glue code easier. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib4f5c232859b9abcd10bfa5c21e2f2c3a70b4b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/81100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-09drivers/intel/fsp2_0: Perform MP init post FSP-MultiPhase SI InitJeremy Compostella
FSP can also make use of Multi-Processor services during its multi-phase stages. If `USE_INTEL_FSP_MP_INIT' is set and `USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI' unset coreboot cannot take MP ownership as FSP-S may still use EDK2 MP services concurrently. TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec92 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80691 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09arch/riscv: Remove typedefsMaximilian Brune
typedefs violate our coding-style Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Id51eda53b6b53ed2cc66c0339c03c855c12c1bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81124 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-09soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-caseJeremy Compostella
Commit 829e8e65b939 ("soc/intel: Use common codeflow for MP init") brokes `USE_INTEL_FSP_MP_INIT' by making `init_cpus' function static. This function needs to be accessible from src/drivers/intel/fsp2_0/fsp_mpinit.c. TEST=Verified on Meteor Lake rex board Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09soc/intel/alderlake: Add Raptor Lake System Agent Device IDsLean Sheng Tan
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09soc/intel/xeon_sp: Further share domain creation logics in Xeon-SPShuo Liu
With this patch, all domain creation logics are moved into the scope of attach_iio_stack/chip_common.c for the ease of maintenance and future SoC integration where the domain creation process for specific stack types might be overridden. TEST=intel/archercity CRB 1. Boot to CentOS 9 Stream Cloud. 2. Compare PCIe enumeration and ACPI table generation logs before and and after this patch, no changes. Change-Id: If06bb5ff41b5f04cef766cf29d38369c6022da79 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81098 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09drivers/spi: Add GD25LR256E supportMartin Roth
Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id405ed990101a1ceda5e09c6db835f8302047f5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/81125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09mb/google/brya/var/xol: Disable unused controllersSeunghwan Kim
Disable unused controllers in overridetree.cb by referring to xol proto2 schematics. Enabling unused controllers blocks entering s0ix. - I2C3 - SATA - PCIE RP8 - PCIE RP9 - GSPI1 BUG=b:328318578 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I1be7caf8234c32406aa2cff8fc7fe9fa39b16d89 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81105 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brya/var/xol: Update psys_pmax value to 122WSeunghwan Kim
Update psys_pmax value to 122 from 145. This value is from internal power team. BUG=None BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I8bc58343d5736e2457db006972dc229e16d3fe59 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81104 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-09mb/google/brya/var/xol: Configure Acoustic noise mitigationSeunghwan Kim
Enable Acoustic noise mitigation for xol. The setting values are from internal power team. - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=None TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I6165ae6ca73d1467a1d2cc7bd545298bd4c2f54f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81103 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-09arch/riscv: Add SMP support for exception handlerXiang Wang
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68841 Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-09mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine typeFelix Held
Explicitly assign the 'PCIE' value to the 'type' field of the corresponding MPIO chips in the devicetree. Since the mpio_type enum element 'PCIE' has the value 0, this won't change the behavior, but explicitly assigning this makes this easier to understand. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/81095 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-09soc/intel/alderlake: Remove the guard for CnviWifiCoreSean Rhodes
The CnviWifiCore UPD exists for ADL (version 4263) and RPL (version 4415). Remove the guard so it is set correctly. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9943ee43a442a43d75e78d1551e46dcea39db357 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81079 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-09mb/google/brox: Enable Wake on WLAN for SKU1Ashish Kumar Mishra
For SKU1, wake pin is WLAN_PCIE_WAKE_ODL. Update gpio config and corresponding ACPI for WoWLAN. BUG=b:327379404 BRANCH=None TEST=Boot image on SKU1 and check Wake on WLAN from S0ix. Change-Id: I04c35da2c9ac57cafdf7f7a35d83ab2e7a05fe4a Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2024-03-09cpu/x86/smm: Set up page tables in safe SMRAMArthur Heymans
Relying on page tables being in RO flash is not safe in every setup, therefore set up some page tables in SMRAM that the permanent smihandler can use. Tested on QEMU. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Icb3086abd577b9abb9966dd910a264a873ace4ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/80336 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-08drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 supportJeremy Compostella
Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-External-Architecture-Specification.pdf TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2024-03-08drivers/intel/fsp2_0: Add "silicon" to the multiphase callback nameJeremy Compostella
The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-08vc/intel/fsp/mtl: Update header files from 3471_85 to 3471_91Ronak Kanabar
Update header files for FSP for Meteor Lake platform to version 3471_91, previous version being 3471_85. FSPM: 1. Address offset changes BUG=b:327688959 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I5a71232018dfefec63b0a83d1e87717e238a4a0a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80782 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp/spr: Fix IOAT resourcesPatrick Rudolph
Do not generate empty mem32 resources for CPMx or HQMx stacks. Switch existing arguments to make sure that base is bigger than limit to indicate that the resource is invalid. Change-Id: I679563e97c33c7ee35d402674972e55f521eafa8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80793 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp: Share numa.c among Xeon-SP platformsShuo Liu
NUMA will be supported by SPR and future generations. TEST=intel/archercity CRB Change-Id: I0d494f8e560059d9c8d5338cef9a6ffe34e59e26 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-07soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platformsJincheng Li
TEST=intel/archercity CRB Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81041 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-07soc/intel/xeon_sp: Add memory type check utilsShuo Liu
FSP memory type representations change across Xeon-SP SoCs. This patch adds type check utils to abstract the differences. TEST=intel/archercity CRB Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-06arch/riscv: Makefile.mk: Fix incorrect config variableRonald G Minnich
ARCH_RISCV_PMP should be CONFIG_ARCH_RISCV_PMP. Rename it. Change-Id: I2a22acae5cd9f30e01c491653bf7fc7b7765d815 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81086 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-06vc/amd/opensil/genoa_poc/memmap: use GiB defineFelix Held
Use the GiB define to make the 4 GiB boundary used in some places in the code a bit easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81877a5d293c883d2e31bdb18ae3b22b8a44e62f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-03-06vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gbFelix Held
Use get_top_of_mem_below_4gb instead of open-coding the functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5885e9ad89ed9f0aa657c56804e98c352267267f Reviewed-on: https://review.coreboot.org/c/coreboot/+/81092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-03-06soc/intel/xeon_sp: Add ACPI namesPatrick Rudolph
Set the unused 'name' property of the domain device and store the ACPI name. Every IIO stack can have multiple domain devices, each owning a subset of the available bus range within the stack. The name will be used in future changes to generate ACPI names in SSDT code generation. It can also be used to identify the domain type by looking at the first two characters of the name. Change-Id: Ic4cc81d198fb88300394055682a3954bf22db570 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80792 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-06mb/google/nissa/var/glassway: Tune eMMC DLL valuesDaniel Peng
Update eMMC DLL values to improve initialization reliability. BUG=b:327123701 TEST=Improve reboot on MB with eMMC smoothly. Change-Id: Ice9ee217acf7dc6e3e704bc82529e0b9a8faf184 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80779 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Yang <simon1.yang@intel.com>
2024-03-06mb/sifive/sifive-unmatched: add support for spi1 x4 modeRonald G Minnich
Tested on an unmatched, both SPI1 x1 and x4 work now. Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel: Add definition of D0 stepping for TigerLake HaloAlicja Michalska
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E portsAlicja Michalska
ACPI _PRT method was missing from PEG (SoC PCI-E) links, resulting in OS complaining about interrupt routing. 'pcieport 0000:00:06.0: can't derive routing for PCI INT A' 'nvme 0000:04:00.0: PCI INT A: not connected' 'Interrupt: pin A routed to IRQ -2147483648' TEST=Boot Linux and Windows 10 on TGL-H platform with PEG0/PEG1 populated with PCI-E devices - Radeon RX 7800XT and Kingston KC3000 NVME SSD. Check logs and stability while running 3D application and disk benchmark at the same time. Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80848 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-05soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SPShuo Liu
Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer to reduce the dependency. TEST=intel/archercity CRB Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05mb/google/oak: Don't build the ChromeEC codebase by defaultMartin Roth
Currently, the oak boards are the only boards that build the ChromeEC by default as a part of the coreboot build. As a part of replacing the chromeec submodule with a different build mechanism, disable this default. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81023 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-03-05drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bugArthur Heymans
Starting with Intel CPX there is a bug in the reference code during the Pipe init. This code synchronises the CAR between sockets in FSP-M. This code implicitly assumes that the FSP heap is right above the RC heap, where both of them are located at the bottom part of CAR. Work around this issue by making that implicit assumption done in FSP explicit in the coreboot linker script and allocation. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80579 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05lib/program.ld: Make (NOLOAD) and to_load more explicitArthur Heymans
(NOLOAD) indicates that the section occupies no space in the file, but does take up space in memory during process execution. It's typically used for bss sections which contain uninitialized global/static variables. to_load makes sure the section is part of the program headers. This is needed for instance with relocatable stages to know how much memory the program will use. Although the BFD linker makes some good guesses making this a NOOP, other linkers like LLD need to mark these sections more explicitly. Change-Id: Ic14543ba580abe7a34c69bba714eae8cce504977 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80803 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-03-05mb/emulation/qemu-riscv: Change to -bios optionMaximilian Brune
This changes the virt target so that it can be run with the -bios option and a pflash backend for the flash. QEMU can now be run as follows: qemu -M virt -m 1G -nographic -bios build/coreboot.rom \ -drive if=pflash,file=./build/coreboot.rom,format=raw coreboot will start in DRAM, but still have a flash to put CBFS onto and to load subsequent stages and payload from. Tested bootflow: coreboot -> OpenSBI -> Linux -> u-root Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-05mb/asus/p8x7x-series: Revert to native max_mem_clock_mhz of 800Keith Hui
The setting was reduced to 666 for native raminit in commit 7039edd2da30 (SNB+MRC boards: Migrate MRC settings to devicetree) based on boot test results at the time. With more changes merged, additional native raminit tests were done on p8z77-m. It is now possible for previously failing memory configurations to operate at full speed. This, combined with multiple reports on gerrit that this family does work at 800, warrants returning the setting to what it was. Change-Id: I1fbe9c8d076fcd633f71424d60585681c40677c4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79726 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05Revert "vc/intel/edk2: Remove edk2-stable202111 support"Ronak Kanabar
This reverts commit b5f6320c694766d10023fe8f5183c9c143441b2b. ADL-N FSP uses 202111 Edk2. There are structure definition changes between 202005 and 202111. One of change is in FSP_INFO_HEADER structure. This patch is to bring back support of edk2-stable202111. BUG=b:296433836 TEST=Able to build google/crassk. Change-Id: Id1d3e2c5b368a479e637f3ab3d18e242607849ed Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-05ec/google/chromeec: Enclose Kconfig in 'if/endif' blockMartin Roth
Instead of having things depend on EC_GOOGLE_CHROMEEC, just put an if/ endif block around the configs. The 'source' line stays outside of the if block because the source always happens, even if it's inside an if/endif block. Each of the sub-Kconfigs here already has an if/endif block surrounding the contents. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If88ba7d36ae04d879332037292c5cf9a3c8c3cab Reviewed-on: https://review.coreboot.org/c/coreboot/+/81025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-03-05mb/google/brya/var/xol: Add VGPIO configurations for PEG60Seunghwan Kim
Add VGPIO configurations for NVMe on PEG60. BUG=b:326481458, b:372086400 BRANCH=firmware-brya-14505.B TEST=Verified DUT could detect NVMe. Install ChromeOS into NVMe and boot from it. Change-Id: I5520dc2a4bf6e788701a774674d223b7e8ad5b44 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-05mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanelYunlong Jia
Add FW_CONFIG probe to separate touch panel settings. TOUCH_PANEL_ENABLE/TOUCH_PANEL_DISABLE Use different gpio tables based on the value of TOUCH_PANEL. BUG=b:325987249 TEST=emerge-nissa coreboot and run in DUT Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kyle Lin <kylelinck@google.com>
2024-03-05soc/intel/xeon_sp: Drop unused helper functionsPatrick Rudolph
Change-Id: Ib319643f6b0b91d8c5854da531e035d333f04d75 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80143 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05soc/intel/xeon_sp: Drop code to locate the UBOX busPatrick Rudolph
Drop the code to retrieve the UBOX bus numbers. Only keep a minial function that works when called from socket0 to retrieve the bus for UBOX(1). Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80102 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-03-05soc/intel/xeon_sp/util: Enhance lock_pam0123Patrick Rudolph
- Only compile code in ramstage - Lock PAM on all sockets - Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-03-05soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSIONSubrata Banik
This patch marks CONFIG_SOC_INTEL_CSE_RW_VERSION as deprecated, as future platforms will automatically determine the CSE RW version using CSE RW partition. BUG=b:327842062 TEST=CSE RW update successful on Screebo. Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80924 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2024-03-05vc/google/chromeos: Implement dynamic ChromeOS boot logo selectionSubrata Banik
* Introduces logic to display context-specific boot splash logos. * Logo selection considers: * Chromebook-Plus hardware compliance (using factory_config). * VPD-based product segmentation (soft-branded vs. regular chromebook). * Default Chromebook logo as fallback for regular Chromebook. This patch fixes the problem where existing logic was unable to pick correct ChromeOS boot splash logo based on the product segmentation. Relation between product segment and boot splash screen: 1. Chromebook-Plus Hard-branded device: Renders "cb_plus_logo.bmp" logo 2. Chromebook-Plus Soft-branded device: Renders "cb_plus_logo.bmp" logo 3. Regular Chromebook device: Renders "cb_logo.bmp" BUG=b:324107408 TEST=Verified logo selection based on compliance and product requirements. Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-03-05drivers/vpd: Add vpd_get_feature_level() APISubrata Banik
This patch introduces the vpd_get_feature_level() API to specifically extract the "feature_level" field from the "feature_device_info" VPD key. This is used to distinguish between Chromebook-Plus and regular Chromebook devices. The previous vpd_get_feature_device_info() API is removed as vpd_get_feature_level() is enough to find VPD and extract the data. Note: The new API decodes the base64-encoded "feature_device_info" VPD data. BUG=b:324107408 TEST=Able to build and boot google/rex0. Change-Id: I76fc220ed792abdfefb0b1a37873b5b828bfdda8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80805 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-05mb/google/brya/var/dochi: Add wifi sar tableMorris Hsu
Add wifi sar table for dochi BUG=b:326137130 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Iaf90756eb318bef1ffcda9368a976c0ca209a100 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-04riscv/mb/qemu: fix DRAM probingPhilipp Hug
Current version of qemu raise an exception when accessing invalid memory. Modify the probing code to temporary redirect the exception handler like on ARM platform. Also move saving of the stack frame out to trap_util.S to have all at the same place for a future rewrite. TEST=boots to ramstage Change-Id: I25860f688c7546714f6fdbce8c8f96da6400813c Signed-off-by: Philipp Hug <philipp@hug.cx> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36486 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/google/guybrush: turn off SD ASPM L1.1/L1.2JasonNien
Turn off SD ASPM L1.1/L1.2 as w/a for wlan DMA resume failure We completed 4 runs for each of the 2 tests - power_idle and power_VideoCall. Here are the averages for both the tests: L1ss disabled SD plugged power idle test: 735.3875 L1ss enabled SD plugged power idle test: 737.2335 L1ss disabled SD plugged power video test: 333.29325 L1ss enabled SD plugged power video test: 333.442 BUG=b:254382832 TEST=test pass over 10k cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80237 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04lib/ramdetect: Limit probe size to function argumentArthur Heymans
This avoids probing above the function argument where other things than DRAM could be mapped. Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-03-04arch/x86/Kconfig: Deduplicate ARCH_SUPPORTS_CLANG selectionElyes Haouas
Change-Id: Iced69e0bce345748a43eb1c14bf17a683e26ba60 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81020 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-04mb/dell: Add OptiPlex 7020/9020 portMate Kukri
The OptiPlex 7020 and 9020 use physically identical motherboards. WARNING: PWM fan control doesn't work via the EC and the fan runs at a fixed speed. There is likely more EC init to reverse engineer. Each model comes in the following form factors: - 7020: SFF, MT - 9020: USFF (not currently supported), SFF, MT (7020 SFF) Boots Linux and Windows 10: - Tested with an i3-4160 and i5-4460 - DRAM init works using the MRC (4G, 4G+4G) - iGPU init works using libgfxinit (VGA, 2x DP) - PCIe 16x: tested, ok - PCIe 4x: tested, ok - All USB2 and USB3 ports work - SMSC SCH5555 Super I/O: serial works, PS/2 untested - Audio: back and front output works, internal speaker works, mic inputs untested - Ethernet: tested, works (9020 MT) - Tested by Michael Büchler (thanks for the overridetree) Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55232 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-03-04nb/haswell: Disable iGPU when dGPU is usedLeah Rowe
This is usually is handled by Haswell mrc.bin, disabling VGA decode on the iGPU when a dGPU is installed. However, Broadwell mrc.bin does not, so the iGPU and dGPU are both enabled. This patch disables legacy VGA cycles for iGPU, under such conditions. It has been tested on Broadwell mrc.bin when using a graphics card on Dell OptiPlex 9020 SFF (currently under review at this time of writing, submitted by Mate Kukri). This patch has also been tested when Haswell mrc.bin is used, and there are seemingly no breaking changes caused by it. Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b Signed-off-by: Leah Rowe <info@minifree.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-03-04mb/google/brya: Enable CSE telemetry for ADL-NKapil Porwal
BUG=none TEST=Verify CSE telemetry data in boot time data on Yahiko. Before: ``` yahiko-rev9 ~ # cbmem -t 71 entries total: 0:1st timestamp 197,583 (0) ``` After: ``` yahiko-rev9 ~ # cbmem -t 76 entries total: 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 49,000 945:CSE started to handle ICC configuration 49,000 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 51,000 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 168,000 (117,000) 0:1st timestamp 195,861 (27,861) ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3f90d0462cb766655bf8e59a90bc550ceefb2256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79768 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/system76/adl,rpl: Add 50ms timeout for PCIe 3.0 RPsTim Crawford
The FSP may fail to detect PCIe 4.0 devices in PCIe 3.0 slots on S3 resume. This issue has only been experienced on lemp12, and only with Samsung drives, but implies it could happen on other systems or with other drives as well. A timeout of 50ms is arbitrarily chosen. Tested on lemp12 with Samsung 980 PRO (FW: 3B2QGXA7, 5B2QGXA7) and 990 PRO (FW: 4B2QJXD7) drives. Change-Id: I4f44fc429c52e407b7566d6bb6dd31b2cf85c48d Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80756 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/system76/adl: Remove duplicate PchHdaAudioLinkHdaEnableTim Crawford
This UPD is hooked up in devicetree since commit 854bd492fcfa ("mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree"). As these boards were in development when the change happened, they still had the UPD set via romstage. Remove them now so they are only set in devicetree. Change-Id: I393e2c7b0134a31feae20f8992d7fd447ff7ee59 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80755 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-04mb/system76/adl,rpl: Enable PchHdaSdiEnableTim Crawford
Commit 4a58d14506ef ("soc/intel/alderlake: Hook up UPD PchHdaSdiEnable") and commit 2d482386182e ("soc/intel/alderlake: Set PchHdaSdiEnable for Alder Lake") hooked up this UPD in devicetree, causing the FSP default to be overridden (now disabled by default). Enable SDI to fix the following error: [DEBUG] PCI: 00:00:1f.3 init [DEBUG] azalia_audio: base = 0xbfbcc000 [DEBUG] azalia_audio: No codec! [DEBUG] PCI: 00:00:1f.3 init finished in 5 msecs Tested on gaze17-3050: Speaker output works again. Change-Id: Iceac1faec939ce9eea68c335929f96ec5f2bd132 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2024-03-04mb/system76/rpl: Add TCSS ACPI for all boardsDan Campbell
Fixes ACPI errors about missing methods: ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TDM0], AE_NOT_FOUND (20230628/dswload2-162) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010) ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0.TRP0], AE_NOT_FOUND (20230628/dswload2-162) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220) Tested on lemp12: ACPI errors in dmesg are gone. Change-Id: I9b79cb04f57a27af2a6c8f3118e573f7ac0041e5 Signed-off-by: Dan Campbell <dan@compiledworks.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80791 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/google/brox: Update Verbtable for beep functionalitypoornima tom
For boot beep functionality, relevant register values are required to be updated. BUG=b:324528901 BRANCH=None TEST=Build & verified Boot Beep functionality on Brox Change-Id: If236c8ac173a279db676af412377fa4e4122c1cd Signed-off-by: poornima tom <poornima.tom@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80416 Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entrySubrata Banik
This patch automates the process of determining the CSE RW version used for the CBFS entry, eliminating the need for manual configuration in CONFIG_SOC_INTEL_CSE_RW_VERSION. How to get CSE RW Version: 1. Open CSE RW file as per CONFIG_SOC_INTEL_CSE_RW_FILE 2. Read offset 16 (0x10) to know the CSE version 3. Format: - CSE_VERSION_MAJOR : offset 16-17 - CSE_VERSION_MINOR : offset 18-19 - CSE_VERSION_HOTFIX: offset 20-21 - CSE_VERSION_HOTFIX: offset 22-23 Benefits: - Removes error-prone manual version updates. - Prevents boot loops due to mismatched CSE RW versions (actual vs config) - Eliminates the need for SKU-specific CSE version limitations. BUG=b:327842062 TEST=CSE RW update successful on Screebo with this patch. Example Debug Output: [DEBUG] cse_lite: RO version = 18.0.5.2066 [DEBUG] cse_lite: RW version = 18.0.5.2107 Change-Id: I0165d81b0e4b38e0e097956f250bb7484d774145 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80923 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04mb/google/brya/var/xol: Update NVMe clock source index to 0Seunghwan Kim
Change ClkSrc index for NVME to 0 from 1 by referring to proto2 schematics. BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80768 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-03Revert "Revert "mb/sifive: Add Hifive Unmatched mainboard""ron minnich
This reverts commit ec7b48076009cfe82e5ee91050f5fc66c4850193. Reason for revert: <Reland> I made the commit out of order with the fu740 commit; that's now merged so there should be no problem. Signed-off-by: ron minnich <rminnich@gmail.com> Change-Id: I2fb8c2e0a7fcd5f26f4a004e0949332b108b6fcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/81052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-03soc/sifive/fu740: Add FU740 SOCMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-02Revert "mb/sifive: Add Hifive Unmatched mainboard"Martin L Roth
This reverts commit e26bcaefbeb1d64cf2a78ad54e0f6ad4affab086. Reason for revert: Patch submitted out of order. Change-Id: I71c024b13411c4e0c9b4d6358f9cd31c57bbbfe2 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-03-02mb/sifive: Add Hifive Unmatched mainboardMaximilian Brune
working: Linux v6.3.5 poweroff via Linux PMIC driver UART console output SPI -> SDCARD I2C -> PMIC 16 GB LPDDR4 memory VSC8541XMV-02 (gigabit ethernet PHY) PCIe x16 Slot M.2 NVMe Slot MSEL: only '1100' has been tested untested: M.2 WiFi/Bluetooth Slot tested bootflow: ZSBL -> coreboot --FDT-> Linuxboot -> uroot --kexec-> ubuntu defconfig used: CONFIG_VENDOR_SIFIVE=y CONFIG_BOARD_SIFIVE_HIFIVE_UNMATCHED=y CONFIG_PAYLOAD_NONE=n CONFIG_PAYLOAD_ELF=y CONFIG_PAYLOAD_FILE="[path-to-linux]/arch/riscv/boot/Image" CONFIG_PAYLOAD_IS_FLAT_BINARY=y CONFIG_PAYLOAD_OPTIONS="-l 0x82000000 -e 0x82000000" CONFIG_COMPRESSED_PAYLOAD_LZMA=y uroot kexec command: kexec -d --cmdline "console=ttySIF0 root=/dev/mmcblk0p1 debug" \ --initrd /mnt/boot/initrd.img-6.5.0-9-generic \ /mnt/boot/vmlinuz-6.5.0-9-generic Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ife0afdce89d5a1a1b936c30c8027f1bc191b8c53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2024-03-02mb/google/nissa/var/glassway: Select drivers for gpio-keys and GL9750Daniel Peng
Add 2 configuration on Kconfig for glassway. - DRIVERS_GENERIC_GPIO_KEYS - DRIVERS_GENESYSLOGIC_GL9750 BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: Id7e358d2f472cd435d2828f6256f5ee91dfb8ef6 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80766 Reviewed-by: Shawn Ku <shawnku@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-01drivers/intel/gma: Allow SPARK function with side effectsNico Huber
Explicitly specifying the aspect `Side_Effects' is necessary for GCC toolchains from 14.0 on. As older toolchains don't know the aspect, we have to silence a warning about it, though. Change-Id: I1eb879f57437587dc11d879fcc4042a70d384786 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80616 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Thomas Heijligen <src@posteo.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-01acpi/acpigen_pci_root_resource_producer: zero-pad rangesFelix Held
Print bus number, IO and MMIO ranges as fixed length zero-padded hexadecimal numbers. The bus numbers are 1 byte long, the IO range values are 2 bytes long and the MMIO range values can be up to 8 bytes long, so use '%02x', '%04llx' and '%016llx' in the corresponding parts of the format string. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Iea45094a3988d57f8640a98fd7214d33ed1d7ccb Reviewed-on: https://review.coreboot.org/c/coreboot/+/80804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-03-01superio/acpi: Add SUPERIO_PNP_NO_DIS to support always active LDNsMichał Żygowski
Some LDNs do not implement the activate bit at all, e.g. ITE GPIO LDNs are an example where the LDN is always active. The pnp_generic.asl can be used to describe the GPIO LDN resources configured by the platform, however the register 0x30 is always 0 for these LDNs, so OS will not claim the reported resource for the GPIO device, because _STA will return inactive LDN. Add SUPERIO_PNP_NO_DIS macro to generate _STA method returning an always active LDN and skip _DIS generation. Define the SUPERIO_PNP_NO_DIS for SIOs which use the pnp_generic.asl preserving the previous states, except the ITE GPIO LDNs. Change-Id: Ieb827fdffe7660b875cba6ca99b0560b4cab66b4 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80496 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-01drivers/mrc_cache: Deselect MRC_CACHE_USING_MRC_VERSION by defaultJincheng Li
EDK2 version binding is irrelevant for MRC_CACHE_USING_MRC_VERSION as this is SoC FSP choice to enable/disable this feature. So deselect the option and leave it to SoC codes to enable it depending on needs. Change-Id: I84fdcfbf3c833a7ccb259a1a1d4be0bcfe291dc3 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80693 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-01soc/intel/meteorlake: Select MRC_CACHE_USING_MRC_VERSIONJincheng Li
MRC_CACHE_USING_MRC_VERSION is irrelevant to the EDK2 binding version and should not be enabled under specific version conditions, so select this at SoC level. Change-Id: I10594df7c8fdc5cfe9b68975e01ae65859735544 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80728 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-03-01mb/google/nissa/var/glassway: Add GPIO tableDaniel Peng
Refer to the reference board of nivviks, and update GPIO settings via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf. BUG=b:319071869 BRANCH=firmware-nissa-15217.B TEST=Local build successfully and boot to OOBE normally. Change-Id: I0de743746160c6eb081cb9a061ac1703b01ba5b4 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-03-01mb/google/link: Use automatic fan controlMatt DeVillier
Several users complained of link's fan not running at all, particularly when using ChromeOS Flex. Enabling auto fan control at boot/s3 resume resolved the issue for them. Change-Id: I8f0db6b6c94fac2e0dcb580be0f6df839780c38c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80713 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-01ec/chromeec: Enable auto fan control on startupMatt DeVillier
Several older ChromeOS boards have issues with fan control on cold boot and/or on S3 resume, so add functionality to allow those boards to programmatically enable auto fan control. TEST=build/boot google/link, verify fan ramps up/down accordingly with CPU load. Change-Id: I08a8562531f8af0c71230477d0221d536443f096 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-02-29device/pnp_device: fix log levels for unassigned resource messagesFelix Held
Commit a662777b6f57 ("pnp_device: don't treat missing PNP_MSC devicetree entry as error") lowered the log level for every resource without the assigned bit set except for the IRQ0 and IRQ1 PNP device resources. Commit df84fff80fed ("device/pnp_device: Demote unassigned resource printk to NOTICE") lowered the log level for the IRQ0 and IRQ1 PNP device resources to a lower log level than for the other warnings that are less likely a problem. Fix this regression by using the BIOS_NOTICE log level for all PNP resources that don't have the IORESOURCE_ASSIGNED bit set. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I232e60ef7ae672e18cc1837b8e6a0427d01c142b Reviewed-on: https://review.coreboot.org/c/coreboot/+/80774 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29mb/google/skyrim/var/skyrim: Hide fingerprint reader from Windows OSMatt DeVillier
No Windows driver exists or is needed, so hide to prevent an unknown device from being listed in Windows Device Manager. Same change was made for frostflow variant previously. TEST=build/boot Win11 on skyrim, verify unknown device for the fingerprint reader no longer present. Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80711 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29soc/amd: move common pci_domain_fill_ssdt implementation to acpi/Felix Held
Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt implementation doesn't contain any AMD-specific code and can also be used by other SoCs. So factor it out, move the implementation to src/acpi/acpigen_pci_root_resource_producer.c, and rename it to pci_domain_fill_ssdt. When a SoC now assigns pci_domain_fill_ssdt to its domain operation's acpi_fill_ssdt function pointer, the PCI domain resource producer information will be added to the SSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80464 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29mb/amd/birman_plus: Add glinda SOC option for Birman+Anand Vaikar
Change-Id: I1efeb7cf1dca31e2a7e17f483f8882925b55e7ea Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2024-02-29lib/rtc: Fix off-by-one error in February day count in leap yearMichał Żygowski
The month argument passed to rtc_month_days is 0-based, not 1-based. This results in the RTC being reverted to the build date constantly on 29th February 2024. Change-Id: If451e3e3471fef0d429e255cf297050a525ca1a2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80790 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2024-02-29mb/lenovo: Add ThinkCentre M700/M900 Tiny board (Skylake/Kaby Lake)Michał Kopeć
The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151 processors. M700 comes with B150 chipset, M900 comes with Q170 and is vPro capable. There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled in vendor FW, but for now it's not used here. LPSS UART for debugging is available on pins 17,18 on the underside of the mainboard, but it is not enabled by default. Tested unit is M900 with i5-6500T. Boots to Fedora 38 w/ kernel 6.5.5 and Windows 11. Tested and working: - Serial port (via optional module) - Rear DisplayPort connectors - Graphics w/ libgfxinit - Ethernet - SATA - NVMe - Internal speaker, front combo jack, rear line-out - Discrete TPM 1.2 - USB ports (Port 1 untested, apparently broken on my unit) - M.2 2230 Wi-Fi slot (needs ASPM L1s disabled) - S3 suspend - ME disable via NVRAM setting Untested: - Front mic input - Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29mb/clevo/tgl-u: hda_verbs: correct vendor value commentsMichael Niewöhner
The vendor vendor values for the hda verbs´ location field were decoded wrong because of relying on the wrong bit shift value in `device/azalia_device.h`. Since this was fixed now, correct the comments. Change-Id: I45b1d09d5a11b357ac2a20ef448ea642540cdc99 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80720 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29mainboard/lenovo: Add ThinkCentre M710s (Skylake)Nicholas Sudsgaard
The processor may be a Pentium or 6/7th generation Core i3/i5/i7. This port was tested on an i5-7400. Working: - Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads: - SeaBIOS - TianoCore EDK 2 - Internal flashing (from coreboot) - PEG - PCIe - SATA - M.2 SSD - M.2 WLAN (+ Bluetooth) - LAN - USB - Memory card reader - CPU fan - VGA (DP bridge) - Display ports - Audio (output) - COM1 - TPM Not Working: - SuperIO related things - Power button LED - PCIe clock related things and AER issues (LiveCD) - Some drm issue when using EDK 2 and libgfxinit (LiveCD) - ME cleaner Untested: - Audio (input) Won't Test: - COM2 header - LPT header - PS/2 keyboard and mouse Thanks to Nico Huber and everyone else on the IRC for helping me write my first port! Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80343 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29include/device/azalia_device.h: Merge location1 and location2Nicholas Sudsgaard
This changes the location to be expressed as a combination of ORs. This allows aliases for special locations. For example, `AZALIA_REAR_PANEL` is easier to read than `AZALIA_EXTERNAL_PRIMARY_CHASSIS, AZALIA_SPECIAL7`. References: - Intel High Definition Audio Specification, rev. 1.0a, page 180, Table 110. Location. Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29include/device: Merge enums from azalia_device.h and azalia.hNicholas Sudsgaard
We were keeping 2 copies of the same thing (albeit there were some slight differences). As azalia_device.h is used much more in the codebase this was kept as the base and then some of the nice features of azalia.h were incorporated. The significant changes are: - All enum names now use the `AZALIA_` prefix. This also drops the AzaliaPinConfiguration enum as it was never used since added in 2013. Change-Id: Ie874b083a18963679981a9cd2b25d123890d628e Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80695 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-02-29include/device/azalia_device.h: Correct location2 shift to 28 bitsNicholas Sudsgaard
The location is specified to be in range of 29:24, which is further divided into upper bits (location2) [5:4] and lower bits (location1) [3:0]. This also corrects the resulting values of clevo/l140mu. References: - Intel High Definition Audio Specification, rev. 1.0a, page 178, Figure 74. Configuration Data Structure. TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the same binary. Change-Id: Ia5a3431b70783cb88e866d0fd8ea5530100f3d52 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80727 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29mb/qemu/fw_cfg: Support using DMA to select fw_cfg fileAlper Nebi Yasak
Commit 8dc95ddbd4a935 ("emulation/qemu-i440fx: use fw_cfg_dma for fw_cfg_read") adds DMA support to interface with the QEMU firmware configuration device, and uses it to read from the "files" exposed by the device. However, the file selection step still uses port-based IO. Use DMA for fw_cfg file selection when possible, as a step towards porting this driver to other architectures. Change-Id: I46f9915e6df04d371c7084815f16034c7e9879d4 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29Revert "lib: Explicitly declare heap as NOLOAD"Subrata Banik
This reverts commit 99bf23c9e73c7492ee9d5c1f208bceedf3ff7cb5. This patch causes the boot regression at depthcharge with below error signature. Able to boot to OS after reverting this patch. ``` Starting depthcharge on Rex... WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime! WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime! fw_config match found: AUDIO=MAX98360_ALC5682I_I2S Looking for NVMe Controller 0x30069a60 @ 00:06:00 libc/lp_vboot.c:25 vboot_get_context(): vboot workbuf could not be initialized, error: 0x10080030 Ready for GDB connection. ``` Change-Id: I8d49e2dc49cd2935a9d8023c989869ec9558039e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80775 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28soc/intel/xeon_sp/util: Locate PCU by PCI device IDPatrick Rudolph
Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: I1dcad4ba3fbc0295d74e1bf832cce95f014fd7bf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80095 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28soc/intel/xeon_sp: Locate PCU by PCI device IDPatrick Rudolph
Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support without any further code modifications, since the correct PCI segment will be stored in the devicetree. Intel Document-ID: 735086 Intel Document-ID: 612246 Tested: On SPR 4S all PCU on all 4 sockets could be found and locked. Change-Id: I06694715cba76b101165f1cef66d161b0f896b26 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80093 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28cpu/x86/(sipi|smm): Pass on CR3 from ramstageArthur Heymans
To allow for more flexibility like generating page tables at runtime or page tables that are part of the ramstage, add a parameter to sipi_vector.S and smm_stub.S so that APs use the same page tables as the BSP during their initialization. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80335 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-28drivers/vpd: Add API to read "feature_device_info" VPDSubrata Banik
This patch introduces an API for reading "feature_device_info" VPD data. This information is essential for correctly differentiating ChromeOS product segments (e.g., Chromebook-Plus vs. standard Chromebook models). BUG=b:324107408 TEST=Build and boot successful on google/yahiko with this change. Change-Id: I8d49e2dc49cd2935a9d8023c989869eb9558039d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-02-28mb/google/brya/var/xol: Add storage option in FW_CONFIGSeunghwan Kim
Add STORAGE config in FW_CONFIG to support NVME sku. - STORAGE_UFS : 0 - STORAGE_NVME: 1 BUG=b:326481458 BRANCH=firmware-brya-14505.B TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: Id8316f643ba9a55319b67431a24a507e92419aa7 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80767 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-02-27soc/intel/tigerlake: Remove IOM Mctp command from TCSS ASLCoolStar
Port fix from Alder Lake to not set/reset IOM MCTP during D3 cold entry or exit. Ports 5008d340033d ("soc/intel/adl: Remove IOM Mctp command from TCSS ASL"): > Recently as part of s0ix hang issue, it was found that sending IOM > MCTP command as part of TCSS D3 Cold enter-exit sequence created an > issue. > We discovered that due to change in hardware sequence, ADL should not > set/reset IOM MCTP during D3 cold entry or exit. This patch removes > the bit setting from ASL file to prevent hang in the system. > This patch also removes obsolete Pcode mailbox communication which > is no longer required for ADL. > BUG=b:220796339 > BRANCH=firmware-brya-14505.B > TEST=Check if hang issue is resolved with the CL and no other > regression > observed > https://review.coreboot.org/c/coreboot/+/62861 Test: build/boot drobit to Win11. Verify TCSS XHCI power management working and USB Root Hub doesn't Code 43 in device manager Change-Id: I40a537fd2b0c821caf282f52aaff1874f54325f1 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80719 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27soc/intel/tigerlake: Fix processor hang while plug unplug of TBT deviceCoolStar
Port 9c348a7b7ea3 ("soc/intel/alderlake: Fix processor hang while plug unplug of TBT device") from Alder Lake to fix a similar issue present on Tiger Lake: > Processor hang is observed while hot plug unplug of TBT device. BIOS > should execute TBT PCIe RP RTD3 flow based on the value of > TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if > BIT30 in TBT FW version is not set. > BUG=b:194880254 > https://review.coreboot.org/c/coreboot/+/56503 Change-Id: Ie5409111d4239be86c0b153f01b4fe5fc6af352c Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80718 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27Kconfig: Make the SEPARATE_ROMSTAGE default configurable in other filesArthur Heymans
This also sets a good default in arch and vboot to have a separate romstage when it makes sense. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I09ab5f8c79917bf93c9d5c9dfd157c652478b186 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80580 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27device/pciexp_device.c: Fix setting Max Payload SizeMichał Żygowski
Current implementation assumes that the endpoint device is connected directly to the PCIe Root Port, which does not always have to be true. In a case where there is a PCIe switch between the endpoint and the root port, the Max Payload Size capability may differ across the devices in the chain and coreboot will not set a correct Max Payload Size. This results in a PCIe device malfunction in pre-OS environment, e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE fails to obtain the DHCP configuration. Fix this by traversing the topology and programming the highest common Max Payload Size in the given PCIe device chain during enumeration. Once finished, the root port has the highest common Max Payload Size supported by all the devices in the chain. So at the end of root port bus scan, propagate the root port's Max Payload Size to all downstream devices to keep Max Payload Size in sync within the whole chain. TEST=Perform successful dhcp command in iPXE on the NIC connected to the PCIe root port via ASMedia ASM1806 PCIe switch and again on the NIC connected directly to the PCIe root port. Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-02-27mb/qemu/fw_cfg: Use fw_cfg_read() to read SMBIOS dataAlper Nebi Yasak
The QEMU firmware configuration driver can help initialize SMBIOS tables using the table data that QEMU provides over the device. While doing so, it reads from the device "file" manually using port-based IO. Use the fw_cfg_read() helper function to read the SMBIOS-related file, so that the driver is easier to port the driver to other architectures. Change-Id: I18e60b8e9de34f2b0ff67af4113beec1d7467329 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80367 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-27mb/qemu/fw_cfg: Fix build when not generating SMBIOS tablesAlper Nebi Yasak
Parts of the QEMU firmware configuration device driver refers to SMBIOS related kconfig values. These depend on GENERATE_SMBIOS_TABLES and are undefined if it isn't enabled, causing a build error. Cover the SMBIOS-related region in this driver with an #if directive checking the necessary config option. This is mostly to help port the driver to non-x86 architectures where support for generating SMBIOS tables isn't there yet. Change-Id: I3ff388d4574eb52686a5dda3dcbc3d64a7ce6f7b Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80366 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 12:16:20 +0000