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2022-03-30mb/google/brya/variants/crota: Add memory config for crotaTerry Chen
Fill in the memory config based on the the schematic by bernadino 14 adl-p 20220112.pdf BUG=b:219891328 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30Revert "mb/google/brya/var/kano: adjust I2C3 speed"David Wu
This reverts commit 65aaccda5910e9c74aaa2a44ea84119d9476c902. Reason: 1. Fix firmware messages show [ERROR] dw_i2c:invalid bus speed 390000 2. Measure DVT I2C3 speed < 400KHz. BUG=b:215095284 TEST=There isn't ERROR messages and verify I2C3 speed < 400KHz. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I5982c82a55710824692b41e263418e4b4d420b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30soc/intel/alderlake: Log CSE RO write protection info for ADLSridhar Siricilla
The patch logs CSE RO's write protection information for Alder Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. TEST=Verify the write protection details on Gimble. Excerpt from Gimble coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30soc/amd/sabrina/makefile: use Sabrina as SoC name in amdfwtool callFelix Held
Now that the amdfwtool support for Sabrina is in place, change the SoC name parameter passed to amdfwtool from Cezanne to Sabrina. The fw.cfg file still points to the Cezanne binaries, but since commit 9cb0a05dfb308323a5b3df1a25fa66b35ecfcdd6 (soc/amd/sabrina: Add prompt for AMDFW_CONFIG_FILE) this can be overridden via the Kconfig config file in the build. As soon as the Sabrina PSP binaries are available in 3rparty/amd_blobs, the fw.cfg file will be updated to use the correct ones for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63189 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30soc/amd/sabrina/makefile: drop PSP_S0I3_RESUME_VERSTAGE handlingFelix Held
The PSP_S0I3_RESUME_VERSTAGE Kconfig symbol is only defined in the Cezanne Kconfig, so drop this from the Sabrina makefile. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9571a302d427981cdf750a1cb3b7f4db9d61a87c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63188 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/google/skyrim: Call espi_switch_to_spi1_padsRaul E Rangel
We are using the second SPI pads for eSPI. BUG=b:226635441 TEST=Build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I43713d7376a28ced2be635668836464ceec46392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63096 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30soc/amd/sabrina: Add espi_switch_to_spi1_padsRaul E Rangel
The way to select the pads has changed from Cezanne. BUG=b:226635441 TEST=Build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I96baf6b9c169ed61d221352b29ac676bca40da21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63095 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30ChromeoS: Retain ACPI CNVS contents on S3 resumeKyösti Mälkki
For platforms without EC_GOOGLE_CHROMEEC S3 resume path always reported ACTIVE_ECFW_RO because acpi_fill_cnvs() and mainboard_chromeos_acpi_generate() were not called. Change-Id: Iea71a51aba7ab1b6966389c17a1e06ccc96ae0e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/guybrush/var/dewatt: add specific SPD hex for dewattChris.Wang
Add the specific SPD hex file for the Samsung memory part with updating the part number into the SPD table. The ABL needs to identify the part by checking SPD data to do the proper tuning. BUG=b:224884904 TEST=Build, validate the SPD data has been applied. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-30commonlib/timestamp_serialized: Add timestamp enum to name mappingJakub Czapiga
Some solutions require readable form of timestamps, which does not contain spaces. Current descriptive timestamp names do not meet this criteria. Also, mapping enums to their text representation allows for quick grepping (use of grep command) to find relevant timestamps in the code. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30commonlib/bsd/helpers: Remove redundancy with libpayload definesJakub Czapiga
Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h Remove redundant defines from libpayload.h and libpayloads' standard headers. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30mb/google/brya/variants/crota: init overridetree for crotaTerry Chen
init overridetree.cb based on the schematic bernadino 14 adl-p 20220112.pdf BUG=b:226315394 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RXFrank Wu
Update the GPP_D12 according to USB_C3_LSX_RX. BUG=b:225081954 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The device can be recognized when it is attached in port3. localhost /sys/bus/thunderbolt/devices # ls 0-0 1-0 1-0:3.1 1-3 domain0 domain1 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30mb/google/cherry: Add PCIe domain support for dojoJianjun Wang
Add override device tree for dojo and add PCIe domain support. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-30mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarloJoey Peng
Add thermal table settings for tarlo which shares the same firmware with taeko BUG=b:215033683 TEST=emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30mb/google/guybrush: Disable EN_SPKR on initYu-Hsuan Hsu
We don't want to enable the speaker on init. It will be enabled while using GPIO AMP codec in depthcharge. BUG=b:223289882 TEST=boot guybrush and verify the devbeep and gpio value in kernel Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147 Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30mb/starlabs/lite: Move Verb Table to variant directorySean Rhodes
Move the verb table to variant directory to allow for different tables for different variants. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30ec/starlabs/merlin: Add GLKR variantSean Rhodes
Add GLKR (N5030) Lite Mk IV variant Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1e17130caa16a605d0d3207d41527df3db6ada81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30ec/starlabs/merlin: Add support for Nuvoton EC'sSean Rhodes
Support was created for the NPCE9m5x series, using version 1.1 of the datasheet. The specific model tested was the NPCE985P/G, on the StarLite Mk IV with version 1.00 of the EC firmware. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30ec/starlabs/merlin: Make EC function names genericSean Rhodes
Rather than using `ite_`, use `ec_` so the same functions can be called for different ECs. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie61af233f731eb47772af1c82c6abdc515bc89cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30ec/starlabs/merlin: Rename ec.c to more specific ite.cSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30drivers/tpm: Force enable long IRQ pulses for Ti50 versions under 0.15.Reka Norman
Only Cr50 versions starting at 0.5.5 support long IRQ pulses, so this feature is enabled based on the value of the board_cfg register (see CB:61722). However, Ti50 versions below 0.0.15 don't support the board_cfg register, and trying to access it will cause I2C errors (see CB:63011). Also, all Ti50 versions only support long IRQ pulses. Therefore, add a workaround to force enable long IRQ pulses for boards using Ti50 versions under 0.0.15, instead of enabling it based on board_cfg. This workaround will be removed once all Ti50 stocks are updated to 0.0.15 or higher. BUG=b:225941781 TEST=Boot nivviks and nereid to OS with Ti50 0.0.14 and check there are none of these I2C errors: [ERROR] I2C stop bit not received [ERROR] cr50_i2c_read: Address write failed [ERROR] cr50_i2c_tis_status: Failed to read status Change-Id: Iaba71461d8ec79e8d6efddbd505339cdf1176485 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63160 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/google/nissa/var/nivviks: Move WWAN power on sequence forwardEric Lai
Move WWAN power on sequence from OS to coreboot. This can save the WWAN initial time about 10S. Another purpose is power resource be removed because we don't power off the LTE in S0ix. BUG=b:223490884 TEST=FM101-GL work as expected. Enumerate time from [ 17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 17.760215] usb 4-2: Product: Fibocom FM101-GL Module [ 17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 17.760224] usb 4-2: SerialNumber: 9c88998f to [ 3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd [ 3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04 [ 3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 4.003813] usb 4-2: Product: Fibocom FM101-GL Module [ 4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc. [ 4.019762] usb 4-2: SerialNumber: 9c88998f Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-30mb/intel/adlrvp: Deselect ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTORSridhar Siricilla
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is locked in the production systems, so the Kconfig is deselected. TEST=Build the coreboot for adlrvp Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-30mb/amd/chausie/port_descriptors: update DDI descriptorsFelix Held
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63163 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/amd/chausie/devicetree: update PCI root portsFelix Held
Only enable the PCIe root ports that have corresponding DXIO descriptors and also update the comments to have them match the actual hardware configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I378c620abb6e52de680669b6edd228874153e399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/amd/chausie/port_descriptors: update DXIO descriptorsFelix Held
Change the DXIO descriptors to match the default PCIe lane mapping on the chausie board. With this configuration and a board-level rework to bypass the EC control of the NVMe SSD power supply rail, this configuration results in the SSD being detected on the root port on bus 0 device 2 function 3 and usable as boot device. This was also validated against the schematics revision B. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/google/brask/variants/moli: update GPIOs for moliRaihow Shi
Follow the Moli GPIO Table_20220324.xlsx to update it. 1.Set A15 as the default value. 2.Set A14, A19 NC. 3.Set C3, C4 as the default value. 4.Set D9 as the default value. 5.Set E5, E13 as the default value. 6.Set R4, R5 as the default value. 7.Update E14. 8.Set E12 as the default value. 9.Set D16 as the default value. BUG=b:220821454 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ia54256244111a99cb130b74f78c37815099a021a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30mb/google/brya/var/agah: Fix GPU GPIOsTim Wawrzynczak
While adding this train of patches to program the dGPU power sequences, I noticed some of the GPU GPIOs are incorrectly programmed in ramstage, so this patch fixes the settings. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I622b1f5cfba84727bb31792358ca4162c7fa9f52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-30mb/google/guybrush/var/dewatt: Update telemetry valueKenneth Chan
AMD SDLE testing had been done and apply the following telemetry settings for dewatt EVT: vdd scale: 91288 vdd offset: 279 soc scale: 29785 soc offset: 461 BUG=b:219626910 TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE test Change-Id: I4456ffddbf9963f1202a349abe52df2bbb726468 Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63136 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30device/pci_device.c: Return if the scan parameter is invalidArthur Heymans
Clang is unhappy about codepath of an invalid parameter because variables remain unset. Change-Id: I1ba392a48cf3f81a29d9645e5cf220b122d588af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30src/console/Kconfig: Add option to disable loglevel prefixIgor Bagnucki
This patch adds an option to disable loglevel prefixes. This patch helps to achieve clear messages when low loglevel is used and very few messages are displayed on a terminal. This option also allows to maintain compatibility with log readers and continuous integration systems that depend on fixed log content. If the code contains: printk(BIOS_DEBUG, "This is a debug message!\n") it will show as: [DEBUG] This is a debug message! but if the Kconfig contains: CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n the same message will show up as This is a debug message! Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Change-Id: I911bb601cf1933a4c6498b2ae1e4cb4d4bc85621 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-29mb/google/skyrim: Disable PSP postcodesKarthikeyan Ramasubramanian
ESPI is not initialized in PSP. Hence any attempt to write to port80 causes failure to boot. Disable PSP postcodes for now and re-enable it later after ESPI is initialized in PSP. BUG=b:224618411 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-29soc/amd/sabrina: Do not clear Port80 enable bit in ESPI DecodeKarthikeyan Ramasubramanian
This is done to work around a hang when SMU writes to port80. Remove it after the issue is fixed. BUG=b:224618411 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/mediatek: Ensure PERST# deassertion time follows the specJianjun Wang
According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met, calculate the elapsed time since assertion. If it is smaller than 100ms, do an extra delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the measured PERST# time: [DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries) And the SSD information in boot log is as follows: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29mb/google/cherry: Pre-initialize PCIe at the bootblock stageJianjun Wang
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Instead of asserting PERST# right before PCIe initialization and waiting for 100ms, which is currently the only function of 'mtk_pcie_pre_init', so that the extra 100ms delay in ramstage is avoided. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29soc/mediatek/mt8195: Add early init supportJianjun Wang
Add early init support for MT8195 platform. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29soc/mediatek: Add early_init for passing data across stagesJianjun Wang
Add support for "early_init_data" region, which can be used to store data initialized in an early stage (such as bootblock), and retrieve it in later stages (such as ramstage). TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29soc/amd/common/block/lpc: Add support to not clear port80 enableKarthikeyan Ramasubramanian
SMU locks up sometimes if the port80 enable bit is cleared in the ESPI Decode register. Add a config to choose between clearing the entire ESPI Decode Register vs retaining the port80 enable bit. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-29mb/google/brya/var/felwinter: Update GPP_E19 from NF to NCJohn Su
Configure GPIO according to b:224107199 comment#15. - GPP_E19 from NF to NC. BUG=b:224107199 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-03-29soc/mediatek/mt8186: Enable USE_CBMEM_DRAM_INFORex-BC Chen
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8186. Therefore, we select this configuration to enable it. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de Reviewed-on: https://review.coreboot.org/c/coreboot/+/63114 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"Rex-BC Chen
The memory initialization reference code didn't support returning DRAM information in the old platforms, for example MT8192 and MT8195. So we have to add a new configuration USE_CBMEM_DRAM_INFO to make sure the common code will try to get DRAM information on new platforms supporting that. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-29soc/mediatek/mt8186: Fix pmif setting for low power modeZhiyong Tao
The current pmif register setting for low power mode is incorrect, which is causing suspend failure. The issue of suspend failure is that SRCLKENA0 will not be pulled down. EC will not be informed AP is suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode() to correct the setting. This implementation is based on chapter 3.7 in MT8186 Functional Specification. BUG=b:215639203 TEST=test of suspend and resume pass. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-29mb/google/cherry: support max98390 audio ampTrevor Wu
The Cherry follower projects may choose Max98390 for audio output so we have to add a new config CHERRY_USE_MAX98390. Also, the 'dojo' device is the first one to use it. BUG=b:204391159 BRANCH=cherry TEST=emerge-cherry coreboot TEST=Verify beep function through CLI in depthcharge successfully Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/intel: Move `pmc_clear_pmcon_sts()` into IA common codeSubrata Banik
This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances. Accessing PMC GEN_PMCON_A register differs between different Intel chipsets. Typically, there are two possible ways to perform GEN_PMCON_A register programming (like `pmc_clear_pmcon_sts()`) as: 1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration register. 2. Using MMIO access when GEN_PMCON_A is a memory mapped register. SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to perform GEN_PMCON_A register programming using PMC MMIO. BUG=b:211954778 TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeff Daly <jeffd@silicom-usa.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-03-29src/mainboard/starlabs: Remove unused <option.h>Elyes Haouas
Found using: diff <(git grep -l '#include <option.h>' -- src/) <(git grep -l 'sanitize_cmos(\|get_uint_option(\|set_uint_option(\|get_uint_option(\|set_uint_option' -- src/) |grep "<" Change-Id: Ib79dfa73b8a30ae1b1e432318bd42e4e3d845af3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-28soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZEFelix Held
The Sabrina microcode update files are 3200 bytes large and not 5568 like it is the case on Cezanne where this file was originally copied from. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-03-28mb/google/skyrim: Implement mb_set_up_early_espiRaul E Rangel
This will setup the eSPI GPIOs in bootblock right before eSPI init. BUG=b:226635441 TEST=build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-28mb/google/skyrim: Swap eSPI_CS_L and SOC_DISABLE_DISP_BLRaul E Rangel
The eSPI CS function only exists on AGPIO30. We will need to rework all boards to make eSPI function. I also fixed the comments on the other eSPI pins. BUG=b:226635441 TEST=Build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-28nb/intel/sandybridge/acpi: Support setting PCI bars above 4GArthur Heymans
Although coreboot can allocate resources above 4G, Linux does not consider those allocation valid when there is no region above 4G in _CRS and disables the device. TESTED: x220 with and external GPU via the expresscard slot. Linux does not touch the BARs allocated above 4G. Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-03-28include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM valuesElyes Haouas
Regarding JEDEC Standard No. 21-C, Release 30, page 13, DDR4_SPD_72B_SO_RDIMM and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09. There is no affected board in coreboot tree. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-28soc/intel/alderlake: Enable FSP_USES_CB_DEBUG_EVENT_HANDLER KconfigSubrata Banik
This patch uses the FSP event handler feature and updates with coreboot native debug implementation to unify the debug library between coreboot and FSP. BUG=b:225544587 TEST=Able to build and boot Brya with the same FSP debug log before and with this code changes. Before: Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 With this code change: [SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE [SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 [SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A [SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000 [SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 [SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 [SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-28soc/intel/alderlake: Use coreboot native event handler for FSP-M/SSubrata Banik
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-28device/pciexp_device: Set resources for pciexp_hotplug_dummy_opsJohn Su
Without setting the set_resources field for pciexp_hotplug_dummy_ops, we will get an error during pciexp_hotplug_dummy. [ERROR] NONE missing set_resources Because the set_resources field is considered mandatory, explicitly set it as no-op noop_set_resources. BUG=b:220639445 TEST=emerge-brya coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ifee7479c69cf16025dbd4e3924056ed7f8e253cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/63101 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27mb/google/skyrim: Add DXIO descriptorsJon Murphy
Add Skyrim DXIO descriptors using info from AMD and skyrim bouard shematics. BUG=b:225179599 TEST=Boots to OS on Skyrim Board Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27mb/google/hatch/moonbuggy: Update GPIOsPablo Ceballos
Implement the GPIOs that have been changed from genesis. - Connect scaler UART on pins C12/C13 - Connect the HDMI redriver I2C on C18/C19 - Connect the iMX8 signals on D1/D2/D3/D21/D22 - Connect the EC interrupt on D14 (same as on scout) - Connect PCH_TYPEC_UPFB on E15 (same as on genesis) - Configure as not connected the following unused pins: D23, E11, E12, F11 -> F22, H0, H8, H9 BUG=b:200876872 TEST=moonbuggy boots Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Signed-off-by: Pablo Ceballos <pceballos@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-27mb/google/brya/var/banshee: Add mic mute switch settingFrank Wu
Using the GPP_F22 as mic mute switch based on the latest schematic. BUG=b:223737606, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The mic_mute event is changed when the mic_mute GPIO pin is switched. Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.639995, -------------- SYN_REPORT ------------ Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.648152, -------------- SYN_REPORT ------------ Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPOZhuohao Lee
Currently, we control the GPP_D0 in the flash_fp_mcu in order to program the component's firmware. If we set this pin to NC, then we can't control the GPP_D0 output low/high and that make the system fails to program the component's firmware. This patch sets the GPP_D0 to GPO to fix it. BUG=b:204679292 BRANCH=firmware-brya-14505.B TEST=program the component's firmware Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27soc/mediatek: Include 'console/console.h' when appropriateElyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) Change-Id: I93f930de5a2a477ec4c0d8e5c8c57b25f5e4252c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
2022-03-27src/soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifc85ed8b5660eca11be50fddda0cf32aa1dd611c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-27src: Remove unused <bootmode.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <bootmode.h>' -- src/) <(git grep -l 'platform_is_resuming\|gfx_set_init_done\|gfx_get_init_done\|display_init_required\|get_ec_is_trusted\|get_lid_switch\|get_wipeout_mode_switch\|clear_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_write_protect_state\|init_bootmode_straps' -- src/) |grep "<" Change-Id: I2ebd472e0cfc641bd7e465b8d29272fd2f7520a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-27mb/google/brya/var/brya0: Replace amp max98357 with max98360Amanda Huang
Based on Brya EVT schametic, replace audio amp max98357 with max98360. Add a new audio FW_CONFIG field to support ALC5682I+MAX98360. BUG=b:224423056 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-27mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-NUsha P
Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP. BRANCH:NONE TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-27vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping tableFelix Held
Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO lanes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27include/espi.h: Switch to types.hRaul E Rangel
We use bool in this file, so switch to using types.h. BUG=b:226635441 TEST=Build skyrim with DEBUG_ESPI Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I78b579de4e3832dd49a18413bf5d03870e347c91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63092 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-27soc/mediatek/mt8195: Update audio and adsp power controlChun-Jie Chen
To control I2S in MT8195 for dojo project, we need to enable adsp power before audio power. Therefore, we need to update bus protection steps to correct the setting. TEST=build pass BUG=b:204391159 BRANCH=cherry Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: I0bcf1ddeebf0d3df0a1d6b22273123be1aaf85a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63106 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung partsRobert Zieba
Parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special handling. This commit assigns them exclusive IDs 9 and 11 to facilitate this. BUG=b:224884904 Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-25vendorcode/amd/pi: Fix building with clangArthur Heymans
Change-Id: I82913de07acc13af2f5f2c67853e112fb3c66319 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25amd/cimx/sb800: Fix building with clangArthur Heymans
These are all set but unused variable problems. Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25drivers/intel/fsp2_0: Add native implementation for FSP Debug HandlerSubrata Banik
This patch implements coreboot native debug handler to manage the FSP event messages. `FSP Event Handlers` feature introduced in FSP to generate event messages to aid in the debugging of firmware issues. This eliminates the need for FSP to directly write debug messages to the UART and FSP might not need to know the board related UART port configuration. Instead FSP signals the bootloader to inform it of a new debug message. This allows the coreboot to provide board specific methods of reporting debug messages, example: legacy UART or LPSS UART etc. This implementation has several advantages as: 1. FSP relies on XIP `DebugLib` driver even while printing FSP-S debug messages, hence, without ROM being cached, post `romstage` would results into sluggish boot with FSP debug enabled. This patch utilities coreboot native debug implementation which is XIP during FSP-M and relocatable to DRAM based resource for FSP-S. 2. This patch simplifies the FSP DebugLib implementation and remove the need to have serial port library. Instead coreboot `printk` can be used for display FSP serial messages. Additionally, unifies the debug library between coreboot and FSP. 3. This patch is also useful to get debug prints even with FSP non-serial image (refer to `Note` below) as FSP PEIMs are now leveraging coreboot debug library instead FSP `NULL` DebugLib reference for release build. 4. Can optimize the FSP binary size by removing the DebugLib dependency from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary size is reduced by ~100KB+ and FSP-S debug library size is also reduced by ~300KB+ (FSP-S debug and release binary size is exactly same with this code changes). The total savings is ~400KB for each FSP copy, and in case of Chrome AP firmware with 3 copies, the total savings would be 400KB * 3 = ~1.2MB. Note: Need to modify FSP source code to remove `MDEPKG_NDEBUG` as compilation flag for release build and generate FSP binary with non-NULL FSP debug wrapper module injected (to allow FSP event handler to execute even with FSP non-serial image) in the final FSP.fd. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1018e67d70492b18c76531f9e78d3b58fa435cd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-25sb/amd/hudson/spi.c: Use C over CPP conditionalArthur Heymans
Change-Id: Ie6e2420813e1b3e8885499b4739b1222aa1b46e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25mb/*/BiosCallOuts.c: Fix unused variableArthur Heymans
This fixes clang builds. Change-Id: Ie09fae149a9530ad45f0cd5945e73f46484ef385 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25soc/amd/pi: Use -Wno-pragma-packArthur Heymans
Agesa headers extensively use and override pragma pack which fails to compile with clang. Change-Id: Ib234be536388f41d63c2d26cac4c35881af25930 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/pi/amd_late_init.c: Fix implicit enum conversionArthur Heymans
This fixes building with clang. Change-Id: Ifda9be8996703b06fe9ee30ffb5f56a91629e065 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25amd/fam*/northbridge.c: Remove unused reset_memhole variableArthur Heymans
Change-Id: I9231e0399d0b3ac6a608282571fc6d4aefad9dfb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25amd/fam*/northbridge.c: Fix unused hest variableArthur Heymans
The variable actually makes to code look a lot better. TESTED: BUILD_TIMELESS=1 results in identical binaries Change-Id: Ie9104e4736a3c30b7592bb0e79a8ddc6af579800 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25vendorcode/amd/agesa: Add CFLAGS required by CLANGArthur Heymans
Vendorcode is messy so instead of trying to fix the warnings thrown by clang ignore them on AGESA platforms. Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfieldsArthur Heymans
Clang complains about this. Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25nb/intel/gm45/pm.c: Make clang happyArthur Heymans
Clang complains that the terniary '?' operator is executed before the bitwise '|'. This is true and desired in this case. Being explicit about won't hurt however. Change-Id: I27d1fc1c19e1dab3d1c82e407151eaa46f8c7b03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2Anil Kumar
FSP 2.3 spec introduced new version of NV storage HOB FSP_NON_VOLATILE_STORAGE_HOB2. This new HOB addresses the limitation of FSP_NON_VOLATILE_STORAGE_HOB which can support data length upto 64KB. FSP_NON_VOLATILE_STORAGE_HOB2 allows >64KB of NVS data to be stored by specifying a pointer to the NVS data. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated from FSP 2.3 onwards and is maintained for backward compatibility only. This patch implements the parsing method for FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue to search for FSP_NON_VOLATILE_STORAGE_HOB HOB. BUG=b:200113959 TEST=Verified on sapphire rapids and meteor lake FSP platform that introduces FSP_NON_VOLATILE_STORAGE_HOB2 for retrieving MRC cached data. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25soc/intel/*/meminit.c: Fix formatted printArthur Heymans
This fixes building with clang. Change-Id: If2686b0938d34cd66393eb14205c5c8a5b3ba98b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25soc/amd/noncar/memmap.c: Fix formatted printArthur Heymans
Fixes building with clang. Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63050 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25soc/amd/dmi.c: Fix implicit enum typingArthur Heymans
Clang complains about implicit enum typing so make it explicit. Change-Id: I20aba3bd3af8a7292e04d2496c3cba1ab6ba3019 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25include/efi: Add EFI Status code definitionsSubrata Banik
This patch adds EFI status code macros in `efi_datatype.h` to implement FSP debug event handler natively in coreboot. Added `PiStatusCode.h` and `StatusCodeDataTypeId.h` files for `UDK base >= 2017`, as these files were added with UDK version 2017. BUG=b:225544587 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib2debb6a50581456783dc9f22f892f8f92a25509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25include/efi: Add correct header file for EFI_PROCESSOR_INFORMATIONSubrata Banik
This patch resolves compilation issue of including `efi_datatype.h` in other stage files due to unresolved EFI_PROCESSOR_INFORMATION macro definition. EFI_PROCESSOR_INFORMATION defined in `Protocol/MpService.h` hence, included to resolve compilation issue. TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4c0ca4f8876e46f1748ffc9e3b90de00ead80ebd Reviewed-on: https://review.coreboot.org/c/coreboot/+/63010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25soc/mediatek/i2c.c: Remove unused variablesArthur Heymans
Change-Id: Iaa643feb76530cc74acf4d714d8a7f96709be1cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-03-25mb/google/skyrim: Increase RW_MRC_CACHE FMAP region sizeKarthikeyan Ramasubramanian
ABL generates memory training data whose size is ~80KiB. So increase the RW_MRC_CACHE region size to accommodate that. BUG=b:224618411 TEST=Build and boot to payload in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume BUG=b:194990818 TEST=Build guybrush Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25soc/amd/sabrina: update soft fuse bit 15 definitionFelix Held
For SoC that don't support LPC any more the definition of the PSP soft fuse chain bit 15 has changed. Earlier SoCs that still supported a physical LPC bus used this bit to determine if the I/O port 0x80 POST code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a physical LPC bus any more and on those this bit selects if the PSP debug output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that the needs to be decoded to eSPI. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25mb/google/brya: Adjust FMD file to chromeos.fmd for kanoDavid Wu
The separate FMD file for Kano is no longer required, as it was only required for early prototype testers, and those devices will be retired soon, therefore switch back to the original FMD file. BUG=b:226018550 TEST=Build pass. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-25drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15Eric Lai
Ti50 FW under 0.15 is not support board cfg command which causes I2C errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed. Add workaround for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-03-25mb/dell/snb_ivb_workstations: Add Precision T1650 supportMichał Żygowski
Precision is a Mid Tower chassis platform with very similar mainboard to OptiPlex 9010. It has one more PCIe port and a PCI port. It also incorporates C216 chipset instead of Q77 and enables DRAM ECC support. Other changes are related to subsystem ID and fan control initialization. TEST=Boot Dell Precision T1650 and launch Debian 10. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-25mb/dell: Convert OptiPlex 9010 into directory with variantsMichał Żygowski
New boards like Dell Precision T1650 will be added as variants, in subsequent commit. They share most of the code, except some EC initialization tables, PCIe port configuration and subsystem ID. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-03-24soc/intel/common: Add APIs to check CSE's write protection infoSridhar Siricilla
The patch add APIs to check CSE Region's write protection information. Also, adds helper functions to get the SPI controller's MMIO address to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read protection details. During the coreboot image build, write protection is enabled for CSE RO. It is enabled through a Intel MFIT XML configuration. TEST=Verify write protection information of CSE Region Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-24drivers/net/r8168: Add support for Realtek RTL8111KRaihow Shi
The Realtek RT8168 and RTL8111K have a similar programming interface, therefore add the PCI device ID for the RTL8111K into driver for support. BUG=b:226253265 TEST=emerge-brask coreboot chromeos-bootimage. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I5ad8f14483393d6f25026847cc0d4229d362bba0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-03-24driver/wifi: Add _DSM method for DDRRFIMVarshit B Pandya
coreboot needs to propagate the CnviDdrRfim value info of the feature enable/disable state into the CNVi via the WiFi DSM ACPI object. This will be consumed by the Wi-Fi driver and it will act according to CB enablement configuration. This patch adds _DSM method for that. Add support for following 2 functions in _DSM method - Function 0: Function Support Query Returns a bitmask of functions supported. - Function 3: RFI enablement 0 Feature Enable 1 Feature Disable Note: Wifi Dsm already has provision for SAR. This patch will add additional support to return RFIM structure based on UUID. BUG=b:201724512 TEST=Build, boot brya0 and dump SSDT entries Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x09 }) } If ((Local1 == One)){} If ((Local1 == 0x02)){} If ((Local1 == 0x03)) { Return (Zero) } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-24mb/google/brya/var/gimble: Include 4 new SPDsMark Hsieh
Add the four SPD files for LPDDD4 memory parts below to gimble: 1. Hynix H54G56CYRBX247 2. Hynix H54G46CYRBX267 3. Samsung K4UBE3D4AB-MGCL 4. Samsung K4U6E3S4AB-MGCL BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I143207cda066603051803b9008eb2e2364f16e46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-23soc/amd/sabrina: Add prompt for AMDFW_CONFIG_FILEKarthikeyan Ramasubramanian
This will allow configuring the concerned config through an external defconfig file. BUG=None TEST=Ensure that AMDFW_CONFIG_FILE is configurable. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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