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2023-07-25mb/ibm/sbp1: Improve SMBIOS type 17 entriesPatrick Rudolph
Add bank locator and slot existance to the mainboard code. TEST: Verified on Linux that all slots show in dmidecode -t 17. Change-Id: I4ced36e26368d3f99a7341cb55a8deb118b2d1a4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-07-25soc/intel/meteorlake: Remove dummy CPU_SPECIFIC_OPTIONSElyes Haouas
Change-Id: I0f9299d4b7417efac0d5fba39d40b97d6c3a1926 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-25soc/intel/xeon/spr: Improve RMT configurationNaresh Solanki
Set AllowedSocketsInParallel to 1 for RMT builds. This help in associating any failures encountered during RMT run with the corresponding Socket/MC/DIMM. Intel recommended setting EnforcePopulationPor to 1 for RMT runs for debugging failures if any. Change-Id: Ie2301368e9470cc23171c3c4eca9fe978e1513d4 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76679 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-07-25mb/ibm/sbp1: Drop SuperIO codePatrick Rudolph
The SuperIO is not used so don't enable decoding of 0xE2 and drop all code using it. It's not even required for the virtual UART on 0x3f8 to work. Add the virtual UART on 0x3f8 as ACPI device. TEST: Verified on SBP1 that serial still works. Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-25mb/google/nissa/var/pujjo: Generate SPD ID for new supported memory partLeo Chou
Add pujjo new supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Hynix H58G56BK7BX068 2. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 3. Micron MT62F1G32D2DS-026 WT:B BUG=b:292452868 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ia123a1cfd93a5e08ab0ba65f1d9be240d60ff356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76672 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25mb/google/rex: Create screebo4es variantSubrata Banik
This patch creates a new variant screebo4es. The new variant will support only ESx samples. The existing rex variant will support the QS samples. BUG=b:292280656 TEST=Able to build google/screebo4es board and boot on target hardware. Change-Id: If77b4a773bee3633008d39c1886b61869c9618de Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-25mb/google/rex: Use specific mainboard part name for each rex variantsSubrata Banik
BUG=b:290894460 TEST=`emerge-rex coreboot chromeos-bootimage` then check variant name with image*.bin. Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I8f739485dbaab074f57eaa4dacc9f228a3f4aa14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76667 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-24soc/amd/*/Makefile.inc: Do not add APOB NV entry when disabledFred Reitberger
Do not add type 0x63 entry to amdfw.rom when APOB_NV cache is disabled. BUG=b:290763369 TEST=boot birman multiple times with/without APOB_NV cache enabled Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Iefe6f56d7dbedd289680f25a5f372eaa12e967b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76568 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-24mb/google/myst: Disable APOB NVFred Reitberger
Disable the APOB cache for only Myst, and re-enable APOB for other Phoenix SOC mainboards. BUG=b:290763369 TEST=verify APOB cache is disabled Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie611e0b84611b2f50c989c75612fc2186b2dbfdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/76567 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-07-24soc/amd/common/block/apob: Add Kconfig option to disable APOB NVFred Reitberger
Add Kconfig option to disable the non-volatile APOB cache for a mainboard using an SOC that supports APOB. BUG=b:290763369 TEST=verify APOB cache is disabled when selected Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I0170355bbf29ea6386fa69a318e61f057b9a9a3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76566 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-24soc/amd/phoenix/Makefile.inc: Enable amdfw manifestFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic030f91bbfd7226d7adbbe83a2f9e7930af46207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-24mb/google/dedede: Add ALC5650 to AUDIO_AMP in devicetreeDaniel_Peng
Mapping to the fw_config of AUDIO_AMP in dedede, and set new AUDIO_AMP configuration of ALC5650 as value 4. BUG=b:284060672 BRANCH=dedede TEST=build pass Change-Id: Ic3dccd09d3ba1619cce2ac0d5f123badbeeaccdc Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-23acpi.c: Add functions to create GTDTArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ica6b2d79d61558706998edbbaee185125ff5b36c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-22mb/google/rex/var/screebo: Reduce TCC from 90°C to 80°CSubrata Banik
This patch increases the `tcc_offset` to reduce the TCC (Thermal Control Circuit) activation temperature to avoid running into abrupt power off during power cycle tests. On Intel processors, the core frequency can be by an HW agent when the current temperature reaches the TCC activation temperature. The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants). However, this patch adjusted the TCC by specifying an offset in degrees C (i.e., using `tcc_offset` from variant override device tree). Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats. BUG=b:283008762 TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown. Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21soc/intel/alderlake: Hook up UPD PchHdaSdiEnableBora Guvendik
Hook the PchHdaSdiEnable UPD so that mainboard can change the settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes. BUG=b:268546941 TEST=Verified the settings on google/brya using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I82bbfa5442936aefa53f8826e395b7ce75c895a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-21mb/google/volteer: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:290985698 BRANCH=firmware-volteer-13672.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I87173f93d0e47baa816d15dad0777007342b4fdb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-21mb/google/rex: Use BOARD_GOOGLE_MODEL_REX instead variant nameSubrata Banik
Choose BOARD_GOOGLE_MODEL_REX while setting up the default config value for variants created using google/rex model. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I107f4e375b5c9e9c0fb80c4d396164c10c1fc1e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21mb/google/rex: Create rex4es variantDinesh Gehlot
This patch creates a new variant rex4es. The new variant will support ESx samples. The existing rex variant will support the QS samples. BUG=b:290732344 TEST=Able to build google/rex4es board and boot on target hardware. Change-Id: I25dd1f42ee812f47289da0c2ef7aa79d6f340d48 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-21mb/google/rex: Create a `rex` model for easier variant integrationSubrata Banik
This patch creates  a rex model so that other variants developed using `rex` baseboard are easy to land without duplicating the config selection. So far, `rex0` and `rex_ec_ish` are developed using the `rex` model. The plan is to extend the support for `rex4es` and `rex4es_ec_ish` variants. TEST=Able to build and boot google/rex. Change-Id: Id4e8d1162da93b7266ee1108f870e89b6d884ab9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76608 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21acpi/acpi.c: Split of ACPI table generation into separate filesArthur Heymans
acpi.c contains architectural specific things like IOAPIC, legacy IRQ, DMAR, HPET, ... all which require the presence of architectural headers. Instead of littering the code with #if ENV_X86 move the functions to different compilation units. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5083b26c0d4cc6764b4e3cb0ff586797cae7e3af Reviewed-on: https://review.coreboot.org/c/coreboot/+/76008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-21acpi/acpigen.c: Ignore compiler warning about stack overflowingArthur Heymans
With arm64 -Wstack-usage= is enabled which is triggered on any use of alloca(). Since this function basically works on x86 without wrecking things and causing massive stack consumption it's unlikely to cause problems on arm64. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5d445d151db5e6cc7b6e13bf74ce81007d819f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76007 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-21vendorcode/amd/fsp/common: Refactor dmi_info.hKonrad Adamczyk
SoC family is able to provide SoC-specific information via amd/fsp/<soc_family>/soc_dmi_info.h. Use common amd/fsp/common/dmi_info.h for all AMD platforms. This way, duplicated dmi_info.h files in vendorcode/amd/fsp/<soc_family>/ can be removed. BUG=b:288520486 TEST=Dump `dmidecode -t 17`. Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76107 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-20soc/amd/common/pi: Ensure AGESA S3 resume called before SMM lockMatt DeVillier
AGESA S3 restore needs to occur before SMM finalization/locking, but it's a crapshoot as to which runs first since both use the same BS_OS_RESUME/BS_ON_ENTRY boot state callback, and there's no way to prioritize/force ordering. To work around this, move the AGESA S3 resume call to the preceding boot state (BS_OS_RESUME_CHECK) to ensure it runs first, and guard it to ensure it only runs on the S3 resume path. BUG=none TEST=build/boot google/liara, verify S3 resume successful. Change-Id: I765db140c6708a0b129f79fb7d3dc8a4ab3095bd Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76592 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-07-20mb/google/rex/var/screebo: Change GPIO of WIFI moduleWentao Qin
Follow baseboard Rex to make GPIO changes BUG=b:286187821 TEST=Ability to enable and disable WIFI function in OS. Change-Id: I805ce859c42c7c0a9d117418a80555658f844e09 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76551 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-07-20soc/amd/common/smn/Kconfig: expand SMN acronymFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icce4092f1e09d492e0faf4b5e85525871614d73d Reviewed-on: https://review.coreboot.org/c/coreboot/+/76607 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-20soc/amd/common/block/smn: add smn_read64Felix Held
Add smn_read64 which calls smn_read32 twice to read two adjacent 32 bit SMN registers and merges the results into a 64 bit value which it then returns. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2d58ec9818559cbefd7b819ae311ad02fafa18f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-20mb/google/link: rework TP/TS ACPI for new Windows I2C driverCoolStar
This supports a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way. On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C driver arbitrator to attach to. The MMIO method is used instead of _CRS so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver). Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached. The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses. The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware. Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-07-20soc/intel/xeon_sp: use VGA_MMIO_* defines from arch/vga.hFelix Held
Now that we have x86 architecture specific VGA_MMIO_* defines in arch/vga.h, use those instead of having SoC-specific defines for this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I77b914d563bdc83e7fad7d7fccd5cf7777cb4918 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-07-20acpi: Add GTDT structsArthur Heymans
Copied from Linux kernel. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I09f84e63346a270f1c7b77e8088b114800ff4864 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75923 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-20acpi: Move ECAM resource below PNP0C02 device in a common placeArthur Heymans
From the Linux documentation (Documentation/PCI/acpi-info.rst): [6] PCI Firmware 3.2, sec 4.1.2: If the operating system does not natively comprehend reserving the MMCFG region, the MMCFG region must be reserved by firmware. The address range reported in the MCFG table or by _CBA method (see Section 4.1.3) must be reserved by declaring a motherboard resource. For most systems, the motherboard resource would appear at the root of the ACPI namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and the resources in this case should not be claimed in the root PCI bus’s _CRS. The resources can optionally be returned in Int15 E820 or EFIGetMemoryMap as reserved memory but must always be reported through ACPI as a motherboard resource. So in order for the OS to use ECAM MMCONF over legacy PCI IO configuration, a PNP0C02 HID device needs to reserve this region. As no AMD platform has this defined in DSDT this fixes Linux using legacy PCI IO configuration over MMCONF. Tianocore messes with e820 table in such a way that it prevents Linux from using PCIe ECAM. This change fixes that problem. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-20mb/inventec: Add Intel SPR server board Inventec TransformersAnnie Chen
CPU: - 2 SPR sockets - 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU - Up to 32 DDR5 DIMM - 1 Gbase-T NIC port - 1 USB3.0 type A, 1 USB2.0 connector - 1 VGA connector BMC: - ASPEED AST2600 BMC - 1 DDR4 8Gb memory - 1 8GB eMMC Test: The board boots to Linux 4.19.6 with all 192 cores available. Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com> Reviewed-by: Annie Chen <chen.annieet@inventec.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-07-20mb/google/nissa/var/uldren: Decrease GT7996F stop_delay_ms to 200msDtrain Hsu
In order to reduce S0ix resume time, decrease stop_delay_ms from 300ms to 200ms for Goodix GT7996F. The value source is from https://partnerissuetracker.corp.google.com/issues/285999032#comment16. BUG=b:285999032 BRANCH=firmware-nissa-15217.B TEST=boot uldren to ChromeOS and touchscreen is workable. Change-Id: I2f0adadbd3d0774da03338cc0abd1639104876d9 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76577 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-20drivers/mipi: Modify INX_P110ZZD_DF0 panel initialization codeCong Yang
There is a problem of screen shake on the old panel[1]. So increase the panel GOP component pull-down circuit size in hardware, and update the initialization code at the same time. The new initialization code is mainly adjusted for GOP timing. When Display sleep in, raise all GOP signals to VGHO and then drop to GND. In order to be consistent with the current panel model, let's rename this file. [1]: INX old panel product number is HJ110IZ-01A-B1, and the new panel product number is HJ110IZ-01A-B2. We have recalled the shipment old panel. BUG=b:270276344 BRANCH=trogdor TEST= test firmware display pass Change-Id: I2b2534afee1ed700c39d3c360aafd685b63ccbfb Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-07-19mb/google/rex/var/ovis: Update the Type-C USB2/3 port mappingSubrata Banik
This patch updates the Type-C USB2/3 port mapping to reflect the mux connection change as mentioned in previous patch commit ee3f796200bf3baf8a1906 (mb/google/rex/var/ovis: Fix mux change as per schematics). Here is the correct port mapping after considering the mux swap: +--------------------------------+-------------+---------------+ | TCSS-USB Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | +------------------+-------------+-------------+---------------+ BUG=b:289300284 TEST=Able to build and boot google/ovis to get display over Type-C1 and Type-C2 port. Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-19soc/intel/alderlake: Use 1MB CBMEM console buffer with FSP debugSubrata Banik
Patch to increase CONSOLE_CBMEM_BUFFER_SIZE to contain FSP debug serial log. The existing implementation uses larger cbmem size irrespective of FSP debug is enabled or not. Ideally. larger cbmem size is required only if FSP debug is enabled. Bug=b:284124701 TEST=Able to build and boot google/marasov. Change-Id: I9a9e660f2738813808e0dd65d2783424b49f9a5e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-19soc/intel/{adl, mtl}: Reduce CAR usage while using FSP debug binariesSubrata Banik
Reduces the CAR (Cache-as-RAM) variable usage while using FSP debug binaries, which can prevent the CAR from becoming too full and unable to integrate other CAR global variables. This change has the following downsides: - FSP debug output into the cbmem buffer will be partial. To test this change, you can: Build and boot google/rex without any function impact with non-serial and serial FSP debug image (unless what has been documented here). Bug=b:284124701 TEST=Able to build and boot google/rex. Change-Id: I16a1aa25fd32327d03a37381a696c86c95014ba0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-19mb/google/rex/var/screebo: Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18Kun Liu
Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18 BUG=b:291051683 BRANCH=none TEST=emerge-rex coreboot Change-Id: Ic102e42482328580c5334e6ff036b774f5002e00 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76565 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18include/cpu/amd/msr: introduce and use PSTATE_MSR_COUNTFelix Held
Add and use a define for the total number of P-state MSRs to avoid magic constants in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I37a89faa0f216790b3404fc03edc62408684cc24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-18soc/amd/stoneyridge/pstate_util: fix off by one in P-state MSR numberFelix Held
There are 8 P-state MSRs and not only 7. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic2899b6e454233c6cbb8fc1e439ff069c4d3d3a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-18soc/amd/*/root_complex.c: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If2048c9cade731b2e4464d0670e0578f5f4bcea0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-18soc/amd/stoneyridge: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I2d01424731b149daa3d3378d66855ee5e074473b Reviewed-on: https://review.coreboot.org/c/coreboot/+/76290 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-18mb/google/brya/var/osiris: Enable CsPiStartHighinEct for Hynix memoryDavid Wu
According to Intel doc#763797 to overcome early command training hang issue, the CsPiStartHighinEct needs to be enabled for hynix memory. BUG=b:284192689 BRANCH=firmware-brya-14505.B TEST=Built and booted into OS. Change-Id: Ic177c5ffcb6a3d3f76292a0d99ab0e806d43fc11 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76549 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-18mb/google/brya/var/taeko: Enable CsPiStartHighinEctJoey Peng
Enable CsPiStartHighinEct to fix MRC Cache fail issue BUG=b:279835630 BRANCH=none TEST=Pass MRC Cache test with toolkit 1000 times Change-Id: I25cd856785bab9c661e30e2987b43f0dc2ba9564 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18mb/google/brya/var/kano: Enable CsPiStartHighinEct for Hynix memoryDavid Wu
According to Intel doc#763797 to overcome early command training hang issue, the CsPiStartHighinEct needs to be enabled for hynix memory. BUG=b:281643325 BRANCH=firmware-brya-14505.B TEST=Built and booted into OS. Change-Id: I95702e675fa3b73c7e8ee0c8625c7828d8129ea8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76355 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/alderlake: Hook up CsPiStartHighinEct UPDKane Chen
This commit provides option for board to set CsPiStartHighinEct FSP UPD using a new cs_pi_start_high_in_ect mb_cfg field. BUG=b:279835630 BRANCH=none TEST=CsPiStartHighinEct UPD is set properly Change-Id: I7d0d5f3c782e29fb047ea421e1a5fdfc30bcc26d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18memory_info: Bump to 64 DIMMsPatrick Rudolph
Intel SPR supports up to 64 DIMMs on a 4 socket board. Bump DIMM_INFO struct to 64 slots to properly present all of them to the OS. Change-Id: I52d77c4e9bff96adba6d265a272e0e425dbdb791 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73367 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-07-18mb/system76/rpl: Add Galago Pro 7 as a variantTim Crawford
The Galago Pro 7 (galp7) is a Raptor Lake-H board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Windows 10 and Linux 6.2 - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Not working: - Detection of devices in TBT slot on boot Change-Id: I1ae3b2c647aa75976a1ea97f7681f93eb000ba8a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75277 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/adl: Disable Intel ME by defaultTim Crawford
Disable the CSME by default now that S3 is used instead of S0ix. The CSME will not go into a low power state during S0ix when it is disabled. This prevents the CPU from reaching C10 and so increases the power usage during suspend compared to leaving CSME enabled. (This was measured to be a ~2W different on TGL-U.) In S3, the state of the CSME doesn't matter because the CPU will be off. Change-Id: I88c0aebdcc977f3ba9dd8f46a6abfaa7a4ae8eb6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73354 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-18{ec,mb}/system76: Replace color keyboard logicTim Crawford
System76 EC since system76/ec@9ac513128ad9 detects if the keyboard is white or RGB backlit via `RGBKB-DET#` at runtime. Remove the Kconfig for the selection and update the ACPI methods for the new functionality. Change-Id: I60d3d165a58e30d2afc8736c0eb64dd90c8227ca Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76152 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/rpl: Add Darter Pro 9 as a variantTim Crawford
The Darter Pro 9 (darp9) is a Raptor Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots with 5200 MT/s memory - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Change-Id: If19caa90e5f90939b2946392da343b7f91f568ca Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75278 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/rpl: Add Serval WS 13 as a variantTim Crawford
The Serval Workstation 13 (serw13) is a Raptor Lake-HX board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 Keyboard - I2C HID touchpad - Both DIMM slots with 5200 MT/s memory - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio output - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Not working: - Discrete/Hybrid graphics - Thunderbolt Change-Id: Id709a7d06854ba9de673d5e3f25c0a1bbcc53d21 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73440 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/adl: Switch from S0ix to S3Tim Crawford
After fixing TPM logs clobbering other regions in CB:73297, S3 no longer causes cache issues resulting in power off after multiple suspends. This is required for disabling Intel CSME by default. Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-18security/tpm: Respect CBMEM TPM log sizeJeremy Soller
The preram TPM log was being copied to the end of the CBMEM TPM log no matter what the size of the CBMEM TPM log was. Eventually, it would overwrite anything else in CBMEM beyond the TPM log. This can currently be reproduced by enabling TPM_MEASURED_BOOT and performing multiple S3 suspends, as coreboot is incorrectly performing TPM measurements on S3 resume. Change-Id: If76299e68eb5ed2ed20c947be35cea46c51fcdec Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73297 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/xeon_sp: Skip empty socketsPatrick Rudolph
The current Sapphire Rapids code assumes that all sockets have working CPUs. On multi-socket platforms a CPU might be missing or was disabled due to an error. The variable PlatformData.numofIIO and the variable SystemStatus.numCpus reflect the working CPUs, but not the actual socket count. Update the code to iterate over sockets until PlatformData.numofIIO IIOs have been found. This is required as FSP doesn't sort IIOs by working/non working status. This resolves invalid ACPI table generation and it fixes a crash as commands were sent to a disabled CPU. TEST: Disabled Socket1 on IBM/SBP1. Change-Id: I237b6392764bbdb3b96013f577a10a4394ba9c6e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76559 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/google/dedede/var/boxy: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:290876132 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Change-Id: Id5e0ba7a4ca57e311465ba8e74105f5ee7b8ee8a Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76435 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18pujjoteen5: modify fw_config to separate pujjoteen5 wifi sar tableLeo Chou
Use fw_config to separate pujjoteen5 intel wifi sar table. BUG=b:279984381 Test=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I2e744bf0801bd7b18817a00fcbe3d0c62b8fc3d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76453 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-18mb/google/nissa/var/gothrax: Initialise overridetreeYunlong Jia
Add an initial overridetree for gothrax based on the schematic. BUG=b:274707912 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76013 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/xeon_sp: Use SocketID in NUMA table generationPatrick Rudolph
Use the actual SocketID instead of the running index. Change-Id: I9128909756d0dbb0c4dabc52acdc98cb2a4f7baa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/xeon_sp: Remove invalid commentPatrick Rudolph
The comment is only true if all sockets have working CPUs installed. Change-Id: I8c3376c9233c33fb770082573e07e9d96abb7855 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76557 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-18soc/intel/xeon_sp: Introduce soc_cpu_is_enabledPatrick Rudolph
Add a function to check if the CPU placed at the specified socket was found usable during QPI init. This is useful for multi-socket platforms were a CPU is missing or has been disabled due to an error. Change-Id: I135968fcc905928b9bc6511e3ddbd7d12bad0096 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-18soc/intel/xeon_sp: Print HOB for all socketsPatrick Rudolph
Use the FSP define to iterate over all sockets as the runtime value of numofIIO is the detected number of sockets, not the highest working socket. This fixes printing the HOB on multi-socket platforms where a CPU has been removed or has been disabled (4S system running as 3S). Change-Id: Ieed67cd48d26c7634636c0aae6a56f3b6fbdf640 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76492 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/google/nissa/var/gothrax: Set up driver as per schematicsYunlong Jia
Drivers for Pen Garage/SDCard Reader/LTE/SAR/WWAN and I2C for TPM. BUG=b:274707912 BRANCH=None Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1203ca13bd55b8ab96ce5d323a36ffde06860fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76104 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com>
2023-07-18soc/intel/meteorlake: Enable PCIE_CLOCK_CONTROL_THROUGH_P2SBKane Chen
On Intel Meteor Lake (MTL), PCIe CLK control register is accessed by P2SB on IOE/SOC die. So this patch does: 1. Enable PCIE_CLOCK_CONTROL_THROUGH_P2SB 2. Include pcie_clk.asl 3. Set the correct IOE_DIE_CLOCK_START for MTL-U/H. BUG=b:288976547, b:289461604 TEST=Test on google/screebo and found the pcie clock is on/off properly and sdcard PCIe port doesn't block S0ix with RTD3 cold enabled. Change-Id: I6788ae766f36c9a0d4910fda1d6700f20ce73ea8 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76356 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/common/acpi: Support on/off PCIe CLK by P2SBKane Chen
In the older platform such as Raptor Lake (RPL), Tiger Lake (TGL), it needs PMC IPC cmd to turn on/off the corresponding clock. Now on Meteor Lake (MTL), it control pcie clock registers on P2SB on IOE or SoC die. BUG=b:288976547, b:289461604 TEST=Test on google/screebo and found the pcie clock is on/off properly and sdcard pcie port doesn't block S0ix with RTD3 cold enabled. Change-Id: Ia729444b561daafc2dca0ed86c797eb98ce1f165 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76347 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/meteorlake: Include IOE PCR register accessSubrata Banik
This patch includes the ioe_pcr.asl file as Intel Meteor Lake has support for IOE die. BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Ia534dbc0db5e54e173da9cdf475a7eb2bfda9e2f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76410 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-18soc/intel/common/acpi: Add IOE PS2B access APIsSubrata Banik
This patch implements APIs to access PCR registers from IOE die. BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Ief7a00c4e81048f87ee308e659faeba3fde4c9cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76409 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-07-18soc/intel/meteorlake: Add IOE P2SB Base AddressSubrata Banik
This patch introduces a new config named IOE_PCR_BASE_ADDRESS to define P2SB base address. BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: I289358f9c53b557a397bd7186e6b7419c5d8c954 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76411 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18soc/intel/common/acpi: Create helper APIs for common P2SB accessSubrata Banik
This patch creates a helper library to migrate all the common P2SB access routines. The PCH P2SB ACPI implementation will now rely on the common library to perform PCR read/write operations. This will make the code more modular and easier to maintain. The helper library provides a single interface for accessing P2SB registers. This makes it easier to port the code to different platforms, for example: adding support for PS2B belongs to the IOE die for Meteor Lake SoC generation. BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: I0b2e7ea416ca7082f68d0b822ebb9a87025b4a8b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76408 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17nb/intel/i945: Rework nb resource readingArthur Heymans
- Use newer functions and avoid the * / KiB dance - Use existing functions for figuring out TSEG and UMA Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I73549b23bd1bfd4009e6467a5bdfeef7de81a0cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76272 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17nb/haswell: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ib649943e13b9b319297c4be68b7039b760ebd820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-17Center bootsplash on bigger framebuffersNico Huber
In the JPEG decoder, use `bytes_per_line` instead of `width` for address calculations, to allow for bigger framebuffers. When calling jpeg_decode(), add an offset to the framebuffer address so the picture gets centered. Change-Id: I0174bdccfaad425e708a5fa50bcb28a1b98a23f7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17soc/amd/common/acpimmio: factor out IO port access to PM registersFelix Held
Factor out all functions that use the indirect IO port based access to the PM registers into a new compilation unit and only select it on platforms that support this interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If9c059e450e2137f7e05441ab89c1f0e7077be9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-17soc/amd/common/pm/pmlib: use PM register mapping in ACPIMMIO regionFelix Held
In all SoC pm_set_power_failure_state gets called either after a call to enable_acpimmio_decode_pm04() or the ACPIMMIO mapping is already enabled after reset on the SoC. This allows to use pm_read8 and pm_write8 that use the ACPIMMIO mapping of the PM registers instead of pm_io_read8 and pm_io_write8 which won't work on Phoenix and Glinda due to the IO ports used on older generations to access to the PM registers not being implemented any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0d0523d2c4920da41b3fb73cf62f22a60f1643a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-17sb/amd/pi/hudson/enable_usbdebug: use pm_io_write8Felix Held
Use pm_io_write8 instead of open coding the same functionality. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d9397f2d85e48883f961adbbca0e1e71e825ce0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-17mb/amd/mayan: Enable the PCIe bridge for DT/M.2 SSD1 slotsAnand Vaikar
Change-Id: I5c5b125ac03e07a22bcc15ad2d34c62edf74ee04 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76452 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17soc/amd/common/lpc/lpc_util: use PM register mapping in ACPIMMIO regionFelix Held
In all SoC lpc_early_init gets called either after a call to enable_acpimmio_decode_pm04() or the ACPIMMIO mapping is already enabled after reset on the SoC. This allows to use pm_read8 and pm_write8 that use the ACPIMMIO mapping of the PM registers to set the PM_LPC_ENABLE bit in the PM_LPC_GATING register instead of pm_io_read8 and pm_io_write8 which won't work on Phoenix and Glinda due to the IO ports used on older generations to access to the PM registers not being implemented any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b31ec4e03a06796502c89e3c2cfaac2d41b0ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76461 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17mb/google/rex/var/screebo: Update I2C timingZhongtian Wu
Change i2c[0] parameter Thd:dat = 50ns; Change i2c[1] parameter Thd:dat = 100ns; BUG=b:287898252 BRANCH=none TEST=Test success by EE. Change-Id: Ibdbe4e17cf21c914b48fa6dc7d3eecf8218a2d8b Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76430 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17soc/amd/common/acpimmio/mmio_util: drop enable_acpimmio_decode_pm24Felix Held
None of the platforms that used enable_acpimmio_decode_pm24 is in the tree any more, so drop this function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iea345a825c4581bf2acb932692ebcad2a7a5b4ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/76457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-17soc/amd/glinda/early_fch: don't call enable_acpimmio_decode_pm04Felix Held
The enable_acpimmio_decode_pm04 function uses the IO port based indirect access of the PM register space. The PM_INDEX and PM_DATA registers don't exist any more on Glinda, so the code shouldn't access those. Since the PM_04_ACPIMMIO_DECODE_EN bit in the ACPIMMIO_DECODE_REGISTER_04 register is 1 after reset, the ACPIMMIO space is still accessible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6bc0479ea4ea2b9fe3629a6e15940b31b2864d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-17soc/amd/phoenix/early_fch: don't call enable_acpimmio_decode_pm04Felix Held
The enable_acpimmio_decode_pm04 function uses the IO port based indirect access of the PM register space. The PM_INDEX and PM_DATA registers don't exist any more on Phoenix, so the code shouldn't access those. Since the PM_04_ACPIMMIO_DECODE_EN bit in the ACPIMMIO_DECODE_REGISTER_04 register is 1 after reset, the ACPIMMIO space is still accessible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia41f239b023edc094f5cbae63ed7c079649c74da Reviewed-on: https://review.coreboot.org/c/coreboot/+/76437 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17mb/google/rex: Disable early EC syncSubrata Banik
This patch disables early EC sync to avoid an idle delay (~3sec) without a provision to notify the user about some critical task in progress. Doing EC sync at later stage allows us to notify using graphical msg on screen to make user aware of the WIP task. BUG=b:279944831 TEST=Able to perform EC sync from depthcharge on google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I03ed40827c50e75ceaaf94e30d675014ebf22dac Reviewed-on: https://review.coreboot.org/c/coreboot/+/74837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-17mb/msi/ms7d25: Disable DMI ASPMMichał Żygowski
Disable DMI link ASPM which can degrade performance of overall system. Desktop does not need to be concerned that much about idle power consumption. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69826 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17mb/google/rex/var/screebo: Update touchscreen GPIOZhongtian Wu
Change touchscreen reset_gpio GPP_C01 -> GPP_D07; Change touchscreen enable_gpio GPP_C00 -> GPP_B17. BUG=b:289425753 BRANCH=none TEST=Test success by EE. Change-Id: I7be6a2b4e87126b281f138c819d2a0a5b1af5821 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17drivers/pc80/tpm: Add Infineon SLB9672 IDTim Crawford
Allows the new Infineon TPM chip used on Clevo laptops to be recognized. Change-Id: I2ee31b787d80c0b9c24c748b1b28906a22a1dee7 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-17mb/google/nissa: Create craaskov variantRex Chou
Create the craaskov variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:290248526 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CRAASKOV Change-Id: I1d12f7c3d0ef7067f4530c1c69c560f9a83561f6 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-07-17mb/google/rex/var/karis: Generate SPD ID for supported memory partTyler Wang
Add karis supported memory parts in mem_parts_used.txt, generate SPD id. 1. MICRON MT62F1G32D2DS-023 WT:B 2. HYNIX H9JCNNNBK3MLYR-N6E 3. HYNIX H58G56BK8BX068 4. SAMSUNG K3KL8L80CM-MGCT BUG=b:291018417 TEST=Use part_id_gen to generate related settings Change-Id: I87c2c4f59454dec84d29590ee91379c9fa60ddcf Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76443 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17soc/intel/adl: Add power limits for RPL-H 4P+8E 45WTim Crawford
Change-Id: I01ae5a484287d2adb1516e1e4551b185b895fdde Ref: RPL-UPH and RPL-U Refresh Platform Design Guide (#686872, rev 2.1) Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-17soc/intel/denverton: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Id092b6dd9d42f2965801b0327a857a5a4945f793 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76288 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15soc/intel/common: Add support for AP initiated mode entryKapil Porwal
Add support for AP initiated mode entry. The code flow has been optimized as below - Code flow when AP initiated mode entry is disabled: +-------+ | Start | +---+---+ | | +---------+---------+ |wait_for_connection| | Is DP ALT mode | | available? | +---------+---------+ | +--------------->-------+ Yes| No | +---------+---------+ | |Skip enter_dp_mode | | +---------+---------+ | | | | | +-----------+----------+ | |wait_for_dp_mode_entry| | | Is DP flag set? | | +-----------+----------+ | | | +--------------->-------- Yes| No | +-----------+----------+ | | wait_for_hpd | | | Is HPD_LVL flag set? | | +-----------+----------+ | | | +--------------->-------- Yes| No | +-----------+----------+ | | Rest of the code | | +-----------+----------+ | | | +---------------<-------+ | +---+---+ | End | +-------+ Code flow when AP initiated mode entry is enabled: +-------+ | Start | +---+---+ | +------------+-----------+ |Skip wait_for_connection| +------------+-----------+ | +--------+-------+ | enter_dp_mode | | Is USB device? | +--------+-------+ | +--------------->-------+ Yes| No | +---------+---------+ | | enter_dp_mode | | | Send DP mode | | | entry command | | +---------+---------+ | | | +-----------+----------+ | |wait_for_dp_mode_entry| | | Is DP flag set? | | | (If not, loop wait | | | until timed out) | | +-----------+----------+ | | | +--------------->-------- Yes| No | +-----------+----------+ | | wait_for_hpd | | | Is HPD_LVL flag set? | | | (If not, loop wait | | | until timed out) | | +-----------+----------+ | | | +--------------->-------- Yes| No | +-----------+----------+ | | Rest of the code | | +-----------+----------+ | | | +---------------<-------+ | +---+---+ | End | +-------+ BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Time taken by enter_dp_mode / wait_for_dp+hpd / MultiPhaseSiInit functions with this patch train: 1. When AP Mode entry is enabled - With type-c display on C1 and SuzyQ on C0: 6.9ms / 420ms / 616ms - With USB key on C1 and SuzyQ on C0 : 6.0ms / 505ms / 666ms - Without any device on C1 and SuzyQ on C0 : 3.7ms / 0ms / 178ms 2. When AP Mode entry is disabled - With type-c display on C1 and SuzyQ on C0: 1.7ms / 2.5ms / 213ms - With USB key on C1 and SuzyQ on C0 : 0.9ms / 3.3ms / 177ms - Without any device on C1 and SuzyQ on C0 : 0.8ms / 1.8ms / 165ms Without this patch train, wait_for_hpd would cause a constant delay of WAIT_FOR_HPD_TIMEOUT_MS (i.e. 3 seconds) per type-c port when there is no device connected. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I514ccbdbaf905c49585dc00746d047554d7c7a58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-15ec/google/chromeec: Split wait-loop for DP and HPD flagsKapil Porwal
Split wait-loop for DP and HPD flags as below - - google_chromeec_wait_for_hpd - google_chromeec_wait_for_dp_mode_entry BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e565d6134f6433930916071e94d56d92dc6cb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76370 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15ec/google/chromeec: Call `wait_for_dp_hpd` only in AP mode entryKapil Porwal
Wait for DP/HPD flags only in AP initiated mode entry BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5137c346fbf1edabc60a53e0978e32f54885c330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76369 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15ec/google/chromeec: Skip TCSS `wait_for_connection` for AP mode entryKapil Porwal
Skip TCSS `wait_for_connection` for AP initiated mode entry. BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia04ff470961831237fe851f7ae3feaa5623d4b4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76368 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-15ec/google/chromeec: Skip unnecessary call to TCSS `enter_dp_mode` cmdKapil Porwal
Skip TCSS `enter_dp_mode` command when there is no USB device detected on the port. BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ie6cd84cab3631596d4d7178dae2040e25c621f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-15mb/amd/mayan: Remove useless break after returnElyes Haouas
Change-Id: Iad0244e798c03a26f755024453ecdd745e6286f3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76473 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15mb/amd/chausie: Remove useless break after returnElyes Haouas
Change-Id: Iafc3735b6d903a4496828189db14b09d3c4d2081 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76432 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14mb/google/myst: Remove PRESERVE FMD flag for RW_MRC_CACHEMartin Roth
The PRESERVE flag in the FMD file tells futility not to erase the fmap partition when updating the firmware. Because of an issue on myst right now, we want the RW_MRC_CACHE partition to be erased when the firmware is updated. BUG=b:290763369 TEST=None Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id586ae057b2fd6d513ddbba5e1284dea39467d95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76478 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14vc/amd/fsp/phoenix/FspmUpd: drop eMMC-related UPDsFelix Held
Phoenix doesn't have an eMMC controller and those UPDs were carried over from Picasso. The SoC's fsp_m_params.c didn't write to any of those fields, so this doesn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie3640c1493a92c1effba3ce42103d022bd8399ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/76450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14soc/amd/common: Add warning if microcode CBFS filename is in useMartin Roth
Because of the way that the CBFS filename is generated from the contents of the microcode patch, if a duplicate microcode patch is included in the build, the makefile would create a second copy of the name, which doesn't work. This led to "odd" results where the other attributes of the first copy were erased, causing cbfstool to fail. The cause of the failure is not immediately obvious, and is a little difficult to track down. This patch causes an immediate failure and gives a reason as to the cause of the issue. When a failure is seen, this is the result: File1: 3rdparty/amd_blobs/phoenix/psp/TypeId0x66_UcodePatch_PHXn4_A0.bin File2: 3rdparty/amd_blobs/phoenix/psp/TypeId0x66_UcodePatch_PHX4_A0.bin src/soc/amd/common/block/cpu/Makefile.inc:25: *** Error: The cbfs filename "cpu_microcode_a740.bin" is used for both above files. Check your microcode patches for duplicates.. Stop. TEST=Now checked for both positive and negative failures. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I3d34dc5585182545bdcbfa6370ebc34aa767cae2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76423 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14soc/intel/cannonlake: Hook up ucode for CML-STim Crawford
Hook up microcode from 3rdparty repo for: - 06-a5-03 (CPUID signature: 0xa0653) - 06-a5-05 (CPUID signature: 0xa0655) Fixes loading microcode on system76/bonw14. Change-Id: Ie6789420926fe46fc61ea6773f02dc07dc2e9b5e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-14mb/system76: Drop VGA_BIOS_IDTim Crawford
System76 boards use the VBT data file, not the VGA optionrom. Change-Id: Ie4100e09221ae4f301a621e7aac62e38ac04a444 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>