| Age | Commit message (Collapse) | Author |
|---|
|
This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The iGPU is on the northbridge or system agent, not the southbridge.
Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Modify I2C3 setting to follow I2C specification (lower than 400kHz).
Original setting:
.rise_time_ns = 184
.fall_time_ns = 42
Change to:
.rise_time_ns = 110
.fall_time_ns = 34
BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Compute timings first, then display them. Drop unneeded comments, too.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I121cf9c4db76ec0ced36caf764b1a1a51e47b552
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45501
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr`
wrappers.
Change-Id: I7a6916e535fbba9f05451d5302261418f950be83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
DPR register's size field is given in whole MiB, so correct where it is
used to ensure the correct size multiple (KiB vs. MiB) is used with it.
Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling")
Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This function returns true if any GPIO pad is programmed to route the
given IRQ to the IO-APIC. It does so by keeping track of which pads are
routed to IOxAPIC and looking this up in the new function.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iceda89cb111caa15056c204b143b4a17d59e523e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This code will eventually support both ME 9.x and ME 10.
Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The tXP bitfield is 3 bits wide, and the tXPDLL bitfield is 5 bits wide.
Clamp any values that would overflow this field. Bits in TC_DTP already
get set when the tXP and/or tXPDLL values are large.
Change-Id: Ie7f3e8e01ff7edd2652562080554c0afadde0bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49889
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Both files are equivalent. Drop Broadwell's ctdp.asl and use Haswell's.
Change-Id: Ida17d030d6022af18078321ee76b425095fe9f5c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Fill the ECC type in `struct memory_info` in romstage, and in SoC code.
The SMBIOS override is unnecessary, and this is not mainboard-specific.
Change-Id: I8370b3ee7d75914b895946b53923598adf87b522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There are platforms that support error correction types other than
single-bit ECC. Extend meminfo to accomodate additional ECC types.
It is assumed that `struct memory_info` is packed to save space. Thus,
use `uint8_t` instead of an enum type (which are usually 4 bytes wide).
Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a method to disable decoding the legacy DMA IO ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
Measured I2C frequency just as below after tuning:
touchpad:372 kHz
audio codec RT5682:386.8 kHz
speaker AMP L:387.5 kHz
speaker AMP R:388.9 kHz
BUG=b:181342340
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add ELAN touchscreen into devicetree for storo.
BUG=b:177389448
BRANCH=dedede
TEST=built storo firmware and verified touchscreen function
Change-Id: I0d9e5005928c6fda3d1f0ce8bd9ae135e4a04867
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50981
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds new soundwire device ALC1308
The codec properties are filled out as best as possible
with the datasheet as a reference.
The ACPI address for the codec is calculated with the information in
the codec driver combined with the devicetree.cb hierarchy where the
link and unique IDs are extracted from the device path.
The unique ID is calculated from schematics by referring to ASEL[1:0]
strap settings. Datasheet of ALC1308 provides info about the mapping of
ASEL strap settings to unique ID
For example this device is connected to master link ID 1 and has strap
settings configuring it for unique ID 2.
chip drivers/soundwire/alc1308
register "desc" = ""Left Speaker""
device generic 1.2 on end
end
Bug=None
Test=Build and boot on TGLRVP.Extract SSDT and confirm that the entries for
PCI0.HDAS.SNDW are present for ALC1308
Test speaker out functionality
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ibf3f1d5c6881cbd106e96ad1ff17ca216aa272ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51042
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sathyanarayana Nujella
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:177834652
BRANCH=dedede
TEST=build kracko firmware
Change-Id: I360920f80f4ce5dcbcde25c433e23803fa72569b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This reverts commit d510b60f5b4eee6c165039be4acbe89ff25d8a4a.
This patch includes the DSDT ASL code for shadowmountain board.
BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch includes the ramstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add SMBIOS type 17 asset tag. Use dimm locator as default value.
Tested=Execute "dmidecode -t 17" to check asset tag field is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I323e6b4cf6b11ede253d5a2a4bfc976a3f432b05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Currently, this function is only invoked for the SPI device through
common SoC code. Since both Intel Harcuvar and Scaleway Tagada have
enabled the SPI device in the devicetree, there's no need to use the
debug version of `pcidev_path_on_root`.
Change-Id: I4340d5860d23c2fa230105f7a7d345c367b2b2aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50128
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Suresh Bellampalli <suresh.bellampalli@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Instead, convert the struct to a union and pass in a pointer to it.
Tested on out-of-tree HP ProBook 6550b, still boots.
Change-Id: I60e3dca7ad101d840759bdc0c88c50d9f07d65e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45367
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This allows booting without ME firmware, even though the 30-minute
auto-shutdown still happens. Without this patch, an HP ProBook 6550b
cannot get past the `setup_heci_uma` function call.
Change-Id: I446c02ac6034ede75cb873a2e676c40e4ef84b7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The PCIe device IDs for Ibexpeak are not in bd82x6x's pcie.c driver.
Thus, the code has always been dead code on Ibexpeak. Drop it.
Change-Id: Ide2b4af2a187ecf98f39a9c979646a7ed959c74f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51067
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Taken from document 322170-028 (5 series specification update).
Tested on out-of-tree HP ProBook 6550b (HM57), fixes several issues.
Without this patch, EHCI controllers had no IRQ assigned and there were
unexpected exceptions about NMIs. With this patch, the issues are gone.
Change-Id: Icd31dd89ba49e38a5e4c108a8361dbf636332ab8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51066
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Brya’s chromeos.fmd contains a region for RECOVERY_MRC_CACHE,
but does not select HAS_RECOVERY_MRC_CACHE, so it’s unused.
BUG=b:174266035
TEST=Check MRC cache can allocate in recovery mode.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b83eec3dcf27bafde610a701e55f1371a5d4571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51081
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I667accd980da6384a7cc6a3f4eb7565b8b3b2400
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I3a67008d84da614e8c8cbfa681a0fdd19ff1d77f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexey Vazhnov <vazhnov@boot-keys.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Fetch second source factory cache configuration (SSFC) as an optional
element to the firmware config interface. Introduce a Kconfig so that it
can be enabled and used on required mainboards.
BUG=b:177055126
TEST=Build and Boot to OS in Magolor.
Change-Id: I81137406d21e77b5d58a33f66778e13cf16c85c7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51094
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As per CL:2641346, update GBB flag names:
GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW
GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW
BUG=b:179458327
TEST=make clean && make test-abuild
BRANCH=none
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
When the EC is reset on PLTRST this information will be lost, causing
system control interrupts to potentially stop functioning.
Change-Id: I137ef6c574a372601bc51f6e815158767acd0e1b
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50489
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With this change NMI works in the kernel:
----------------
| NMI testsuite:
--------------------
remote IPI: ok |
local IPI: ok |
--------------------
Good, all 2 testcases passed! |
---------------------------------
See setup_lapic() for where this gets configured.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia391ec5a015d909462ff8aaf3cb047c6fd45fe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
|
|
Follow elan's suggestion to configure IRQ as level trigger to prevent touchscreen lost
BUG=b:180778934
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I3aca0ad20791c989dec9e70d69d637b28c9cc043
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50417
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This function should be using the RK_CLRSETBITS() macros to access the
special Rockchip write-mask registers, like the rest of our code. Also,
there were already existing bit field definitions for these bits that
should be used (although it makes sense to adjust them a bit to allow
passing in the channel number).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If1f5c06aabb16045d890df3bbd271f08a2cdf390
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51080
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
From JSL FSP v2376 "FirmwareVersionInfo.h" header file is
added and "FirmwareVersionInfoHob.h" is deprecated. This patch
adds support to display firmware version information using
"FirmwareVersionInfo.h" header file.
Changes included in this patch:
- Add Kconfig to select FirmwareVersionInfo.h
- Add code change to display firmware version info using
FirmwareVersionInfo.h header
No change in version info print format.
BUG=b:153038236
BRANCH=None
TEST=Verify JSLRVP build with all the patch in relation chain
and verify the version output prints no junk data observed.
couple of lines from logs are as below.
Display FSP Version Info HOB
Reference Code - CPU = 8.7.16.10
uCode Version = 0.0.0.1
Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
|
|
This has been tested on the OCP Delta Lake platform.
Change-Id: I07c882077eb3c035faae81641bc860e69db224b4
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
|
|
Add a weak variant routine to allow variants to perform any needed
initialization in ramstage.
BUG=b:178094376
TEST=none
Change-Id: I65dc1cdf15b68d9f2239e02fcb4b2c902d749378
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50827
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the missing PM initialization for Lynxpoint-H. There are some small
changes to Lynxpoint-LP, since some register writes are common among
both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to
Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values.
Without this patch, nearly all registers don't have the expected values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GPP_E11 should be configured to be routed via APIC to avoid
p-sensor communication error in OS.
BUG=b:178465379
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected.
un-approach：
=> register address: 0x01 value: 0x00
approach:
=> register address: 0x01 value: 0x02
verify sx932x IRQ in "/proc/interrupts" loading as expected.
Change-Id: I7d639ec1f9b31b240475dc1c8025bf59ae1e8e0b
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50876
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the blipper variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:179648964
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BLIPPER
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Change-Id: I8e67521bd9ab05c257cb3d5d5d4cf506f258bfa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
New boards introduced to trogodor family.
BUG=b:180668002
BRANCH=none
TEST=make
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: If0f9b6c89198a882acae7191d08b166eb8c1dd71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
CB:50863 refactored the data_training() function to split out read gate
training into a separate function, but in the course of this forgot to
correctly initialize the local obs_err varible in the new function to 0.
This means that it will be used uninitialized, and when it happens to be
non-zero it makes the training process fail. Due to the convoluted
control flow in the function, it seems that GCC's static analyzer
couldn't pick up on this uninitialized use.
The whole variable is unnecessary anyway, all it's used for is to force
the function to return two lines below without doing anything with
side-effects in between. This patch removes the variable and simplifies
the code in all three training functions to avoid this uninitialized use
issue and make everything a bit more readable. (Also restore the
original pre-clang-format continuation line intendations for more
readability.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia475d64c06f2ec1bf9295742d173ce66717b821c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51079
Reviewed-by: Moritz Fischer <moritzf@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This causes the linux kernel to complain:
32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800
32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804
32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808
32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814
The linux kernel also verifies that the PM Timer block only uses IO
ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I53290226012d9f6c08c6adae0a633c7fd5702135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Stamp_boost 1640 parameter is too short to keep APU performance.
Restore parameter to 2500 then APU could have longer boost time (~3xxx sec)
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Change-Id: Ie08394d0b1a693f71336cb4cb6ce9528dfdce14b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Printing this in both bootblock and romstage is redundant, since the CPU
family and model aren't expected to change between bootblock and
romstage entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78b847c54c6cd3bfc2b947a579f4ba6b410fd2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Because the entries were formatted differently to the baseboard, the
devicetree overrides didn't work as intended, and all 5 entries from
the baseboard were included, and then the overrides were applied, but
the baseboard's entries were kept, so there were duplicate ACPI
entries, which causes errors when parsing the table.
Fixes: 5f30ae3714d ("mb/google/volteer: update thermal table for Eldrid")
BUG=b:181034399
TEST=compile, verify static.c is correct now
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update the first version DPTF parameters. The TDP is down to 13w for acoustic concern.
BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test image and verified by thermal team.
Change-Id: I36f016530a61e3660938ce8d2948bb3b0f275d88
Signed-off-by: Wayne3 Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51030
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The headers added are generated as per FSP v2037.
Previous FSP version was v2037.
Changes Include:
- add BootFrequency, RMTBIT, RmtPerTask, RMTLoopCount and
MrcFastBoot UPDs in Fspm.h
- add EnableFastMsrHwpReq, VbtSize, CpuPcieComplianceTestMode,
LidStatus and PcieComplianceTestMode UPDs in Fsps.h
BUG=b:178461282,b:180627057
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I5496dfebc7b65a94abb31244ef2b400d89d6d444
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50914
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ide0e33826dd237bcd13f00400bbc8a08255b4f62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50945
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Broadwell has these devices, so add them to Lynx Point as well. This is
done in preparation to have Broadwell boards use Lynx Point ACPI code.
Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update the first version DPTF parameters received from the thermal team.
BUG=b:177628854
TEST=cros build-ap --debug -b dedede --fw-name galtic
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia8e76d303db0add95e77693f15cad108fa92303b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Change-Id: I4dd40014259ac3fd0223f7feb08620b87735f60b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I73d713ec3aa62ae207640ac7e5550e5407f5afa2
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
BUG=b:177399759
TEST=firmware_EventLog passed on asurada
BRANCH=none
Change-Id: I759f9030f525fa9e34ed542198a9dba8f25909f5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Rewrite early QPI initialisation to account for variables in the
register values. Trace replays did not capture these relationships.
Tested on out-of-tree HP 630, still boots.
Change-Id: I5d393e8222be286ab4d4dc074d85f721b07bbca4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49586
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I7ed24e76df3c0542b04c0f072c1eaacceea4b71f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49965
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The device function is missing in the PCI device table in the PPR, but
is present in the hardware. Verified on a Mandolin board with PCO APU.
The corresponding ticket for the PPR is DESPCSOC-6667.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The PSP soft fuse bit 6 doesn't do what the comment above it says. See
NDA document #55758 for details.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic84cf6e1eee30af92cd700dc4bf78290143bf88b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
DPR size is in MiB, but the range boundaries are expressed in KiB. In
addition, DPR and TSEG use the same attributes, so unify both regions.
Also improve a comment about DPR, since `is special` is uninformative.
Change-Id: I4479483e17890b5a4c39165138fa1c5f8215bc84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46987
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The per-lane registers need to be modified in some cases. Also, MRC
does not have any delay after the loop, so remove it.
Tested on out-of-tree HP 630, still boots.
Change-Id: If02e171d2e999f4a5be5b43ecc5aafe8ca092951
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49585
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Given that the PCI devices/registers being accessed are about QuickPath,
this code must be part of QuickPath init. Move it with the other code.
Tested on out-of-tree HP 630, still boots.
Change-Id: I0854e7f0ce3070eed1adc0603f68a9d1552204d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49584
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Transform the existing functions so that their functionality does not
overlap. Also, deduplicate printing these values in debug builds.
Tested on out-of-tree HP 630, still boots.
Change-Id: I3f50dcf56284c9648b116bc5aacc0adf2d863b5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49583
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The platform performs a CPU-only reset after initializing QPI (QuickPath
Interconnect) and before actually performing raminit. The state is saved
in the sticky scratchpad register at MCHBAR + 0x2ca8.
Relocate some QuickPath init to a separate file. All moved functions are
only used within QPI init code, and had to be relocated in one commit.
Tested on out-of-tree HP 630, still boots.
Change-Id: I48e3517285d8fd4b448add131cd8bfb80641e7ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49582
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I14c5671dfc611209e28f25f38b4e82d11aef88ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49580
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Introduce the `get_bits_420` helper to avoid doing the same thing in
three different ways, and also correct a related register write.
Tested on out-of-tree HP 630, still boots.
Change-Id: Iec87f080714f0f07f5d43200ec01d6d3f31e8120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49579
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Dummy reads followed by writes are actually read-modify-write operations
in disassembled binaries. Handling of the scratchpad register 0x2ca8 is
still nonsense, but that should be taken care of in a separate commit.
Tested on out-of-tree HP 630, still boots.
Change-Id: Ie33f42ecdb25febf3c82febeca13662232dea9ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45606
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We only need to toggle one bit at a time. Introduce `rmw_500` to
simplify the code. The rank population doesn't seem to matter.
Tested on out-of-tree HP 630, still boots.
Change-Id: Ic1a680dae90889c84c9b2c536745e254475ff878
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49577
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Since Elkhart Lake and Alder Lake use alphabetical ordering, apply that
to the other platforms. Now there are only two versions of smmrelocate.c
across seven different platforms. They will be unified in follow-ups.
Change-Id: I5425323a6d4eecaa97916b6f2683dff57392157c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50935
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use the same log message everywhere for consistency.
Change-Id: I9d2230bc92313269470839486f6644f16e837d7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50934
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Looks like smmrelocate.c is nearly identical across multiple platforms.
This is done to be able to deduplicate smmrelocate.c in the follow-ups.
Change-Id: I2edc64c9eabc3815b12a2e3cffb03cba2228eea0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50933
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ie534a05f8d3945492ab5b817522486cdcd3c4cab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50932
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I78d1b15deac2b80cc319dcfc5ab6bf419e2d61db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50931
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I01035ad88dc6ba702fde2c58aa0093214a57e482
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50930
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The array was copied from Broadwell, which uses a different bit layout
for SMI_STS. Copy the array from Cannonlake instead, because Skylake
uses the same bit layout. This could be deduplicated in the future.
Change-Id: I1c4df727c549eac6f361754d6011bf302da64c5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50929
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use different verb tables depending on board revision.
For board revision R03 and older use the existing verb tables.
For revisions newer than R03 use the new verb tables and also
apply the dynamic audio configuration recently added.
Also do the following:
* Use correct NID port mapping
* Fix verb count in ALC888 header
* Fix NID in Intel codec verbs
Change-Id: I24ea9149eb2cddb815ff82744a351c926a94aaef
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
List of changes:
1. Add mainboard Kconfig to Kconfig.name files
2. Handle mainboard names in Kconfig file for adlrvp
3. Created a new devicetree.cb for Adlrvp-m.
3. Add override devicetree for ADL-M RVP.
4. Configure proper PCI and USB ports as per schematics for ADL-M
BUG=None
BRANCH=None
TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec.
Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add ELAN touchpad into devicetree for storo.
BUG=b:177393444
BRANCH=dedede
TEST=built storo firmware and verified touchpad function
Change-Id: I95780d23b9ea5425d7762e850c25fd14d8a9caf4
Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50979
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Follow vendor suggestion to configure IRQs as level triggered to prevent TS lost.
BUG=b:171440909
BRANCH=dedede
TEST=1. emerge-dedede coreboot chromeos-bootimage
2. power on, suspend DUT to check TS is functional
Change-Id: I07a5cd5e2ac9caad9dbcca12e05bda7f08f42dce
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
associated GPIO configuartion
Adding LTE module support into devicetree and associated GPIO configuartion.
BUG=b:177385043
BRANCH=dedede
TEST=LTE function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I4d91045176fd6413ac6a5eed70289a5668e5b94f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
speaker amplifier support into devicetree
Adding audio codec and speaker amplifier support into devicetree
BUG=b:177479444
BRANCH=dedede
TEST=audio function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I90ff3a107278c711a085d04ae708e41f95d454ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Adding Touchpad support into devicetree.
BUG=b:177348842
BRANCH=dedede
TEST=touchpad function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I7ecafb5b3e39ff2ed9e176531bd0939f830a6397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
and associated GPIO configuration
Adding camera support in devicetree and associated GPIO configuration.
BUG=b:177351873
BRANCH=dedede
TEST=camera function is OK
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I539e969e180c8c71d4b54b50519d2e1ff25415f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Post boot SAI PCR access to ITSS polarity regsiter is locked.
Restore of ITSS polarity does not take effect anyways. Hence
removing the related programming.
Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Configuring GPP_G7 as NC causes SD card detection issue.
Remove the GPP_G7 override and keep the baseboard
configuration as native function (SDIO_WP).
BUG=b:179733306
BRANCH=firmware-dedede-13606.B
TEST=Built and verified Kingston 64G SD card operation on boten
Change-Id: Ied319437de0e867ee9821d0151ff0c76834c4726
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This makes it clear what this function pointer is used for.
Change-Id: I2090e164edee513e05a9409d6c7d18c2cdeb8662
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51009
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.
Change-Id: I0443a45522b2267e8e23b28e4e2033f25a7ccbf0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The .disable function pointer is only referenced inside
set_vga_bridge_bits() and is used to unset VGA decoding on the
internal GFX device.
Change-Id: I6888b08ac11ba2431601fa179d063cee0bb93370
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add MMIO offsets for USB2 and USB3 port status registers, for
both north (TCSS) and south (PCH) XHCI controllers; implement
soc_get_xhci_usb_info() to return the appropriate entries for
elog.
Change-Id: I5ceb73707a0af0542a07027fd5c873a9658b19d6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This adds functionality to mask certain IIO errors on the root complex as recommended by HW vendor.
Tested on DeltaLake mainboard. Boot to OS, verify IIO mask registers are programmed correctly.
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Change-Id: I99f05928930bbf1f617c2d8ce31e8df2a6fd15e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
As one option is consumed by MPinit, update the soc config even earlier.
Tested on Prodrive hermes:
Turbo can be disabled and cores won't exceed their base frequency.
Change-Id: I9f444c3b91d2ee1a613ebac1922f1e6b60363c0b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
With an external GPU connected via the expresscard slot this is
required.
Change-Id: I154721ff2c712cfe7eb79b8bf8943182c8c36548
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Let's not have 7 boards of all use a different name for
the .enable_dev function in mainboard chip_operations.
Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The semantics of pirq_setup() from previous platforms was to
only setup the global pointers for PIC and APIC tables, not
to create or modify the tables themselves.
Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
