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2011-05-10This replaces the fixed shift values in the apic timer init with macros.Vikram Narayanan
Signed-off-by: Vikram Narayanan <vikram186@gmail.com> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-09Adds RS740 HT and internal graphics PCI ids.Ivaylo Valkov
Signed-off-by: Ivaylo Valkov <ivaylo@e-valkov.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-07ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 ↵Kerry She
platform. Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-07RS780 DDI Lanes configure support,Kerry She
and remove RS780 get_cpu_rev(). Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-07SB800 CIMX code can share the AGESA V5 lib code,Kerry She
some platform only use sb800 cimx code, not use AGESA v5 code. for such platform, one can compile the sb800 cimx and AGESA v5 lib code. Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-071. move _mm_clflush_fs() to __SSE3__ block, because __builtin_ia32_sfence() ↵Kerry She
is the sse built-in function 2. move the Amd Lib functions using sse build-in functions to __SSE3__ block Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-07put the amdlib and agesa constant to .rodata segment.Kerry She
so amdlib.c would not complain "Do not use global variables in romstage" Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6557 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-05Adds VOID to empty parameter lists to get rid of some build warnings.Frank Vibrans
This change modifies a collection of files by adding the VOID parameter to empty parameter lists to cut down on the number of warnings produced when compiling the AMD Agesa code. This should cut down the number of warnings by about 1100 each for rom- and ramstage. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-05Remove AMD Agesa requirement for standard include filesFrank Vibrans
This change modifies Makefile.inc to add the -nostdinc flag to the default CFLAGS value and removes the test for non-AMD Agesa builds. Other code is added to the gcc-intrin.h file in the Agesa Include folder to make the requirement for the standard includes obsolete from the Agesa perspective. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-03Enable caching for ROM area in model_6ex/cache_as_ram.incSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-03i82801gx: enable SPI prefetchingSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-02Add option 'compress ramstage'Sven Schnelle
Add an option to make compression of ramstage configurable. Right now it is always compressed. On my Thinkpad, the complete boot to grub takes 4s, with around 1s required for decompressing ramstage. This is probably caused by the fact the decompression does a lot of single byte/word/qword accesses, which are really slow on SPI buses. So give the user the option to store ramstage uncompressed, if he has enough memory. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-28Thinkpad: Enable Battery eventsSven Schnelle
Enable the following events for battery objects on Thinkpad X60/T60: 24: BAT0 critical 25: BAT1 critical 4A: BAT0 present 4B: BAT0 state change 4C: BAT1 present 4D: BAT1 state change Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27X60: enable Ultrabay if device is plugged inSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27T60: enable Ultrabay if device is plugged inSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27Lenovo PMH7: add pmh7_ultrabay_power_enable()Sven Schnelle
Can be used to enable/disable Ultrabay power on Thinkpads who control that with the PMH7. (i.e. T60) Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27Lenovo H8: add h8_ultrabay_device_present()Sven Schnelle
returns 1 if a CDROM/HDD device is plugging in the ultrabay. Return 0 if there's a battery or superio extensions plugged in. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-26Add support for memory mapped UARTs to coreboot and add the OXPCIe952 as anStefan Reinauer
example. This newer version reflects the recent changes to further simplify the console code and partly gets rid of some hacks in the previous version. Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-22Fix of fix copy and paste errors in ne2k.c (r6512 by stepan)Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-22fix typo ttys0_index -> b_indexStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-22Get rid of all but one (I/O mapped) UART init functions.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-22The UART divider should be calculated based on the base frequencyStefan Reinauer
and baudrate, not hardcoded in addition to that. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21more ifdef -> if fixes.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21more ifdef -> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21some ifdef --> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20drop dead code from sb800 bootblockStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20drop excessive newline in uart8250.cStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20Simplify coreboot's console/console.hStefan Reinauer
- shift most (romcc) code out of console.h into arch/x86/lib/romcc_console.c - rename arch/x86/lib/printk_init.c to .../romstage_console.c - drop FUNCTIONS_FOR_PRINT since __console_tx_* are already functions, so there should not be any side effects to eliminating another indirection. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20run uart_init() from console_init, just like the other console ↵Stefan Reinauer
initialization functions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20Add Lenovo ThinkPad T60Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20PC87384: remove unused init functionSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: remove latency/bridge control/cacheline size settingsSven Schnelle
Those settings should be handled by the generic PCI/Cardbus code, and not by the driver itself. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: use cardbus_read_resources()/cardbus_enable_resources()Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: use pci_ops set_subsystem instead of custom codeSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: add PCI1510 device IDsSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: use devicetree register configurationSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20drop dead uart init code.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20fix boards that still had some uart init remaindersStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Drop baud rate init to an arbitrary baud rate from Super I/O code. ↵Stefan Reinauer
See discussion at http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html config->com1, devicetree.cb cleanup and init_uart8250() removal will follow once this patch is comitted Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Updated to drop com1, com2.... from config structure and devicetree.cb git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Lenovo PMH7: add pmh7_touchpad_enable()Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Fix compilation of all i82371eb boards when ACPI tables aren't generatedIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19The "temp" will be used later. So it has to be calculated correctly.Zheng Bao
Comment by Peter, The variable name "temp" unfortunately does not explain what the value is. The commit message also does not have hints. Hopefully in the future it's possible to also use a brief moment to improve the clarity of the code, while it is already being fixed for some other reason. Ie. fixing up variable names, writing particularly informative commit messages, or of course both at the same time! :) Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Recently the 3 projects using the new AMD reference code have beenScott Duplichan
failing the check for globals (or statics) in romstage. This causes ASRock E350M1, AMD Inagua, and AMD Persimmon builds to fail with the message "Do not use global variables in romstage". The message is working as intended. It is detecting data declared as 'static' when 'static const' was intended. The code executes correctly because it never tries to modify the data. To make reference code updates easy, it is probably best to avoid modifying the AMD provided code if possible. The following change bypasses the "Do not use global variables in romstage" check for the AMD reference code only. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6516 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Fix some more misuses of ifdef/if definedStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19cleanup wrong use of defined() after exporting all variables in KconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18fix copy and paste errors in ne2k.cStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-17Lenovo H8 EC: add missing systemstatus.asl includeSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-17PMH7: Add dock event controlSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-16bootblock updates: ↵Stefan Reinauer
- allow CPU to define bootblock code, too. - drop unneeded __PRE_RAM__ define - move CBFS specific code out of bootblock_common.h into cbfs.h Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15sorry for breaking the tree. Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15comment cosmetics in bootblock.ldStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15add FILO easy payload optionStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15Handle drivers/ equally to any other sub directory.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15fix mainboards that were including earlymtrr.c without actually using it.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14drop half an uart8250 implementation from smiutil and use the common code Stefan Reinauer
for that instead. This also allows using non-uart8250 consoles for smi debugging. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14fix coreboot compilation without serial console enabled.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14earlymtrr.c: wipe some dead code, use names instead of numbers and someStefan Reinauer
cosmetics. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14add some comments to walkcbfs.SStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14- drop remaining CONFIG_ROM_IMAGE_SIZEStefan Reinauer
- re-enable .data section check for bootblock. - rename ldscript_fallback_cbfs.lb to bootblock.ld Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCHStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14nvidia mcp55: drop unused dbg_info Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14cosmetic cleanup of sis966 usb2 code Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14Use symbolic names for some MTRR bits instead of numbers in CAR codeStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-13Lenovo H8 EC: add missing include for thermal.aslSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-12Lenovo H8 EC: Set fancontrol to Automatic managementSven Schnelle
My Notebook gets far to hot without fan, so just enable automatic fan control by default. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-12PC87384: add GPIO definesSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-12Use TOM2 for highest sysmem setting for northbound memory routing (DMA). ↵Marc Jones
This fixes 4GB memory issues. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Kerry she <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11Unify use of post_codeAlexandru Gagniuc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11PMH7: Add chip configSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11EC: Add Lenovo H8Sven Schnelle
Move the EC support code from the X60 mainboard to a generic driver, as this EC is used in many thinkpads. Also move the ACPI code to this directory for this reason. This patch also adds a chip config, so that the initial setting for basic register can be specified in devicetree.cb Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10i945: improve get_top_of_ram()Sven Schnelle
The current version doesn't honor TSEG, and fails to report the correct top of RAM if IGD is disabled. This is because it uses the BSM (base of stolen RAM) register. In that case, we should use the TOLUD register. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-05X60: use pnp_write_config() instead of custom functionSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-05X60: move ec version info code to log_ec_version()Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: assert audio mute before entering SuspendSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: log firmware versionSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: blink suspend LED during resumeSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: we have ACPI_RESUMESven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: deassert audio mute on bootSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01remove swp files accidently addedSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01X60: add dock code for Ultrabase X6Sven Schnelle
Move the old docking code from romstage.c to dock.c, and use that code both in romstage and SMM code. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01Add GPIO definitions to PC87392 superioSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01ICH7: Fix register naming errorSven Schnelle
There's an off-by-one error in the ACPI GP_LVL declaration: it declares GL00 with a bit count of 6, and continues with GP07 afterwards. This should be GP06, as the first bitfield covers GP00-GP05. While at it, change it to GP00-GP05, as right now GL00 isn't used, and single bitfield are more usable here. Also adjust the Getac P470, as this is the only user of those defintions right now. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-29BUILD: add missing config.h dependencySven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28Add support for Supermicro H8scm.Zheng Bao
It is AMD C32 + SR5650 + SP5100. It is created by svn copy amd/tilapia_fam10. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28Add the SR5650 & SP5100 to the Kconfig and Makefile.incZheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28Add AMD C32 support.Zheng Bao
It is based on other existing Fam10 code. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.Zheng Bao
Since the SB700 has changed to sb7xx_51xx, change legacy name in other mainboard. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27Add AMD SR56x0 support.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-27This is for board Supermicro H8scm. The code was done by existing chips andZheng Bao
superiotool. WPCM450 is more like an EC. SuperIO is just a part of multi-features. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-21X60: Add notification for LID objectsSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-21X60: remove beep call from _Q26/_Q27Sven Schnelle
no need to trigger sound, the EC takes care of generating the annoying AC state beep if enabled in the sound mask. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-17Fix breaking the build after removing files in tthe previous checkin. Marc Jones
Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-17Perform cleanup and file shrinkage of the AMD AGESA code.Frank.Vibrans
Signed-off-by: Frank.Vibrans <frank.vibrans@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-17Fix power_on_after_fail handling on AMD SB600Josef Kellermann
Bit 0 of pm reg#74 have to be set turn on system after power resumes. See '42661_sb600_rrg_nda_3.02.pdf' (or '46155_sb600_rrg_pub_3.03.pdf') for details, look for 'PwrFailShadow'. [Patrick: I didn't include the get_options reorganization as get_option doesn't overwrite "on" if power_on_after_fail isn't found in CMOS. Style changes were also left out.] Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-15X60: Clear EC events when wake GPE is triggeredSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-15ACPI EC: add ec_query functionSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14X60: LPC bus is LPCB, not LPCSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14X60: fix typo in dsdt.aslSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 01:31:27 +0000