more ifdef -> if fixes

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

25 files changed, 46 insertions, 46 deletions

diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c
index 20917b6f40..91525d5935 100644
--- a/src/arch/x86/lib/exception.c
+++ b/src/arch/x86/lib/exception.c
@@ -1,7 +1,7 @@
 #include <console/console.h>
 #include <string.h>
 
-#if defined(CONFIG_GDB_STUB) && CONFIG_GDB_STUB == 1
+#if CONFIG_GDB_STUB
 
 /* BUFMAX defines the maximum number of characters in inbound/outbound buffers.
  * At least NUM_REGBYTES*2 are needed for register packets
diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index e39fe8fd0a..3f64209746 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -91,7 +91,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 
 // XXX this decision should probably be made elsewhere, and
 // it's the C3, not the EPIA this depends on.
-#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT
+#if CONFIG_EPIA_VT8237R_INIT
 #define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
 #else
 #define IOAPIC_INTERRUPTS_ON_FSB
diff --git a/src/console/post.c b/src/console/post.c
index 49f6311303..3872c2d4fe 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -26,8 +26,8 @@
 
 void post_code(uint8_t value)
 {
-#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
-#if CONFIG_CONSOLE_POST==1
+#if !CONFIG_NO_POST
+#if CONFIG_CONSOLE_POST
 	print_emerg("POST: 0x");
 	print_emerg_hex8(value);
 	print_emerg("\n");
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 424bd93e7c..48992969f0 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -281,7 +281,7 @@ clear_fixed_var_mtrr_out:
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#if CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index fc4eb8ae74..2310d7d9d2 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -231,7 +231,7 @@ clear_fixed_var_mtrr_out:
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#if CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index e9820c9aeb..da14db22ae 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -102,7 +102,7 @@ clear_mtrrs:
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#if CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
@@ -128,7 +128,7 @@ clear_mtrrs:
 	movl	%eax, %cr0
 
 	/* Set up the stack pointer. */
-#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
+#if CONFIG_USBDEBUG
 	/* Leave some space for the struct ehci_debug_info. */
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 0ee26fcdd2..0906bc0e5f 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -102,7 +102,7 @@ clear_mtrrs:
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#if CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
@@ -128,7 +128,7 @@ clear_mtrrs:
 	movl	%eax, %cr0
 
 	/* Set up the stack pointer. */
-#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
+#if CONFIG_USBDEBUG
 	/* Leave some space for the struct ehci_debug_info. */
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index a7605cc689..2f13d355fd 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -109,7 +109,7 @@ clear_mtrrs:
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#if CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
@@ -135,7 +135,7 @@ clear_mtrrs:
 	movl	%eax, %cr0
 
 	/* Set up the stack pointer. */
-#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
+#if CONFIG_USBDEBUG
 	/* Leave some space for the struct ehci_debug_info. */
 	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 6303162cf0..20b3220f87 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -110,7 +110,7 @@ clear_fixed_var_mtrr_out:
 	movl	$(~(CacheSize - 1) | MTRRphysMaskValid), %eax
 	wrmsr
 
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#if CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index adbb5fd776..37b45e6376 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -296,7 +296,7 @@ void run_bios(struct device *dev, unsigned long addr)
 	printk(BIOS_DEBUG, "... Option ROM returned.\n");
 }
 
-#if defined(CONFIG_GEODE_VSA) && CONFIG_GEODE_VSA
+#if CONFIG_GEODE_VSA
 #include <cpu/amd/lxdef.h>
 #include <cpu/amd/vr.h>
 #include <cbfs.h>
diff --git a/src/devices/oprom/yabel/biosemu.c b/src/devices/oprom/yabel/biosemu.c
index f1f19c46be..8d7795971f 100644
--- a/src/devices/oprom/yabel/biosemu.c
+++ b/src/devices/oprom/yabel/biosemu.c
@@ -58,37 +58,37 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad
 	int i = 0;
 #if CONFIG_X86EMU_DEBUG
 	debug_flags = 0;
-#if defined(CONFIG_X86EMU_DEBUG_JMP) && CONFIG_X86EMU_DEBUG_JMP
+#if CONFIG_X86EMU_DEBUG_JMP
 	debug_flags |= DEBUG_JMP;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_TRACE) && CONFIG_X86EMU_DEBUG_TRACE
+#if CONFIG_X86EMU_DEBUG_TRACE
 	debug_flags |= DEBUG_TRACE_X86EMU;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_PNP) && CONFIG_X86EMU_DEBUG_PNP
+#if CONFIG_X86EMU_DEBUG_PNP
 	debug_flags |= DEBUG_PNP;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_DISK) && CONFIG_X86EMU_DEBUG_DISK
+#if CONFIG_X86EMU_DEBUG_DISK
 	debug_flags |= DEBUG_DISK;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_PMM) && CONFIG_X86EMU_DEBUG_PMM
+#if CONFIG_X86EMU_DEBUG_PMM
 	debug_flags |= DEBUG_PMM;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_VBE) && CONFIG_X86EMU_DEBUG_VBE
+#if CONFIG_X86EMU_DEBUG_VBE
 	debug_flags |= DEBUG_VBE;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_INT10) && CONFIG_X86EMU_DEBUG_INT10
+#if CONFIG_X86EMU_DEBUG_INT10
 	debug_flags |= DEBUG_PRINT_INT10;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_INTERRUPTS) && CONFIG_X86EMU_DEBUG_INTERRUPTS
+#if CONFIG_X86EMU_DEBUG_INTERRUPTS
 	debug_flags |= DEBUG_INTR;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS) && CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS
+#if CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS
 	debug_flags |= DEBUG_CHECK_VMEM_ACCESS;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_MEM) && CONFIG_X86EMU_DEBUG_MEM
+#if CONFIG_X86EMU_DEBUG_MEM
 	debug_flags |= DEBUG_MEM;
 #endif
-#if defined(CONFIG_X86EMU_DEBUG_IO) && CONFIG_X86EMU_DEBUG_IO
+#if CONFIG_X86EMU_DEBUG_IO
 	debug_flags |= DEBUG_IO;
 #endif
 
@@ -309,7 +309,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad
 	 * some boot device status in AX (see PNP BIOS Spec Section 3.3
 	 */
 	DEBUG_PRINTF_CS_IP("Option ROM Exit Status: %04x\n", M.x86.R_AX);
-#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG
+#if CONFIG_X86EMU_DEBUG
 	DEBUG_PRINTF("Exit Status Decode:\n");
 	if (M.x86.R_AX & 0x100) {	// bit 8
 		DEBUG_PRINTF
diff --git a/src/devices/oprom/yabel/compat/functions.c b/src/devices/oprom/yabel/compat/functions.c
index 50bc7b9192..db37fbc6f9 100644
--- a/src/devices/oprom/yabel/compat/functions.c
+++ b/src/devices/oprom/yabel/compat/functions.c
@@ -23,8 +23,8 @@
 
 #define VMEM_SIZE (1024 * 1024) /* 1 MB */
 
-#if !defined(CONFIG_YABEL_DIRECTHW) || (!CONFIG_YABEL_DIRECTHW)
-#ifdef CONFIG_YABEL_VIRTMEM_LOCATION
+#if !CONFIG_YABEL_DIRECTHW
+#if CONFIG_YABEL_VIRTMEM_LOCATION
 u8* vmem = (u8 *) CONFIG_YABEL_VIRTMEM_LOCATION;
 #else
 u8* vmem = (u8 *) (16*1024*1024); /* default to 16MB */
diff --git a/src/devices/oprom/yabel/debug.h b/src/devices/oprom/yabel/debug.h
index fea1fb7a3b..9361553da7 100644
--- a/src/devices/oprom/yabel/debug.h
+++ b/src/devices/oprom/yabel/debug.h
@@ -66,7 +66,7 @@ static inline void set_ci(void) {};
 // set to enable tracing of JMPs in x86emu
 #define DEBUG_JMP 0x2000
 
-#if defined(CONFIG_X86EMU_DEBUG) && CONFIG_X86EMU_DEBUG
+#if CONFIG_X86EMU_DEBUG
 
 #define CHECK_DBG(_flag) if (debug_flags & _flag)
 
diff --git a/src/devices/oprom/yabel/device.h b/src/devices/oprom/yabel/device.h
index b6ec1e3df8..edee44d20e 100644
--- a/src/devices/oprom/yabel/device.h
+++ b/src/devices/oprom/yabel/device.h
@@ -62,7 +62,7 @@ typedef struct {
 typedef struct {
 	u8 bus;
 	u8 devfn;
-#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
 	struct device* dev;
 #else
 	u64 puid;
@@ -84,7 +84,7 @@ typedef struct {
 } biosemu_device_t;
 
 typedef struct {
-#ifdef CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
 	unsigned long info;
 #else
 	u8 info;
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index d33b6da62e..cca2be1b27 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -9,7 +9,7 @@ void cpu_initialize(void);
 void initialize_cpus(struct bus *cpu_bus);
 void secondary_cpu_init(void);
 
-#if !defined(CONFIG_WAIT_BEFORE_CPUS_INIT) || CONFIG_WAIT_BEFORE_CPUS_INIT==0
+#if !CONFIG_WAIT_BEFORE_CPUS_INIT
 	#define cpus_ready_for_init() do {} while(0)
 #else
 	void cpus_ready_for_init(void);
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 5f0a8f2e4a..44a2223738 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -69,7 +69,7 @@ void x86_setup_fixed_mtrrs(void);
 
 #if !defined (__ASSEMBLER__)
 #if defined(CONFIG_XIP_ROM_SIZE)
-# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+# if CONFIG_TINY_BOOTBLOCK
    extern unsigned long AUTO_XIP_ROM_BASE;
 #  define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 # else
diff --git a/src/include/lib.h b/src/include/lib.h
index 1acb114dc6..ba9684a0c1 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -40,7 +40,7 @@ void ram_check(unsigned long start, unsigned long stop);
 void quick_ram_check(void);
 
 /* Defined in romstage.c */
-#if defined(CONFIG_CPU_AMD_LX) && CONFIG_CPU_AMD_LX
+#if CONFIG_CPU_AMD_LX
 void cache_as_ram_main(void);
 #else
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c
index 5cf703bf26..a8fe377125 100644
--- a/src/lib/fallback_boot.c
+++ b/src/lib/fallback_boot.c
@@ -28,7 +28,7 @@ void set_boot_successful(void)
 
 void boot_successful(void)
 {
-#if defined(CONFIG_BOOTSPLASH) && CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER
+#if CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER
 	void vbe_textmode_console(void);
 
 	vbe_textmode_console();
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index d7d6157357..9ccc56b2b2 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1111,7 +1111,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
 	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0)
 		return 0;
 #else
-#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) || (CONFIG_INTERLEAVE_CHIP_SELECTS == 0)
+#if !CONFIG_INTERLEAVE_CHIP_SELECTS
 	return 0;
 #endif
 #endif
@@ -2379,7 +2379,7 @@ static void set_ecc(const struct mem_controller *ctrl,
 		dcl &= ~DCL_DimmEccEn;
 	}
 #else // CMOS_VSTART_ECC_memory not defined
-#if defined(CONFIG_ECC_MEMORY) && (CONFIG_ECC_MEMORY == 0)
+#if !CONFIG_ECC_MEMORY
 	dcl &= ~DCL_DimmEccEn;
 #endif
 #endif
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index acb40dc622..df4010eafd 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -24,7 +24,7 @@
 #include <delay.h>
 #include "cn700.h"
 
-#ifdef CONFIG_DEBUG_RAM_SETUP
+#if CONFIG_DEBUG_RAM_SETUP
 #define PRINT_DEBUG_MEM(x)		print_debug(x)
 #define PRINT_DEBUG_MEM_HEX8(x)		print_debug_hex8(x)
 #define PRINT_DEBUG_MEM_HEX16(x)	print_debug_hex16(x)
diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c
index 421716cb6c..3894d67c01 100644
--- a/src/northbridge/via/vx800/early_smbus.c
+++ b/src/northbridge/via/vx800/early_smbus.c
@@ -49,7 +49,7 @@
 
 #define SMBUS_DELAY()		outb(0x80, 0x80)
 
-#ifdef CONFIG_DEBUG_SMBUS
+#if CONFIG_DEBUG_SMBUS
 #define PRINT_DEBUG(x)		print_debug(x)
 #define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
 #else
diff --git a/src/pc80/i8254.c b/src/pc80/i8254.c
index e5dc40b56b..ca993f494c 100644
--- a/src/pc80/i8254.c
+++ b/src/pc80/i8254.c
@@ -35,7 +35,7 @@ void setup_i8254(void)
 	outb(0x12, TIMER1_PORT);
 }
 
-#ifdef CONFIG_UDELAY_TIMER2
+#if CONFIG_UDELAY_TIMER2
 static void load_timer2(unsigned int ticks)
 {
         /* Set up the timer gate, turn off the speaker */
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 7345cdeca3..a5e76c7a05 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -149,7 +149,7 @@ static void sb7xx_51xx_lpc_init(void)
 	reg32 |= 1 << 20;
 	pci_write_config32(dev, 0x64, reg32);
 
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
 	post_code(0x66);
 	dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);     /* LPC Controller */
 	reg8 = pci_read_config8(dev, 0xBB);
@@ -163,7 +163,7 @@ static void sb7xx_51xx_lpc_init(void)
 	// XXX Serial port decode on LPC is hardcoded to 0x3f8
 	reg8 = pci_read_config8(dev, 0x44);
 	reg8 |= 1 << 6;
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
 #if CONFIG_TTYS0_BASE == 0x2f8
 	reg8 |= 1 << 7;
 #endif
@@ -369,7 +369,7 @@ static void sb700_devices_por_init(void)
 {
 	device_t dev;
 	u8 byte;
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
 	u32 dword;
 #endif
 
@@ -505,7 +505,7 @@ static void sb700_devices_por_init(void)
 	/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
 	pci_write_config8(dev, 0x50, 0x01);
 
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
 	/* SP5100 default SATA mode is RAID5 MODE */
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0);
 	/* Set SATA Operation Mode, Set to IDE mode */
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 273aabc128..3e596c240d 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -63,7 +63,7 @@ static void lpc_init(device_t dev)
 	/* Disable LPC MSI Capability */
 	byte = pci_read_config8(dev, 0x78);
 	byte &= ~(1 << 1);
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
 	/* Disable FlowContrl, Always service the request from Host
 	 * whenever there is a request from Host pending
 	 */
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 4838d93658..89eba4b168 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -190,7 +190,7 @@ static void sata_init(struct device *dev)
 	byte |= 7 << 0;
 	pci_write_config8(dev, 0x4, byte);
 
-#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100
+#if CONFIG_SOUTHBRIDGE_AMD_SP5100
 	/* Master Latency Timer */
 	pci_write_config32(dev, 0xC, 0x00004000);
 #endif