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2022-02-17drivers/intel/usb4/retimer/retimer.c: Remove space before tabElyes Haouas
Spaces before tabs are not allowed. Change-Id: I1aa8490cb81a77f48d69c16c175eb4fec70dc0db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62054 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17soc/intel/alderlake: Add CNVi common driver KconfigVarshit B Pandya
Alder Lake has CNVI device. Select SOC_INTEL_COMMON_BLOCK_CNVI for Alder Lake. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6bf2292e870c990deb63fbf6e841ae7c5c63b3a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-17soc/mediatek/mt8195/include/soc/addressmap.h: Remove space before tabElyes Haouas
Spaces before tabs are not allowed. Change-Id: I2732c01fd87c56227d47a4c0104de8e227b0cc34 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62018 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17amd/common/block/gpio/gpio: don't use -1 as bitmask in gpio_or32Felix Held
The and-mask passed to the gpio_update32 call needs all 32 bits to be set to ones. When building as 32 bit binary the -1UL will result in the needed bit mask, but for a 64 bit build the constant would have 64 bits set to ones which then gets truncated to 32 bits causing a compiler error. Use 0xffffffff as bit mask instead which behaves correctly in both cases and also clarifies what this is doing. TEST=Timeless build for Chausie results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17amd/common/block/spi/fch_spi_ctrl: use uintptr_t for addressesFelix Held
This fixes a build failure when trying to build the code in 64 bit mode. TEST=Timeless build for Chausie results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-16mb/google/herobrine: Add Gigadevice SPI PartShelley Chen
BUG=b:182963902 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I73dc695afb7aa2b32aa966070eb057c828073d47 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16mb/google/herobrine: Alphabetize SPI_FLASH configsShelley Chen
BUG=b:182963902 BRANCH=None TEST=None Change-Id: Ia73460d335e859644511b7e9ca80111a919baf2c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-02-16soc/amd/cezanne/psp_verstage/uart: Fix off by 1 errorRaul E Rangel
We only allow index = {0, 1}. Fix the check. BUG=b:215599230 TEST=Build guybrush BRANCH=guybrush Found-by: Coverity CID 1469611 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I59615ab39faeded43b3803b4450c84ab8a8b81ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/61988 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16compiler.h: Define a __fallthrough statementArthur Heymans
Change-Id: I0487698290992162fac6bb74b5082901415e917e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16mb/google/brya/var/agah: Select PCIEXP_SUPPORT_RESIZABLE_BARSTim Wawrzynczak
The google/agah variant will use a peripheral that will require the use of the PCIe Resizable BAR feature from the PCIe spec. Thus, select the new Kconfig option to enable it. The appropriate Resizable BAR size will be updated later. BUG=b:214443809 TEST=build Change-Id: I9cf86ba3160ae5018655b5d366e89f4273b30b94 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-16device: Add support for PCIe Resizable BARsTim Wawrzynczak
Section 7.8.6 of the PCIe spec (rev 4) indicates that some devices can indicates support for "Resizable BARs" via a PCIe extended capability. When support this capability is indicated by the device, the size of each BAR is determined in a different way than the normal "moving bits" method. Instead, a pair of capability and control registers is allocated in config space for each BAR, which can be used to both indicate the different sizes the device is capable of supporting for the BAR (powers-of-2 number of bits from 20 [1 MiB] to 63 [8 EiB]), and to also inform the device of the size that the allocator actually reserved for the MMIO range. This patch adds a Kconfig for a mainboard to select if it knows that it will have a device that requires this support during PCI enumeration. If so, there is a corresponding Kconfig to indicate the maximum number of bits of address space to hand out to devices this way (again, limited by what devices can support and each individual system may want to support, but just like above, this number can range from 20 to 63) If the device can support more bits than this Kconfig, the resource request is truncated to the number indicated by this Kconfig. BUG=b:214443809 TEST=compile (device with this capability not available yet), also verify that no changes are seen in resource allocation for google/brya0 before and after this change. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I14fcbe0ef09fdc7f6061bcf7439d1160d3bc4abf Reviewed-on: https://review.coreboot.org/c/coreboot/+/61215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v2503_00Ronak Kanabar
The headers added are generated as per Alder Lake N FSP v2503_00. Previous FSP version was v2503_00. Change include: Add following Emmc UPDs in Fsps.h - ScsEmmcEnabled - ScsEmmcHs400Enabled - EmmcUseCustomDlls - EmmcTxCmdDelayRegValue - EmmcTxDataDelay1RegValue - EmmcTxDataDelay2RegValue - EmmcRxCmdDataDelay1RegValue - EmmcRxCmdDataDelay2RegValue - EmmcRxStrobeDelayRegValue BUG=b:213828776 BRANCH=None Change-Id: I617673a0cb12e7165f2f63cce73fff38bc7bf827 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-16mb/google/brya/var/agah: Change ELAN touchpad driver for eKT3744Tony Huang
Change to use i2c/generic to match ELAN FW update script. BUG=b:210970640 TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ib416da6000d9e99f9c37cf497fb1c43e3fca0220 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-16soc/amd/common/block/psp: add PSP commandJason Glenesk
Add PSP command to send SPL fuse command if PSP indicates SPL fusing is required. Also add Kconfig option to enable sending message. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Build an image with an SPL table indicating fusing is required, confirm that PSP indicates fusing required and coreboot sends the appropriate command. A message indicating PSP requested fusing will appear in the log: "PSP: Fuse SPL requested" Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-02-16payloads/external: add skiboot (for QEMU/Power9)Sergii Dmytruk
Add an option to build skiboot as a payload. This makes QEMU Power9 board simpler to use as skiboot is necessary anyway. Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-16soc/intel/alderlake: Correct Alder Lake M/N ESPI device IDKrishna Prasad Bhat
Alder Lake M/N ESPI ID 18 was incorrectly assigned to be 0x5482. Assign it to the correct value. Reference documents: 619501, 645548. Change-Id: I08bd218fd128497825b96aa5b9496826afa620d2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61947 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16mb/google/brya: Update memory DQ mapEric Lai
Follow latest schematic to update the DQ map. BUG=b:218939997 TEST=boot into OS without issue. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If29cc22b1749fb5d602d3ce64bcc1182593d673f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-16drivers/intel/fsp: Set FSP_LOG_LEVEL_ERR_WARN_INFO for DEBUG_RAM_SETUPKane Chen
To get verbose MRC log includes RMT log, we need to set FSP_LOG_LEVEL_ERR_WARN_INFO instead. TEST=tested on gimble, see MRC verbose and RMT log are printed Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Change-Id: I3896f0482dfde090b4e087490b7937683b5de091 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-15mb/starlabs/labtop: Disconnect unused GPIO'sSean Rhodes
Disconnect all GPIO's that aren't connected to anything. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I2050da62f73c0f99fbfef013c22e35225cc480c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15mb/starlabs/labtop: Add comments for GPIOsSean Rhodes
Add comment for each GPIO details its endpoint based on the schematic. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-15ec/starlabs/merlin: Adjust Keyboard Backlight configurationSean Rhodes
* Change TGL Q Event for Keyboard Backlight to Q4A * Change enabled value to 0xdd Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibae95e458f14b9d03ff50cb6222b336fd015d0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15ec/starlabs/merlin: Apply EC settings when suspendingSean Rhodes
Currently, the settings from CMOS were written to the EC, which was pointless. Now, when suspending, the EC values are stored in CMOS when suspending and subsequently restored when waking. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I998d5509cd5e95736468f88663a1423217cf6ddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/60165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15nb/intel/ironlake/raminit_heci.c: Move to southbridge scopeAngel Pons
HECI stuff is in the southbridge, so put the code in there. Rename the file to match the name of the function it provides. Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake: Decouple `setup_heci_uma()` from northbridgeAngel Pons
Remove all northbridge dependencies in the `setup_heci_uma()` function. Update its signature to not pull in raminit internals and drop a dummy read that doesn't have any side-effects (it's probably a leftover from a replay of vendor firmware). This code will be moved into southbridge scope in a follow-up. Change-Id: Ie5b5c5f374e19512c5568ee8a292a82e146e67ad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake/raminit_heci.c: Turn into compilation unitAngel Pons
Remove the temporary `raminit_heci.c` include and make it a proper compilation unit. Export the `setup_heci_uma()` function. Change-Id: Ia6782a0cb5e731d58764d0fa4ee256bfc8cef98a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake: Split out HECI code out of raminitAngel Pons
Move HECI code out of raminit.c into a separate raminit_heci.c file. To preserve reproducibility, use a temporary .c include. This will be gone in a follow-up. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I240552c9628f613fcfa8d2dd09b8e59c87df6019 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-15arch/x86/id.S: Fix building with clangAngel Pons
Commit 0e688b113d7fd98dfdb69cd0a407c8efcd968456 (arch/x86/id.S: Fix building with clang) broke building with GCC 8.3 so this approach should work for both GCC 8.3 and clang. The clang error is: CC bootblock/arch/x86/id.o /tmp/id-35b17a.s:35:7: error: expected relocatable expression .long - ver ^ /tmp/id-35b17a.s:36:7: error: expected relocatable expression .long - vendor ^ /tmp/id-35b17a.s:37:7: error: expected relocatable expression .long - part ^ Change-Id: Ide3d313800641d4d9b5f79127f84d9fdb4ec2b96 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15Revert "arch/x86/id.S: Fix building with clang"Angel Pons
This reverts commit 0e688b113d7fd98dfdb69cd0a407c8efcd968456. Reason for revert: Breaks building with GCC 8.3 which is currently needed to build bootable coreboot images for Ironlake boards: src/arch/x86/id.S: Assembler messages: src/arch/x86/id.S:14: Error: value of 4294967344 too large for field of 4 bytes at 48 src/arch/x86/id.S:15: Error: value of 4294967327 too large for field of 4 bytes at 52 src/arch/x86/id.S:16: Error: value of 4294967318 too large for field of 4 bytes at 56 Change-Id: I9e13b15c062bc6598717382b1fedfa120c6d7209 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblockFelix Held
The SPI ROM REQ/GNT pins are used in systems where the EC and the APU share one flash chip to make sure that not both devices will try to access the flash at the same time. The firmware running before the x86 cores are released from reset has likely already done this, but do it again in bootblock just to be sure. The KBRST_L pin can be used to reset the APU from the EC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5af285ac222ed6625f498d82360f2d1cc522df2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-15soc/intel/cnl: Move selection of DISABLE_HECI1_AT_PRE_BOOT back to mainboardMatt DeVillier
Commit 805956bce [soc/intel/cnl: Use Kconfig to disable HECI1] moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig, but in doing so inadvertently disabled HECI1 for Puff-based boards which previously had HECI1 enabled by default. To correct this, move the Kconfig selection back into the mainboard Kconfig, and set defaults to match values prior to refactoring in 805956bce. Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and ensure Disable HECI1 option defaults to selected for all except Puff. Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/intel/cnl: switch to PMC/IPC for HECI disable on SOC_INTEL_COMETLAKEMatt DeVillier
Commit d6dbd933 [soc/intel/cannonlake: Use SBI msg to disable HECI1] switched CNL-based mainboards from using FSP for HECI disablement to SBI msg, but this causes google/hatch to hang when attempting to unhide p2sb as part of disabling HECI1 via SBI during SMM, so switch to using PMC/IPC method. SOC_INTEL_WHISKEYLAKE and SOC_INTEL_COFFEELAKE do not support PMC disablement method, so they remain using SBI. Test: build/boot google/hatch, verify HECI1 disabled via console log and lspci in booted OS. Change-Id: I06f0eb312b579af4a0fe826403374dcd99689d21 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/intel/common/block/cse: move cse_disable_mei_devices() into disable_heci.cMatt DeVillier
Move cse_disable_mei_devices() from cse_eop.c into heci_disable.c, so that platforms needing to use heci1_disable_using_pmc() can do so without requiring cse_eop.c be unnecessarily compiled in as well. This will allow Cannon Lake platforms to use PMC to disable HECI1 instead of SBI, which is currently causing a hang on google/hatch (and will be changed in a follow-on patch). Test: build test google/{ampton,drobit,eve,akemi} boards to ensure no breakage. Change-Id: Iee6aff570aa4465ced6ffe2968412bcbb5ff3a8d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-02-15mb/google/dedede/var/beadrix: Add LTE power off sequenceTeddy Shih
This change adds LTE power off sequence for beadrix. BUG=b:204882915 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot Change-Id: I11370bf69438465d2230e2633044ba42685a152b Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61329 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15soc/intel/apollolake: Fix overlapping ACPI resource rangesMatt DeVillier
The address space allotted to MCRS in the northbridge needs to be exclusive of the address space allotted to the GPIO controllers in the southbridge, otherwise Windows complains of overlapping resource ranges and disables the GPIO controllers. To prevent overlap, use CONFIG_PCR_BASE_ADDRESS to set the upper bound of MCRS rather than MMCONF. Test: boot Windows 10/11 on google/{reef,ampton} and verify that GPIO controllers are indicated as without fault in Device Manager. Change-Id: I2117054edb448e717b7cbe80958c9c4e6c996e2b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: CoolStar Organization <coolstarorganization@gmail.com>
2022-02-15soc/intel/common/cse: Add `cse_send_end_of_post()` as a public functionSubrata Banik
This patch creates a global function `cse_send_end_of_post()` so that IA common code may get access to this function for sending EOP command to the HECI1/CSE device. Additionally, use static variable to track and prevent sending EOP command more than once in boot flow. BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-15soc/intel/*/pmc: Add `finalize` operation for pmcSubrata Banik
This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs, i.e., Ready to Boot and End Of Firmware. Additionally, move the PMCON status bit clear operation to `.final` ops to cover any such chances where FSP-S Notify Phase or any other later boot stage may request a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=Able to build brya with these changes. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a0b869849d5d8c76031b8999f3d28817ac69247 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/intel/xeon_sp: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I22650f539a1646f93f2c6494cbf54b8ca785d6ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/61652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/intel/apollolake: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I982f669b13f25d1d0e6dfaec2fbf50d3200f74fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/61651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15soc/intel/skylake: Add function to clear PMCON status bitsSubrata Banik
This patch adds an SoC function to clear GEN_PMCON_A status bits to align with other IA coreboot implementations. Additionally, move the PMCON status bit clear operation to finalize.c to cover any such chances where FSP-S NotifyPhase requested a global reset and PMCON status bit remains set. BUG=b:211954778 TEST=None. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-15mb/google/guybrush: Add a mainboard specific SPL tableZheng Bao
Chromebook needs to do some additional check, which is not available in the AMD's PI released SPL table. BUG=b:216096562 Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/intel/elkhartlake: Fix PCR ID for eSPIWerner Zeh
According to the Datasheet Volume 1 (doc #636112, [1]) the PCR port ID for eSPI is 0x72 (see chapter 25.2.2). Fix it in the header file. [1]: https://cdrdv2.intel.com/v1/dl/getContent/636112?explicitVersion=true Test=Read and modify PCR registers of eSPI controller. Change-Id: I5b07ef0f3a285f981791b1f4b4cdbda98ccf05ad Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61841 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15mb/google/brya/var/nereid: Disable LTE-related GPIOsReka Norman
Nereid does not support the LTE sub-board, so disable the LTE-related GPIOs. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6d6b5babeefb7c4b79adab5e756f37616c2338d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya/var/nereid: Initialise overridetreeReka Norman
Add an initial overridetree for nereid based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Change-Id: I7d313439337c84ab1024b3570cc7b57b4255af5d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya/var/nereid: Add H9JCNNNBK3MLYR-N6E for P1 buildReka Norman
Nereid P1 will also use Hynix H9JCNNNBK3MLYR-N6E. Add it to the parts list and regenerate the memory IDs using part_id_gen. BUG=b:217096008 TEST=abuild -a -x -c max -p none -t google/brya -b nereid Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ibacb9dfb336967dd7fffe351d785cbbff9ba8b7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-15mb/google/brya: Create kinox variantDtrain Hsu
Create the kinox variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:215049181 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KINOX Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I68cac421f6299a5f82f2ab51633173648c993060 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61789 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-15drivers/wwan/fm/acpi_fm350gl.c: Fix bit checksAngel Pons
Fix always-true conditions to properly test whether a bit is set. Change-Id: I54b5dbfdbb99a47ef0dfdb9497179f516d6e1f23 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/intel/common/block/pcie/rtd3: Fix bit checksAngel Pons
Fix always-true conditions to properly test whether a bit is set. Change-Id: Ibfeafe222c0c2b39ced5b77f79ceb0c679a471b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15Revert "soc/intel/adl: Skip sending MBP HOB to save boot time"MAULIK V VAGHELA
This reverts commit 9a7fbbc98e8610a0a5314470edd8d5dafe676a06. SkipMbpHob UPD skips generation of MBP Hob within FSP. Skipping MBP Hob generation also skips syncing correct version of chipset data with CSE since FSP uses version information from MBP HOB. In absence of MBP Hob, FSP is unable to get version information and hence chipset data sync is skipped. This creates an issue while platform tries to enter deeper sleep states. BUG=b:215448362 BRANCH=None TEST= FSP can get version information from MBP HOB and chipset sync is performed. It has been Verified using FSP debug logs on Brya board. Change-Id: I9a160fee72b61ae9eecababf9a16900e6bd4acff Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-15soc/apollolake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-15soc/intel/cnl: Enable CSE FW sync for CSE LITE SKUMatt DeVillier
Boards based on google/puff baseboard (hatch variant) use CSE LITE, which utilizes RO and RW firmware. If the CSE does not switch to the RW firmware, the HECI1 interface is disabled, and dependent drivers (like SOF audio firmware) fail to load. Use the same logic as other platforms utilizing CSE LITE (eg, TGL/JSL) to check if an ME RW firmware update is available, and if not jump to the onboard RW firmware. Test: built/boot Manjaro 21.x on google/wyvern, verify CSE RW firmware loaded via cbmem console, HECI1 interface is present vis lspci, and the SOF DSP firmware is correctly loaded via dmesg. Change-Id: I0ae21adde4a64bbcc5fa4fb144436a0430e92280 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15soc/amd/sabrina: Select ACP gen2Fred Reitberger
Select ACP gen2 for Sabrina Change-Id: I107ebd390732b597629a3236d0e7d1f5e2c51379 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/amd/common/acp: add acp_gen2Fred Reitberger
The gen2 ACP register definitions and locations are different from previous models. Specific code is refactored into acp_gen1 and acp_gen2. Update ACP register locations and definitions for gen2. Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15herobrine: update SPI-NOR config optionsT Michael Turney
Configuration support for 4k-byte addressing mode BUG=b:215605946 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Signed-off-by: T Michael Turney <quic_mturney@quicinc.com> Change-Id: If82de6204446251dded1b83684677e6eb536e6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-15drivers: spi_flash: Addressing mode change for SPI NORT Michael Turney
As 4-byte addressing mode is not support in coreboot, change the addressing mode of SPI NOR from 4-bytes to 3-bytes. BUG=b:215605946 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com> Signed-off-by: Shaik Sajida Bhanu <quic_c_sbhanu@quicinc.com> Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2022-02-14mb/google/brya/var/vell: update gpio for DMICShon Wang
Data on channel 0 & 1 are normal (from DMIC) but there is noise on channel 2 & 3, so change to NF PAD_CFG_NF(GPP_R6, NONE, DEEP, NF4) to PAD_NC(GPP_R6, NONE), PAD_CFG_NF(GPP_R7, NONE, DEEP, NF4) to PAD_NC(GPP_R7, NONE), BUG=b:210802722 TEST=FW_NAME=vell emerge-brya coreboot Change-Id: I1b5ccd2c239e526e4f1ce2d5ed6c1386303590c8 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61033 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-14mb/google/guybrush: Enable power resource for BTRaul E Rangel
The `reset` gpio is currently being consumed by the btusb kernel driver. The functionality was added in https://crrev.com/c/3342774. The goal of the patch was to reset the BT device when command timeouts occur. This works, but it doesn't support the case where the BT device is having problems with USB enumeration. In that case the device can't enumerate so the driver can't help resetting the device. If we instead switch to using an ACPI power resource, the kernel can control the BT device's power. This is beneficial when the device is having USB communication problems since the kernel will try and power cycle the device. We don't lose the ability to reset the device on command timeouts either since `btusb_qca_cmd_timeout` will enqueue a USB port reset if there is no `reset` GPIO. So win / win. This results in the following power resource: PowerResource (PR02, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x84) Sleep (0x01F4) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.STXS (0x84) Sleep (0x0A) } } I switched the device tree entry from using reset_gpio to enable_gpio because the acpi_device_add_power_res method asserts the reset in the _ON method unconditionally. This results in a small glitch on the line. By using the enable_gpio we get the correct behavior. I don't have a datasheet right now, so I just picked some values for the reset timing. The kernel driver was using 200ms. We can revisit the numbers when we get a datasheet. BUG=b:218295688 TEST=Suspend stress test on nipperkin with 600+ cycles. Verify power resource is created on the kernel. This should allow the kernel to power cycle the device via usb_acpi_set_power_state. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib1eff86db76929f76432cd6f765880c892e7a786 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-14mb/google/brya: Adjust FMD file for some boardsTracy Wu
When brya boards that use ChromeOS autoupdate update their firmware, devices with SOC_INTEL_CSE_SUB_PART_UPDATE will end up attempting to replace IOM and NPHY BPDT firmware in the CSE region. However, because of the way the autoupdate works, the CSE RO will not be updated during autoupdate. This means that these boards now have different stitching schemes between CSE RO and RW and this causes the sub-partition update to fail and the boot hangs. To remedy the situation for these boards, a separate FMD files is provided so they can continue to use the cse_serger tool for stitching. The only boards affected were kano and brask, so they are updated here. BUG=b:218376385 TEST=use flashrom to downgrade to 14474 then use futility to update to image with this patch and system boots. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: Ia8bdf6b28d952f6d983b84e39da96e159027a822 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-14drivers/smmstore/store.c: Add fmap_config.h dependencyArthur Heymans
This fixes building with -jx Change-Id: I51efc03839c53b96fa248e6fe5dc0e00b773aa53 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-02-14soc/intel/graphics: Repurpose graphics_get_memory_base()Ethan Tsao
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory base if required, because it may vary by platfrom. BUG=b:216756721 TEST= Check default offset for existing platform and update platform specific offset in Kconfig under SoC directory. Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e Signed-off-by: Ethan Tsao <ethan.tsao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61389 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-14mb/google/brya/var/brask: Enable ASPM of RTL8125Alan Huang
Brask cannot pass powerd_dbus_suspend test because the NIC does not enter ASPM L1.2. Here we add "enable_aspm_l1_2" in devicetree for RTL8125 to enable ASPM L1.2. BUG=b:204309459 BRANCH=None TEST=emerge and test with command powerd_dbus_suspend Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I9a56df1d68696f409f9ee681d37de6759a588d80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-14drivers/net/r8168: Add ASPM control mechanismAlan Huang
Add a new configuration parameter "enable_aspm_l1_2". Write value 0xe059000f to register offset 0xb0 to allow kernel driver to enable ASPM L1.2. Use Kconfig "PCIEXP_ASPM" and "enable_aspm_l1_2" to decide whether to enable ASPM L1.2. BUG=b:204309459 TEST=emerge and test if the driver can read the correct value Change-Id: I944dbf04d3ca19df4de224540bee538bff4d1f12 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-13mb/amd/chausie: update GPIO for chausieFred Reitberger
Add/update initial GPIO pin descriptions and initialization types for chausie mainboard. Change-Id: I14ea0e1086f626398a867896ee81ce07cf530182 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-13soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUSFelix Held
Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC talk to each other via the system bus, there is no longer the requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2 as the IOAPIC ID while most of their CPUs have more than 2 logical cores resulting in the IOAPIC having the same ID as one of the LAPICs. All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT and IVRS ACPI tables and there's no MPTable support for those SoCs that might also rely on those IDs being consistent. This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4 bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of IOAPIC IDs, this is non-standard. TEST=AMD Mandolin and Google Liara still work. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-02-12arch/x86/id.S: Fix building with clangArthur Heymans
The following error message is now gone: CC bootblock/arch/x86/id.o /tmp/id-35b17a.s:35:7: error: expected relocatable expression .long - ver ^ /tmp/id-35b17a.s:36:7: error: expected relocatable expression .long - vendor ^ /tmp/id-35b17a.s:37:7: error: expected relocatable expression .long - part ^ Tested with BUILD_TIMELESS=1 on x86_32 with gcc. The binary stays the same. Change-Id: I930e7b96c4428bcb95ff1903e6a3e7679171ffee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-02-12soc/intel/apl: Use Kconfig to enable CseRbpSean Rhodes
This patch makes SKIP_CSE_RBP=y default for Apollo Lake if Boot Device is memory mapped and ensures SkipCseRbp UPD is guarded against this config. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-12mb/google/dedede/var/beadrix: Add LTE modem supportTeddy Shih
This change adds LTE modem for beadrix. BUG=b:204882915 BRANCH=dedede TEST=Build and boot beadrix, check with command modem status Change-Id: I7acb88634478ff486810b2c3fc14d6739c3268e1 Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61328 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12soc/amd/cezanne/psp_verstage/uart: Fix off by 1 errorRaul E Rangel
FCH_UART_ID_MAX == 2, and there are 2 UARTS, so we don't need the -1. BUG=b:215599230 TEST=Build guybrush Found-by: Coverity CID 1469611 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f0171ed2d3da7f86ba3cfd0457f60d2d5722625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61869 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12arch/x86/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer
Replace `LEqual(a, b)` with `a == b`. Change-Id: Iabfaaee22011a75cc981607d366d61660838ab21 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-12mb/google/brya/var/agah: Update Aux settingsTony Huang
Agah port 0 does not have a retimer so the port needs to be configured for the SOC to handle Aux orientation flipping. Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-12mb/google/nissa: Set half_populated trueKrishna Prasad Bhat
Alder Lake N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-12sb/intel/ibexpeak/azalia.c: Use 'pci_{and,or}_config'Elyes HAOUAS
Change-Id: Iafe1a3476c0afa5ebfb75fb704429594e24e96f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-02-12mb/siemens/mc_apl{2,4,5,6}: Enable recovery MRC cacheWerner Zeh
The mainboards mc_apl{2,4,5,6} use VBOOT for verification and can be in a recovery state for different reasons. In this case we still want the MRC cache to be around to avoid the DRAM retraining on every boot. This patch enables the Kconfig switch HAS_RECOVERY_MRC_CACHE which makes the already available MRC recovery region in FMAP useable. Test=Boot mc_apl2 in recovery mode and make sure the recovery MRC cache is used. Change-Id: I2ea4993f05dd87a0e637f55e84b4fc06f5e29ecc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2022-02-12soc/amd/cezanne: Allow to specify SPL table path in KconfigZheng Bao
BUG=b:216096562 Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12mb/amd/majolica/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. The IRQ routing on Chausie that was a 1:1 copy caused some issues with the I2C driver, so port the Chausie IRQ mapping change back to Majolica. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb958639dd8aef7c60c050ad107dde7d1cd6a8bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/61867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12mb/amd/chausie/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. This should fix these errors: [ 0.655051] i2c_designware AMDI0010:00: IRQ index 0 not found [ 0.659239] i2c_designware AMDI0010:01: IRQ index 0 not found [ 0.663198] i2c_designware AMDI0010:02: IRQ index 0 not found [ 0.667200] i2c_designware AMDI0010:03: IRQ index 0 not found Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c85c8e4b1c860d6ca25060353355f703a49e1e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-12mb/google/guybrush/var/nipperkin: Add _HID for privacy screen deviceKevin Chiu
BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot dump SSDT, see _HID instead of _ADR Change-Id: I3f45fabac1548cca39379f91cc42fed0cd04f8a3 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12soc/amd/common: Scan bridge devices behind SoCs GPU ControllerKevin Chiu
Scan devices behind SoCs GPU controller to expose more buses. BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot Change-Id: Ib78e6570f101c71efaf9cc1843defcb05301cd30 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12soc/mediatek: Fix printing SPM versionYu-Ping Wu
Currently the SPM version string is stored at the end of the blob, possibly without a trailing '\0'. Therefore, we should be careful not to print characters beyond the blob size. BUG=b:211944565 TEST=emerge-corsola coreboot TEST=SPM version looked good in AP console BRANCH=asurada,cherry Change-Id: Icfeb686539dc20cf5b78de77c27bdbb137b5d624 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-02-11mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMERCasper Chang
Config USE_PM_ACPI_TIMER to y for primus4es only as commit 1ce0f3aab7 (mb/google/brya: Fix S0i3 regression) breaks suspend stress test on ES CPU SKU. BUG=b:211377699 TEST=USE="project_primus emerge-brya coreboot" and verified the suspend stress test works on primus4es. Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-02-11soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-NUsha P
Few of the Alder Lake-N Device IDs according to EDS, are named as ADL_M IDs in the current code. Hence rename those device IDs as ADL_M_N and use them for Alder Lake-N platform. Document Number: 619501, 645548 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I6042017c6189cbc3ca9dce0e50acfb68ea4003f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11soc/amd/common/acp: introduce acp_gen1Fred Reitberger
Refactor existing acp code into acp_gen1 variant as preparation for gen2 variant in sabrina. Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/common/fsp: check fsp image revisionJulian Schroeder
Check if FSP binary and coreboot FSP structures (fspmupd.h) match sufficiently. A change in minor number denotes less critical changes or additions to the FSP API that still allow for the boot process to proceed. A change of the AMD image revision major number will halt boot. The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD Picasso, Cezanne and Sabrina APUs. BUG=b:184650244 TEST=build, boot and check fsp image revision info. Example: FSP major = 1 FSP minor = 0 FSP revision = 5 FSP build = 0 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11src/arch/ppc64/*: pass FDT address to payloadSergii Dmytruk
It's available in %r3 in bootblock and needs to be passed to payload in %r27. We use one of two hypervisor's special registers as a buffer, which aren't used for anything by the code. Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-02-11arch/ppc64/boot.c: handle non-OPD entry pointSergii Dmytruk
Change-Id: I309be370d66a808b355241fcee880883631f38ce Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-11src/mainboard/emulation/qemu-power9: require hb-mode=onYaroslav Kurlaev
"hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which is OpenPower firmware created by IBM. QEMU for PPC64 can run initial program in two different modes: * hb-mode=off with load address 0x00000000 * hb-mode=on with load address 0x08000000 Real hardware always loads firmware at 0x08000000 and coreboot shouldn't require a special build to be run on QEMU. Memory layout is updated to reflect change of load address. Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11src/mainboard/emulation/qemu-power9: add RAM detectionYaroslav Kurlaev
Change-Id: Ie333294c7a311f6d47bdfbd1fc3cec0128cf63e7 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11ppc64/arch/mmio.h: ignore HRMOR and inhibit cacheYaroslav Kurlaev
Change-Id: I9895fc0dcc0ab72151f3b2bde409c8556525433d Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11src/mainboard/emulation/qemu-power9/*: add QEMU POWER9 mainboardYaroslav Kurlaev
Add initial implementation for booting on QEMU POWER9 emulation. Change-Id: I079c5b9ad564024dd13296ef75c263bdc40c9d39 Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-02-11mb/google/brya/variants/primus: add dram part idMalik_Hsu
This change adds mem_parts_uesd.txt that contains the new memory parts used (H54G46CYRBX267,H54G56CYRBX247) by primus and Makefile.inc generated by gen_part_id using mem_parts_used.txt. BUG=b:218415732 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0d236c51f0c996a22954046876f3494ba9e62693 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position ↵Robert Zieba
makefile variables Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded. This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well. BUG=b:198322933 TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-11soc/amd/common/block/lpc/espi_util: add decode range register helpersFelix Held
Introduce and use functions to translate eSPI IO/MMIO decode range IDs into the corresponding register bits and the IO/MMIO range and size register IDs into register offsets. This is a preparation to support the additional eSPI decode ranges on Sabrina where not all enable bits and base/size registers for one type of decode ranges are consecutive. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11soc/amd/common/block/include/espi: rename IO/MMIO base/size registersFelix Held
This aligns the register names more with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11mb/google/brya/var/nivviks: Implement WWAN power sequencingReka Norman
Nissa is using the FM101, which has the following power sequencing requirements: Power on: assert WWAN_EN, delay 20 ms, deassert WWAN_RST_L Power off: assert WWAN_RST_L, delay 20 ms, deassert WWAN_EN Add a power resource to the USB device, and use wwan_power.asl to handle the power off sequence. BUG=b:217092522 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/61694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11mb/google/brya: Support power sequencing for USB-only WWANReka Norman
Nissa is using the FM101 which is USB only. To allow us to reuse the existing wwan_power.asl for power sequencing, move the PCIe-specific part behind a new Kconfig HAVE_PCIE_WWAN. BUG=b:217092522 TEST=Build brya0 and check that generated dsdt.asl doesn't change. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Icb6db91ce00deb2b30379f5ff7a974d1feb62ea8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-11mb/google/brya/var/nivviks: Disable LTE-related GPIOs based on fw_configReka Norman
If the LTE USB DB is not connected, disable the LTE-related GPIOs. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I86251d8ad58d82ff2112ac5f2dfafdabbff4c76f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-02-11mb/google/brya/var/nivviks: Initialise overridetreeReka Norman
Add an initial overridetree for nivviks based on the pre-proto schematic and build matrix. BUG=b:197479026 TEST=abuild -a -x -c max -p none -t google/brya -b nivviks Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2022-02-11src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADERTim Wawrzynczak
There may be occasions where an I2C device was initialized during "early initialization," but when used again in ENV_PAYLOAD_LOADER before resource allocation happens, it would currently return that it has not been assigned a BAR. However, because of the early BAR assigned to it, it should still be valid to use that until proper resources have been assigned, therefore return any BAR that may have been assigned to the device during early initialization. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8ab599199592a72ae96cd9f95accfaa0d84e66b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-11drivers/i2c/tpm/cr50: Remove unused `chip` function argumentsTim Wawrzynczak
The `chip` argument passed around to many functions in this driver is actualy unused, so remove it where it is unused. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib8d32fdf340c8ef49fefd11da433e3b6ee561f29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-11lib/device_tree.c: Change 'printk(BIOS_DEBUG, "ERROR:' to printk(BIOS_ERR, "'Elyes HAOUAS
Change-Id: Ie20a2c35afc2b849396ddb023b99aab33836b8de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 04:46:30 +0000