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2019-10-03cpu/intel/: Fix regression with smmrelocateKyösti Mälkki
Fix regression with commit d53fd70 intel/smm/gen1: Use smm_subregion(). The bitmask on SMRR register parameter was inverted for selected models. Change-Id: Ia572ca3bdd4da371985691b5d249f998382fbe48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-03ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabledMartin Roth
Don't set a default bus type for the Chrome EC on x86. The platform must select the bus, typically LPC or ESPI. BUG=b:140055300 TEST=Build tested only Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-10-03mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPIMartin Roth
Previously all boards using eSPI for the Chrome EC just called it LPC as the code for the chrome EC is the same between the two busses. I'm adding a new Kconfig symbol to specify eSPI, so switch the boards that actually use eSPI to that symbol and add the LPC symbol to all the others. The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default to enabled for x86 platforms, so one symbol or the other needs to be specified for each platform. BUG=b:140055300 TEST=Build tested only. Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-03southbridge/intel: Add config option to validate firmware descriptorMathew King
Add new config option to validate the Intel firmware descriptor against the fmap layout. This will prevent a firmware descriptor from being used that could corrupt regions of the bootimage in certian circumstances. BUG=chromium:992215 TEST=Build firmware image with mismached decriptor and fmp Without VALIDATE_INTEL_DESCRIPTOR set firmware builds With VALIDATE_INTEL_DESCRIPTOR set error is shown with mismached regions Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03sb/intel/i82801gx: Use symbolic name for register, code reworkPetr Cvek
An original code had a wrong register address 0x27 for AHCI BAR. The value was aligned incidentally by the code specific of the pci_read_config32 function to the correct address 0x24. All 0x24 values in sata.c were changed to the symbolic name PCI_BASE_ADDRESS_5 and the code was optimized. An equivalent code was tested on a real hardware. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35737 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-03mb/facebook/fbg1701/devicetree.cb: Use 64MB framebuffer sizeFrans Hendriks
Connected 4K monitor is not configured at max resolution. The framebuffer size is too small. Increase the framebuffer size to 64MB. This is sufficient for max configuration of 1 HDMI monitor combined with internal LCD panel. BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701 Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-03soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMBFrans Hendriks
Add defines to have some more readable code for devcietree.cb. BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701 Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-03mb/facebook/fbg1701: Add mainboard_read_pcb_version()Frans Hendriks
PCB version is determined using inb() in actual code. Create function mainboard_read_pcb_version to read pcb version. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 Change-Id: I7c16627f468d84ca4ad2aab8bf9fb555f50dc23c Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-03intel/fsp_baytrail: Drop some PCI scratchpad register definitionsKyösti Mälkki
These were unused and somewhat cryptic, assumed purpose was to store pre-CBMEM timestamps in various PCI config space locations. Change-Id: I074294446501d49a9bd3c823a2a794c33f443168 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35731 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02intel/quark: Drop xx_DEV_FUNCKyösti Mälkki
Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02intel/skylake: Refactor IRQ assignmentsKyösti Mälkki
When creating the IRQ routing, referenced device and function number are always of the same PCI device. Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02intel/pci_devs: Regroup PCI xx_DEVID entriesKyösti Mälkki
Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02mb/google/drallion: Disable GBE in firmware for drallion variantsThejaswani Putta
BUG: None TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.corp-partner.google.com> Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02intel/baytrail: Replace config_of(dev) with config_of_soc()Kyösti Mälkki
The function does not otherwise need dev. Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35670 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02mb/google/drallion: Dynamicly disable memory channelEric Lai
Disable memory channel by HW strap pin. Using for factory debug. BUG=b:139773082 BRANCH=N/A TEST=Rework HW strap pin and check /proc/mem_info Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02mediatek/mt8183: Rename fields of struct sdram_paramsYu-Ping Wu
Two fields of struct sdram_params are renamed for future CL of DRAM full calibration. Field 'impedance' is also removed. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02sb/intel/common/smihandler: Hook up smmstoreArthur Heymans
TESTED on Asus P5QC. Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30012 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-02soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameterMichael Niewöhner
Make the the FSP Parameter PchHdaVcType a devicetree setting and make use of it in the devicetrees of all boards that currently set it. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2019-10-01mediatek/mt8183: Allow modifying vcore voltageHsin-Hsiung Wang
Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be calibrated with different vcore voltages to get correct parameters. A new API is added to allow changing vcore voltage. BUG=b:80501386 BRANCH=none TEST=measure vcore voltage with multimeter Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-01cpu/intel/common: Move intel_ht_sibling() to common folderPatrick Rudolph
Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-01mb/kontron/986lcd-m: Add gameport base allocation workaroundPetr Cvek
A missing definition of gameport base (PNP io 0x60) will cause an automatic address assignment during PCI/PNP enumeration, which won't obey limit 0x7ff. This will cause the enumeration to fail as other devices already have the values enabled. The symptoms are: not working USB, PS/2, garbled UART console, not working PCIe GPUs and crashes. Probably because of wrongly assigned IO ports. Example of log (shortened): Done reading resources. Setting resources... !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.0 1c * [0x0 - 0xfff] io !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.1 1c * [0x1000 - 0x1fff] io !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.2 1c * [0x2000 - 0x2fff] io !! Resource didn't fit !! aligned base 400 size 10 limit 2e7 40f needs to be <= 2e7 (limit) PCI: 00:1f.2 20 * [0x3080 - 0x308f] io !! Resource didn't fit !! ... ERROR: PCI: 00:02.0 14 io size: 0x0000000008 not assigned ... ERROR: PCI: 00:1f.2 10 io size: 0x0000000008 not assigned ERROR: PCI: 00:1f.2 14 io size: 0x0000000004 not assigned ERROR: PCI: 00:1f.2 18 io size: 0x0000000008 not assigned ERROR: PCI: 00:1f.2 1c io size: 0x0000000004 not assigned ERROR: PCI: 00:1f.2 20 io size: 0x0000000010 not assigned ... PCI: 00:1b.0 subsystem <- 8086/27d8 PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/27d0 PCI: 00:1c.0 cmd <- 107 PCI: 00:1c.1 brids70c01mcu0PeC: 0 dV0i8s0immicrocode: upd10a00000y0025 x666600CPU physiaB 0 0 e k MTRR cheaeu60zeAttemfWaiting for 1st Sot AP: slot 1 apic_L0ecl0zsax a aInitiNntt kac:oIG0 Ua dUrSGSGL Ct0C07fintel_vga_int15_h VGA Option ROM wa7..Azalia0Azalia: codkAbCiPCI: 00:1c.0 init finished We can see the ports probably started to collide after the activation of 00:1c.0 device. A debug run with compiled SPEW shows the problem with enumeration: PCI: 00:1f.1 18 * [0x50b8 - 0x50bf] io PCI: 00:1f.2 10 * [0x50c0 - 0x50c7] io PCI: 00:1f.2 18 * [0x50c8 - 0x50cf] io PCI: 00:1f.1 14 * [0x50d0 - 0x50d3] io PCI: 00:1f.1 1c * [0x50d4 - 0x50d7] io PCI: 00:1f.2 14 * [0x50d8 - 0x50db] io PCI: 00:1f.2 1c * [0x50dc - 0x50df] io PNP: 002e.7 60 * [0x50e0 - 0x50e0] io <-- gameport base DOMAIN: 0000 io: base: 50e1 size: 40e1 align: 12 gran: 0 limit: 7ff done Notice a weird base for DOMAIN, along with the limit. Adding a definition of gameport (0x220) as a workaround fixes the problems. The gameport should be still disabled thanks to disable bits (W83627THF datasheet is little bit chaotic). I didn't find any info if the gameport is available on some pads of the motherboard. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: Ie8e42552ac5e638e91e5c290655edcce1f64e408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-01intel/i945: Define peg_plugin for potential add-on PCIe cardKyösti Mälkki
Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-01intel/i945: Delay bridge VGA IO enable to ramstageKyösti Mälkki
Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-01intel/i945: Define p2peg for PCIe x16 slotKyösti Mälkki
Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-01intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROLKyösti Mälkki
This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30sb/intel/bd8x62x,i82801gx: Fix PCI bridge subsystem IDsKyösti Mälkki
Implementation of ich_pci_dev_enable_resources() used to have a custom implementation to program PCI subsystem IDs for the (legacy) PCI bus bridge. With the local implementation removed, we no longer need the custom .enable_resources callback. Change-Id: I6f73fd0e4d5a1829d1555455c9a143f1d18a6116 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Petr Cvek <petrcvekcz@gmail.com>
2019-09-30device/pci_early: Drop some __SIMPLE_DEVICE__ useKyösti Mälkki
The simple PCI config accessors are always available under names pci_s_[read|write]_configX. We have some use for PCI bridge configurations and resets in romstages, so expose them. Change-Id: Ia97a4e1f1b4c80b3dae800d80615bdc118414ed3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30sb/intel/spi: Use different SPIOPS for most SST flashesArthur Heymans
Many supported SST flashes use the AAI OP (0xad) to write. TESTED on Thinkpad X60 with SST25VF016B, flashrom can use AAI_WRITE op with locked down SPIOPS. Change-Id: Ica72eda04a8d9f4e563987871b1640565c6e7e12 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-30sb/intel/bd82x6x: Use common final SPI OPs setupArthur Heymans
This also reworks the interface to override OPs from the devicetree to match the interface in sb/intel/common/spi. Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-09-30mb/google/drallion: Clean up devicetree configAamir Bohra
* Disable SATA controller and related configs. * Disable PCIe root ports 10 and related configs. -> Board uses integrated CnVi for WLAN * Disable PCIe root ports 12 and related configs. -> Board uses WWAN intarfaced over USB Change-Id: If9d49cef290dcccb114afccc3ac34cd072802ea4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35723 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mb/google/drallion: Configure LPSS controller parametersAamir Bohra
drallion uses below LPSS controllers: I2C: 0/1/4 GSPI: None UART: 0(Console) BUG=b:141575294 Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2019-09-30arch/x86: Fix __ROMCC__ automatic prerequisitiesKyösti Mälkki
While the list of prerequisities is not created with romcc, we need to simulate it since different set of header files will is used. Change-Id: Ib799c872b5280e2035126f9660e04e51acc4b1a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35601 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30soc/intel/fsp_broadwell_de: Enable SSE and SSE2Kyösti Mälkki
Apparently romcc-bootblock just barely built without XMM registers. Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-30drivers/i2c/lm96000: Add more settings for fan controlNico Huber
Allow to set a lower temperature limit, as the currently hard-coded 25C may be to low for a given temperature sensor. Also enable smoo- thing, currently hard-coded to the maximum interval of 35s, and set the hysteresis value. Change-Id: I5fde1cf909e8fbbaf8a345790b00c58a73c19ef8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30drivers/i2c/lm96000: Fix integer sign issueNico Huber
We accidentally converted an `int` return value to an `unsigned`, making it impossible to check for errors with `< 0`. Fix that by using an `int` variable. Change-Id: I5433c27e334bc177913e138df83118b128c674b7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30ec/kontron/kempld: Add fall-through comments where appropriateNico Huber
Fixes related GCC warnings. Change-Id: I803fc0e005390ebd8a5e3ac6886ee968c56c3a34 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30drivers/i2c/at24rf08c: Add proper Kconfig optionNico Huber
The existing Kconfig code made SMBIOS_PROVIDED_BY_MOBO depend on VENDOR_LENOVO. Thus, it couldn't be selected by boards from other vendors. So we add another Kconfig that selects it here. NB. It's still unclear how the two drivers in this directory are related (at24rf08c and lenovo_serial). From the code, it doesn't look like the latter belongs here. Change-Id: Iaa5c5a584f2a5e2426352ec6aa681f99a55efa49 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30device/i2c_bus: Add i2c_dev_read_at16()Nico Huber
i2c_dev_read_at16() sends a 16-bit offset to the I2C chip (for larger EEPROM parts), then reads bytes up to a given length into a buffer. Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-09-30pci_ids: fix PCI ID for Intel Iris HALO GT4 iGPUMaxim Polyakov
According to the documentation [1], SKL-H Halo GT4E (Iris Pro Graphics P580) PCI ID should be 0x193B. [1] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM) Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference Manual. Volume 4: Configurations. May 2016, Revision 1.0 Doc Ref # IHD-OS-SKL-Vol 4-05.16 Change-Id: Id62fe3ec26779d51b748efd271db565ade1e3ee0 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-30pci_ids: rename PCI_DEVICE_ID_INTEL_SKL_ID_HMaxim Polyakov
The new macro name contains the number of cores: PCI_DEVICE_ID_INTEL_SKL_ID_H_4 - 4 core PCI_DEVICE_ID_INTEL_SKL_ID_H_2 - 2 core Change-Id: I190181b213d55865aa577ae5baff179fef95afde Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35302 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mediatek/mt8183: Init SPM driverDawei Chien
To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal. BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200 Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien <dawei.chien@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-09-30soc/intel/skylake: Fix ACPI exception AE_NOT_FOUNDPatrick Rudolph
Make sure to match devices on the root bus only. This fixes an issue where the SoC returned "MCHC" as ACPI name for devices behind bridge devices, as the DEVFN matched. Fixes observed "ACPI exception: AE_NOT_FOUND" in dmesg, as the ACPI path no longer contains invalid names. Tested on Supermicro X11SSH-TF. Change-Id: I6eca37a1792287502a46a90144f2f0d8e12ae5d4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30mb/supermicro/x11-lga1151-series: x11ssh-tf: remove unneeded ACPI ifdefMichael Niewöhner
This removes the "ifdef ACPI" which is not needed here as we currently don't include gpio.h in any asl file. Change-Id: I803bbee5933eda9423a9bc9fcaea9e905e3ac78e Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35543 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mb/supermicro/x11-lga1151-series: fix cmos layout and add default configMichael Niewöhner
This fixes the warning that power_on_after_fail could not be found, adds a default config and adds the parameter hyper_threading. Change-Id: I10b0aa71fa7916b01e93e16cbd81e427fd14f6a4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35526 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30mb: remove test-only HWIDsHung-Te Lin
The CONFIG_GBB_HWID can be generated automatically now so we can remove the test-only HWIDs set in board config files. BUG=b:140067412 TEST=Built few boards (kukui, cheza, octopus) and checked HWID: futility gbb -g coreboot.rom Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-30vboot: create board-specific test-only GBB HWID if not setHung-Te Lin
The HWID in vboot GBB is an identifier for machine model. On Chrome OS, that should be provisioned in manufacturing process (by collecting real hardware information), and will be checked in system startup. For bring up developers, they usually prefer to generate a test-only string for HWID. However that format was not well documented and cause problems. Further more, most Chromebooks are using HWID v3+ today while the test-only HWID is usually v2. Non-Chrome OS developers may also prefer their own format. To simplify development process, the GBB_CONFIG now defaults to empty string, and will be replaced by a board-specific test-only v2 HWID automatically. Developers can still override that in mainboard Kconfig if they prefer v3 or other arbitrary format. BUG=b:140067412 TEST=Built 'kukui' successfully. Removed kukui GBB config and built again, still seeing correct test HWID. Change-Id: I0cda17a374641589291ec8dfb1d66c553f7cbf35 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30device,drivers/: Drop some __SIMPLE_DEVICE__ useKyösti Mälkki
The simple PCI config accessors are always available under names pci_s_[read|write]_configX. Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-30getac/p470: Drop unused PCI secondary bus resetKyösti Mälkki
Change-Id: I959cdc08d43fea28f8bbc649cd46bab5656d6ca8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30console: Declare empty printk() for __ROMCC__Kyösti Mälkki
The typical do { } while (0) did not work, so provide empty stub function instead. Change-Id: Ieb0c33b082b4c4453d29d917f46561c0e672d09a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guardsKyösti Mälkki
Change in ssus_disable_internal_pull() is for romcc compatibility. Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-30mb/siemens/mc_bdx1: Enable VBOOTWerner Zeh
Enable VBOOT in Kconfig and provide a flashmap that includes all the needed sections for VBOOT support. Change-Id: Iee12a5d1781c869b20bc14a52ecbf23474caa3fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30fsp_broadwell_de: Enable early write access to the SPI flashWerner Zeh
If VBOOT is used on a mainboard based on fsp_broadwell_de then VBOOT needs to be able to write to its NV data which may be stored on the SPI flash. Enable write access to the SPI flash on SoC level. If the mainboard does not use VBOOT the linker will drop the extra code. The benefit is that this code is at least compiled and therefore build tested with fsp_broadwell_de. Change-Id: I90a2d30f5749c75df2b286dce6779f10dde62632 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-30mb/google/drallion: Adjust GPD3 pin terminationBora Guvendik
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cometlake pch EDS vol1 section 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on drallion platform, able to boot up into OS and stay at power up state. Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-09-30mb/google/drallion: De-assert WWAN reset signalAamir Bohra
BUG=b:141734594 Change-Id: I419f7d11dffebe6c44eefa05750834d07d19857b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-29amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICEKyösti Mälkki
Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29device/pnp_ops: Add ENV_PNP_SIMPLE_DEVICEKyösti Mälkki
Source files including this may have locally defined __SIMPLE_DEVICE__ so this cannot be placed in <rules.h>. Change-Id: I2336111b871203f1628c3c47027d4052c37899dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35653 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29device/pci_ops: Add ENV_PCI_SIMPLE_DEVICEKyösti Mälkki
Source files including this may have locally defined __SIMPLE_DEVICE__ so this cannot be placed in <rules.h>. Change-Id: If700dd10fd5e082568cd6866bfd802fc2e021806 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35652 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29intel/fsp_baytrail: Drop unnecessary lookup for PCI 0:0.0Kyösti Mälkki
It is safe to assume this to be copy-paste from eg. i945 where registers of said PCI device were read. Change-Id: I387b7fd6caf317543a6438f973d9e1d96e418de3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35668 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-29soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki
The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-28cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ useKyösti Mälkki
Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28usbdebug: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
We can always PCI config accessors with pci_devfn_t. Change-Id: I6d98c2441cc870cdcadbe8fabc9f35b9ffc652d8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28drivers/net/ne2k: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
Note that the code assumes mainboard code to configure any PCI bridges prior to calling console_init(). Change-Id: I0312d359f153c02e4afcf1c09d79f9eb3019a8b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28arch/arm,mips: Use generic PCI MMCONFKyösti Mälkki
We need the stub header file. If PCI was implemented, assume generic MMIO mapped configuration space would work here. Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb/via/vx900: Remove some __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: I840131f91e79c740c0c8784c252723ae90ded458 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28device/pci: Replace some __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: Ide9df46b5ff47fea54b9de0e365638a6223c8267 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ useKyösti Mälkki
Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-28nb/intel/x4x: Avoid x4x.h header with romcc-bootblockKyösti Mälkki
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-28mb/google/variants/drallion: Update the spd index mapAamir Bohra
BUG=b:141575294 Change-Id: I1b2b4362b84b170bd73b760828ca300ec86c4534 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-09-28mb/google/drallion: Set UART for console to UART controller 0Aamir Bohra
Drallion uses UART 0 for console, change the config accordindly. BUG=b:139095062 Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-28Kconfig: Hide CONFIG_CBFS_SIZE when an FMDFILE is providedArthur Heymans
CONFIG_CBFS_SIZE should only be used as a parameter to generate the default FMAP. This also swaps around FMDFILE and CBFS_SIZE to avoid that the CBFS_SIZE entry disappears when filling in the FMDFILE entry below it. One advantage is that if code references CONFIG_CBFS_SIZE the jenkins buildtest will most likely fail as many boards provide an FMD file. Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-28mb/lenovo/x131e: enable mSATA slotJames Ye
Per google/stout. Tested with SanDisk SSD U110. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-09-27mb/lenovo/x131e: correct USB port configJames Ye
Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-27fmap: Add get_fmap_flash_offset()Furquan Shaikh
CB:35377 changed the behavior of find_fmap_directory() to return pointer to CBMEM_ID_FMAP if fmap is cached in cbmem. lb_boot_media_params() calls find_fmap_directory to add offset of fmap in flash to coreboot table. However, because of the change in behavior of find_fmap_directory(), it ended up adding 0 as the offset. This change adds a new function get_fmap_flash_offset() which returns the offset of fmap in flash. Ideally, all payloads should move to using the FMAP from CBMEM. However, in order to maintain compatibility with payloads which are not updated, ensure that fmap_offset is updated correctly. Since find_fmap_directory() is no longer used outside fmap.c, this change also removes it from fmap.h and limits scope to fmap.c. In a follow up patch, we need to push a change to libpayload to expose the fmap cache pointer to lib_sysinfo. BUG=b:141723751 Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-09-27device: add commentary to dev_find_slot()Aaron Durbin
dev_find_slot() can sometimes fail to return the desired device object prior to full PCI enumeration. Comment the declaration and implementation accordingly to help the user understand the problem and avoid its usage. Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35632 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-27mb/supermicro/x11-lga1151-series: remove unneeded vendor id configMichael Niewöhner
The vendor id option set here is useless as most SSVID registers get filled with 0x8086 (their VID) by default, anyway. Besides that the Kconfig option isn't meant for retrofit ports, cf. commit 7e1c83e31bd (Add Kconfig options to override Subsystem Vendor and Device ID). The right place would be the devicetree. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: If67c679bb342f63096902535734106e4f1651118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-27lib/bootsplash: Fix compilationPatrick Rudolph
Add missing include. Tested on Supermicro X11SSH-TF. Change-Id: Id0c80ac646001a497e96cae4d48a0f09762eb936 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35613 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26arch/: Replace __BOOTBLOCK__ with ENV_BOOTBLOCKKyösti Mälkki
Change-Id: I294a3fd7be57b505cd209f7c2718a05770786c51 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-26soc/amd/common/block/spi/fch_spi_ctrl.c: Fix SPI vendor id codeRichard Spiegel
All solid state devices have vendor id defined by JEDEC specification JEP106, which originally allocated only 7 bits for it plus parity. When number of vendors exploded beyond 126, a banking proposition came maintaining compatibility with older vendors while allowing for 4 extra bits (16 banks) through the introduction of the concept "Continuation code", denoted by the byte value of 0x7f. Examples: 0xfe, 0x60, 0x18, 0x00, 0x00 => vendor 0xfe of bank o 0x7f, 0x7f, 0xfe, 0x60, 0x18 => vendor 0xfe of bank 2 BUG=b:141535133 TEST=Build and boot grunt. Change-Id: I16c5df70b8ba65017d1a45c79e90a76d1f78550c Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-26soc/intel/fsp_broadwell_de: move get_busno1() into vtd.cAndrey Petrov
TEST=just build it Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-26mb/supermicro: restructure x11ssh-tf to represent a x11 board seriesMichael Niewöhner
Most of the X11 boards with socket LGA1151 are basically the same boards with just some minor differences like different NICs (1 GbE, 10 GbE), number of NICs / PCIe ports etc. There are about 20 boards that can be added, if there is a community for testing. To be able to add more x11 boards easily like x11ssm (see CB:35427) this restructures the x11ssh tree to represent a "X11 LGA1151 series". There were multiple suggestions for the structure like grouping by series (x10, x11, x...), grouping by chipset or by cpu family. It turned out that there are some "X11 series" boards that are completely different. Grouping by chipset or cpu family suffers from the same problem. This is why finally we agreed on grouping by series and socket ("X11 LGA1151 series"). The structure uses the common baseboard scheme, while there is no "real" baseboard we know of. By checking images, comparing logs etc. we came to the conclusion that Supermicro does have some base layout which is only modified a bit for the different boards. X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we expect the other boards to have mostly the same device tree, there is a common devicetree that gets overridden by each variant's overridetree. Besides that some very minor modifications happened (formatting, fixing comments, ...) but not much. Documentation is reworked in CB:35547 Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26mb/mainboard/hatch: support elan touchpad for AkemiPeichao Wang
Modify IRQ pin from D21 to A21 and support wake-up from touchpad BUG=b:141519690 TEST=build bios and verify elan touchpad works fine Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26google/grunt: add new two DDR source for TreeyaPeichao Wang
new DDR particle: 1. Samung K4A8G165WC-BCWE 2. Hynix H5AN8G6NCJR-XNC BUG=b:139085024 BRANCH=master TEST=rework new source to DUT and re-flash bios to DUT and verify DUT will bring up successfully Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-26cpu/intel/: Clean up microcode update from __PRE_RAM__Kyösti Mälkki
Change-Id: Ib12985dd9a12495533a82be556405f975a0abe27 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-26cpu/amd/pi/00730F01: Clean up microcode update from __PRE_RAM__Kyösti Mälkki
It is only called in ramstage. Even if it was called in romstage, execution flow is such that BSP and AP CPUs should not be able to enter update_microcode() routine concurrently. Also the Kconfig guarding the spin_lock() calls are not selected nor are the lock variables declared for these platforms. Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35586 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-25soc/fsp_broadwell_de: fix flashconsole support for platformMatt DeVillier
CB:29633 switched platform to use sb/common spi implementation, which worked until CAR_GLOBAL was removed in CB:30506. Revert the changes back to usage of CAR_GLOBAL in the common spi driver so that flashconsole will work again in romsatge for fsp_broadwell_de. Test: verify flashconsole functional on out-of-tree Broadwell-DE board Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-25mb/google/kukui: Add new build target 'Juniper'Hung-Te Lin
Add the configuration 'Juniper' for the new mainboard. BUG=b:137517228 TEST=make menuconfig; select 'juniper' and build Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-09-25mb/google/hatch: Move SOC_INTEL_COMETLAKE selection to KconfigFurquan Shaikh
All variants of hatch are using Comet Lake and so the selection can be done in Kconfig without requiring each variant to do the same. Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-25mb/siemens/mc_apl1: Sort the names of all variant mainboardsWerner Zeh
Sort the names of all variant mainboards in an ascending order. Change-Id: I19d502298744c0e0cbc91eb836c62ca90cdb9a5c Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-25mb/siemens/mc_apl{2,4,5}: Enable VBOOTWerner Zeh
Enable VBOOT in Kconfig and provide a flashmap that includes all the needed sections for VBOOT support. Change-Id: I3d58094256d2730dbd249291a8f1ed8df9dfe62d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-25soc/intel/(apl,skl,cnl,common): Move mkhi_hdr structure definition to commonSridhar Siricilla
Removed mkhi_hdr structure definition from multiple SOCs, and moved to common. TEST=Built code for Hatch, apollolake boards. Change-Id: Ifeba0ed4d98975049179d1b47fb22c06a927dc29 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35545 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24intel/cpu: Switch older models to TSC_MONOTONIC_TIMERKyösti Mälkki
The implementation of udelay() with LAPIC timers existed first, as we did not have calculations implemented for TSC frequency. Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24cpu/intel: Use CPU_INTEL_COMMON_TIMEBASEKyösti Mälkki
Change-Id: I0e7159039751a88d86b6c343be5f085e6e15570a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24intel/socket_mPGA604: Enable TSC_CONSTANT_RATEKyösti Mälkki
We can use intel/common implementation for tsc_freq_mhz(). Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24cpu/intel/common: Fix invalid MSR accessKyösti Mälkki
Fix regression from commit ecea916 cpu/intel/common: Extend FSB detection to cover TSC MSR_EBC_FREQUENCY_ID (0x2c) was not defined for affected CPU models and rdmsr() caused reset loops. Implementations deviate from public documentation. Change to IA32_PERF_STATUS (0x198) already used in i945/udelay.c to detect FSB to TSC multiplier. Change-Id: I7a91da221920a7e7bfccb98d76115b5c89e3b52e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-24Add Razer Blade Stealth (2016) H2UJohanna Schander
The Razer Blade Stealth H2U is a KabyLake System using: - Intel KBL 7500U - ITE8528E SuperIO - Intel 600P Series NVMe SSD - Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB) of soldered memory in dualchannel mode - (Optional) Touchscreen - HDMI 2.0a via DP-1: Paradetech PS175 - AlpineRidge Thunderbolt 3 controller - TPS65982 USB-PD power switch / multiplexer Even though it has a 16MB chip equipped (W25Q128.V) only the first 8MB are used and mapped via IFD. The rest is left empty (0xFF). The flash is not secured in any way and can be read via flashrom. It should be the source for this port's IFD and ME blobs. Working: - USB-A Ports left and right - Speakers - Touchscreen (USB) - Onboard Keyboard in Linux - NVMe SSD - SeaBIOS, Tianocore and Grub Payloads - Webcam - Powersaving Modes - Battery state and LID switch, sometimes slow to update. - Touchpad (I2C-HID) - Headphones Not part of this commit: - Thunderbolt / USB-C (Requires advanced EC signaling) - Full HDMI support (Currently requires plugged connection at boot) Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2019-09-24device/mmio.h: Add bit field helpersHung-Te Lin
When accessing register with multiple bit fields, the common approach is to use clrsetbits_le32, for example: clrsetbits(&reg, (1 << 0) | (0x3 << 1) | (0x7 << 10), (1 << 0) | (0x1 << 1) | (0x5 << 10)); This hard to maintain because we have to calculate the mask values manually, make sure the duplicated shift (offset) was set correctly. And it may be even worse if the value to set will be based on some runtime values (that many developers will do a if-block with two very similar argument list), and leaving lots of magic numbers. We want to encourage developers always giving field names, and have a better way of setting fields. The proposed utility macros are: DEFINE_BITFIELD(name, high_bit, low_bit) EXTRACT_BITFIELD(value, name) WRITE32_BITFIELDS(addr, name, value, [name2, value2, ...]) READ32_BITFIELD(addr, name) Where a developer can easily convert from data sheet like BITS NAME 26:24 SEC_VIO Into a declaration DEFINE_BITFIELD(SEC_VIO, 26, 24) Then, a simple call can set the field as: WRITE32_BITFIELDS(&reg, SEC_VIO, 2); That is much easier to understand than clrsetbits_le32(&reg, 0x7 << 24, 0x2 << 24); And to extract the value: READ32_BITFIELD(&reg, SEC_VIO) That is equivalent to: (read32(&reg) & 0x3) >> 24 Change-Id: I8a1b17142f7a7dc6c441b0b1ee67d60d73ec8cc8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35463 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24mainboard/ocp/monolake: Hide internal NICAndrey Petrov
Disable root port IOU0 to which built-in NIC is attached. TEST=on OCP monolake, hide built-in NIC and make sure OS does not report built-in NIC Change-Id: I2384e7dd073355f0ced2902ac2d8418996b1c5aa Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-24soc/fsp_broadwell_de: Add devhide functionalityAndrey Petrov
Add function to hide IIO PCIe root ports. TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3] and make sure OS does not detect built-in NIC. Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-09-24emulation/qemu-i440fx: use fw_cfg_dma for fw_cfg_readHimanshu Sahdev
- configure DMA fw_cfg - add support to read using fw_cfg_dma - provide fw config version id info in logs BUG=N/A TEST=Build and boot using qemu-i440fx. Change-Id: I0be5355b124af40aba62c0840790d46ed0fe80a2 Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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