| Age | Commit message (Collapse) | Author |
|---|
|
Set the following register value to make SX9324 work normally
"ph0_pin" = "{1, 3, 3}"
"ph1_pin" = "{3, 2, 1}"
"ph2_pin" = "{3, 3, 1}"
"ph3_pin" = "{1, 3, 3}"
"ph01_resolution" = "512"
"ph23_resolution" = "1024"
"startup_sensor" = "1"
"ph01_proxraw_strength" = "2"
"ph23_proxraw_strength" = "2"
"avg_pos_strength" = "256"
"cs_idle_sleep" = ""gnd""
"int_comp_resistor" = ""lowest""
"input_precharge_resistor_ohms" = "4000"
"input_analog_gain" = "3"
BUG=b:295109511
BRANCH=None
TEST=emerge-nissa coreboot chromeos-bootimage & Check sar sensor data
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ib15f12d754fec8b379afd702b27d0701fac78072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
After commit e12b313844da ("drivers/pc80/rtc/option.c: Allow CMOS
defaults to extend to bank 1"), Thinkpad X200 with
CONFIG(STATIC_OPTION_TABLE) can no longer resume from s3 (detected via
bisect).
Further inspection shows that DRAM training result of GM45 is stored
in CMOS above 128 bytes in raminit_read_write_training.c, for s3 resume
to restore, but it will be erased by sanitize_cmos(), which now clears
both bank 0 and bank 1, leaving only "untrained" result restored, so s3
resume will fail.
However, resetting CMOS seems unnecessary during s3 resume. Now,
cmos_need_reset will be negated when acpi_is_wakeup_s3() returns true.
Tested: Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from
s3 again with these changes.
Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78288
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use human readable properties as upstream driver support.
BUG=b:297977526
TEST=Able to get sensor values changed w/wo a hand covering the device.
before this CL , SSD.dsl of STH9324
Package (0x02)
{
"semtech,ph0-pin",
Package (0x03)
{
Zero,
Zero,
Zero
},
...
Package (0x02)
{
"semtech,ph23-resolution",
Zero
},
Package (0x02)
{
"semtech,startup-sensor",
Zero
},
....
after this CL , SSD.dsl of STH9324
Package (0x02)
{
"semtech,ph0-pin",
Package (0x03)
{
One,
0x02,
0x02
},
...
Package (0x02)
{
" semtech,ph23-resolution",
0x0400
},
Package (0x02)
{
"semtech,startup-sensor",
One
},
Change-Id: Ie0d929228f4510f33b07d9c4cfdfcd2a9a437c27
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78174
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
|
|
Clevo had apparently swapped the Realtek card reader for the O2 Micro
card reader for newer batches of all TGL models. Enable the BayHub
driver on everything (except bonw15, which doesn't have a card reader)
to fix LTR programming, as was done for other in commit 3d7a5bdf58e0
("mb/system76: Enable DRIVERS_GENERIC_BAYHUB_LV2 to fix LTR issue").
Tested on system76/galp5: CPU reaches C-states deeper than C2 when idle.
Change-Id: I3667e08acd23c12638159a2f7d2592737a34e63d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Update Goodix touchpad HID to GDIX0000 for GXTP7288 and GXTP7863.
BUG=b:305118852
BRANCH=firmware-dedede-13606.B
TEST=Build and touchpads are workable
# evtest for GXTP7863
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: Lid Switch
/dev/input/event1: Power Button
/dev/input/event2: AT Translated Set 2 keyboard
/dev/input/event3: cros_ec_buttons
/dev/input/event4: Elan Touchscreen
/dev/input/event5: GDIX0000:00 27C6:0D51 Mouse
/dev/input/event6: GDIX0000:00 27C6:0D51 Touchpad
# evtest for GXTP7288
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: Lid Switch
/dev/input/event1: Power Button
/dev/input/event10: GDIX0000:00 27C6:01F5 Touchpad
/dev/input/event11: sof-da7219max98360a Headset Jack
/dev/input/event12: sof-da7219max98360a HDMI/DP,pcm=2
/dev/input/event13: sof-da7219max98360a HDMI/DP,pcm=3
/dev/input/event14: sof-da7219max98360a HDMI/DP,pcm=4
/dev/input/event2: AT Translated Set 2 keyboard
/dev/input/event3: cros_ec_buttons
/dev/input/event4: ELAN900C:00 04F3:2E5D
/dev/input/event5: ELAN900C:00 04F3:2E5D UNKNOWN
/dev/input/event6: ELAN900C:00 04F3:2E5D UNKNOWN
/dev/input/event7: ELAN900C:00 04F3:2E5D Stylus
/dev/input/event8: ELAN900C:00 04F3:2E5D Stylus
/dev/input/event9: GDIX0000:00 27C6:01F5 Mouse
Change-Id: Id2a6223bdbb2f0693149136baa853ca2efb57815
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
When CBFS verification is enabled, add amdfw_a/b.rom at offset 128 bytes
to account for CBFS file header with hash attribute. When CBFS
verification is disabled, add amdfw_a/b.rom at offset 64 bytes to
account for CBFS file header without hash attribute.
BUG=None
TEST=Build Skyrim, Myst BIOS images with and without CBFS verification
enabled.
Change-Id: Ic374ac41df0c8fb8ce59488881ce5846e9058915
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Fix the hash file names to be used to verify signed PSP binaries when
booting with VBOOT FW Slot B.
BUG=None
TEST=Build and boot to OS in Myst with PSP Verstage enabled using both
VBOOT slots A and B.
Change-Id: I89f02922bc901d8ac71d48bf5128fe6ecead43a0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Enable RO verification by GSC and RO/RW CBFS verification.
BUG=b:277087492
TEST=Build and boot to OS in Myst with CBFS verification enabled using
PSP verstage.
Change-Id: I2dd3ce59f331f89660185309ccf60c53d50e4fad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78235
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Some stalls are observed while using CCP DMA in PSP verstage -
especially with CBFS verification enabled. Also with RW CBFS
verification enabled, the entire firmware body is not loaded during
verstage for verification. Instead the files are verified as and when
they are loaded from CBFS. Hence the impact to boot time is reduced
since only few files are loaded during PSP verstage. Hence disable CCP
DMA in PSP verstage until the root cause is identified.
BUG=None
TEST=Build and boot to OS in Myst with CBFS verification enabled.
Change-Id: I22ac108b08abcfe432dfd175644393e384888e11
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78234
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add SPI flash RO ranges to be verified by GSC in order to enable CBFS
verification. Also with CBFS verification enabled, CBFS metadata is
more than 64 bytes. So configure the offset of amdfw_a/b to 128 bytes -
next address aligned to 64 bytes.
BUG=b:277087492
TEST=Build and boot to OS in Myst with and without CBFS verification
enabled.
Change-Id: Ibfffd3d6fce8b80ec156a7b13b387e1df8c43347
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78233
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Meteor Lake TME bits [42-45] are reserved regardless of if the part
supports TME or not.
On a device with TME fused off, we noticed some reboot hangs which
have been narrowed down to internal IP routing issues when the IA
accesses the Input Output Manager (IOM) which is mapped at
0x3fff0aa0000 (0x3ff upper 32 bits).
It turns out since TME is fused off, coreboot uses the full physical
address size reported by CPUID MAXPHYADDR (46 bits). Therefore, it
allocates thunderbolt memory range on 46 bits (0x3fff upper 32 bits).
Since 4 of these bits are actually reserved, it seems that this
address range is "stripped down" to 42 bits (=> 0x3ff upper 32 bits)
resulting in potential conflict with other devices such as IOM.
BUG=b:288978352
TEST=No reboot issue on rex with TME fused off
Change-Id: I96ba23ab304257003c0413243d3ac8129ce31743
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78452
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According the Intel Software Developer Manual,
CPUID.80000008H:EAX[15:8] reports the physical-address width supported
by the processor. Unfortunately, it does not necessarily reflect the
physical-address space the system can actulally use as some of those
bits can be reserved for internal hardware use.
It is critical for coreboot to know the actual physical address size.
Overestimating this size can lead to device resource overlaps due to
the hardware ignoring upper reserved bits. On rex for instance, it
creates some reboot hangs due to an overlap between thunderbolt and
Input Output Manager (IOM) address space.
As some SoCs, such as Meteor Lake, have physical address reserved bits
which cannot be probed at runtime, this commit introduces
`CPU_INTEL_COMMON_RESERVED_PHYS_ADDR_BITS' Kconfig to set the number
of physical address reserved bits at compilation time for those SoCs.
A runtime detection by hardware probing will be attempted if the value
is 0 (default).
BUG=b:288978352
Change-Id: I8748fa3e5bdfd339e973d562c5a201d5616f813e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78451
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This reverts commit 55b7dee2784e9fe80870c6c33ba91b98021df8b5.
Reason for revert: accidentally submitted out of order / breaks tree
Change-Id: Ic15d0e3688cd54f7d678998341263e7bd30e75f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78525
Tested-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
This reverts commit bb5fa6419dfd71950e61e75eecd48ef8203bb1b1.
Reason for revert: accidentally committed out of order; reverting to
unbreak tree
Change-Id: I36aa1fd3a0befe49b7e9e34198676f16fb08cf73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78524
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: Martin L Roth <gaumless@gmail.com>
|
|
Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Having a CBFS cache scratchpad offers a generic way to decompress CBFS
files through the cbfs_map() function without having to reserve a
per-file specific memory region.
This commit introduces the x86 `RAMSTAGE_CBFS_CACHE_SIZE' Kconfig to
set a ramstage CBFS cache size. A cache size of zero disables the
CBFS cache feature. The default size is 16 KB which seems a
reasonable minimal value large enough to satisfy basic needs such as
the decompression of a small configuration file. This setting can be
adjusted depending on the platform needs and capabilities.
To support S3 suspend/resume use-case, the CBFS cache memory cannot be
released to the operating system. There are two options to meet this
requirement:
1. Define a static CBFS cache buffer (located in the .bss section)
2. Create a new CBMEM entry
Option #2 seems more powerful but considering that:
1. The CBFS cache is actually not a cache but just a scratch pad
designed to be isolated between stages
2. postcar is a very short stage not really needing CBFS cache
3. The static initialization of the `cbfs_cache' global
variable (cf. src/lib/cbfs.c) offers a simple and robust design
=> It is simpler to use a static buffer and limit the support to
ramstage.
Since some AMD SoCs (cf. `SOC_AMD_COMMON_BLOCK_NONCAR' Kconfig) define
a `_cbfs_cache' region, an extra `POSTRAM_CBFS_CACHE_IN_BSS' Kconfig
must be set to enable the use of a static buffer as the CBFS cache
scratchpad.
TEST=Decompression of vbt.bin in ramstage on rex using cbfs_map()
Change-Id: I7fbb1b51cda9f84842992e365b16c5ced1010b89
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77885
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Having a CBFS cache scratchpad offers a generic way to decompress CBFS
files through the cbfs_map() function without having to reserve a
per-file specific memory region.
This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set
the pre-memory stages CBFS cache size. A cache size of zero disables
the CBFS cache feature. The default value is 16 KB which seems a
reasonable minimal value enough to satisfy basic needs such as the
decompression of a small configuration file. This setting can be
adjusted depending on the platform needs and capabilities.
We have set this size to zero for all the platforms without enough
space in Cache-As-RAM to accommodate the default size.
TEST=Decompression of vbt.bin in romstage on rex using cbfs_map()
Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This fixes assembling with clang which complains about fpu instructions.
TEST: BUILD_TIMELESS=1 remains the same.
Change-Id: I175b8e749fafde5fb7ffb8101fc0dc892d9b4e0d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74539
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable sending EOP from payload
BUG=b:279184514
TEST=Verify sending EOP from depthcharge on google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5eda0a5c6d4c34cfcc2de898adde0b005d6edc1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74768
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable EC keyboard backlight for dochi.
BUG=b:299284564
TEST=FW_NAME=dochi emerge-brya coreboot chromeos-bootimage
Change-Id: I1b640c576fcdd368110b88cba6f969f10dfc15f1
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Change-Id: I8d64236fc81e848503535db6f52e93328a60404c
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I2419feed1a76ec1cb04cb9640689b8758fa1d3f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Change-Id: Ief56bff2a1b8825d6e65aeb5f7ed9e8f432e465b
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I068fcbbcb0641cddce8fa85e2a64ab44d91d6bcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76526
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As per PPR, Genoa supports up to 96 core, that is 192 threads.
It also supports dual socket.
Change-Id: I817fea7c41477f476794e9e5c16451037d01f912
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
GPP_H04/GPP_H05 doesn't use for I2C usage, remove I2C2 "on" settings.
BUG=b:294155897
TEST=Check ap firmware log, i2c2 is disabled
Change-Id: I0124fd108fbbd87507d252e9caab4dfc16aceddb
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78339
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update SaGv gears and frequency values as per recommendation
from power and performance team. This change doesn't cause
negative impact on firmware boot time performance.
BUG=b:274137879
TEST=Verified the settings on google/rex using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ie8a81c05f25b1cdab1008d09c606d1debea6e6e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Crypto Engine in PSP prefers the buffer from Static RAM (SRAM). Hence if
a buffer comes from within SRAM address range, then it is passed
directly to Crypto Engine. Otherwise a bounce bufer from the stack is
used. But on SoCs like Picasso where PSP Verstage stack is mapped to a
virtual address space this check fails causing a bounce buffer to be
used and hence a stack overflow. Fix this issue by assuming that the
buffer comes from the SRAM always in such SoCs and pass the buffer
directly to crypto engine.
BUG=b:259649666
TEST=Build and boot to OS in Dalboz with unsigned PSP verstage.
Change-Id: I2161c8f0720c770efa5c05aece9584c3cbe7712a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
The Bayhub BH720 eMMC bridge is a fixed internal device, and needs to
me marked as non-removable in order for Windows to properly recognize/
utilize the device. Add the necessary ACPI to be generated at runtime.
TEST=build/boot/install Win11 on google/kahlee (liara)
Change-Id: I0815abf1d2dc5cfe785dc04670ab91f2a6a1af23
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Windows does not use these devices for audio. Hide these so they don't
clutter device manager.
Change-Id: Ic85eff7f7ff68e25cc005bbb822bf99374c96532
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78418
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On all targets the domain works as a host bridge. Xeon-sp code intends
to feature multiple host bridges below a domain, hence rename the
function to pci_host_bridge_scan_bus.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I4e65fdbaf0b42c5f4f62297a60d818d299d76f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78326
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
AMD Audio CoProcessor handles I2S audio on AMD SoC's. Prior to AMD
Ryzen platforms (e.g. STONEY) it is located on the Integrated GFX
device. As the proprietary AMD driver does not support accessing this
easily, reserve a custom ACPI ID from the coreboot namespace so that
another driver can be attached in Windows device manager.
Change-Id: I855b81908ed9ad0587b6367b052c726c36350208
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Use 2 gpio for stylus detect and wake function.
GPP_E04 is the IRQ source, and GPP_E09 is the wake source.
BUG=b:304680060
TEST=Build and test on karis, stylus detect function works
Change-Id: I7a83326f76932c8e501e6369bb845fc7236291b4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78336
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use runtime detection for touchscreens.
BUG=b:289962599
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ia43ada8b3b6dbee95dbadacc353106e0f8f37549
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This Kconfig option is used as a failback when `get_uint_option`
fails. It will fail after coreboot is flashed, as the cfr code has
not yet setup the options.
Change the default to OFF, so when it does fallback, it's the correct
behaviour.
Change-Id: I5d06047fe23322520e9c84ded8f1941f6d716a51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: Id42d07aabfd08c6c7a38515f9cf4b749750deecd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78202
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is required for the HDA device to work.
Change-Id: I5fd3617c4cb1e69b7e0ecf6cddf4c143da99b927
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78201
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This adds support for the Librem 11 tablet, using the ME 13.50.15.1436
binary from the original BIOS (version 28.D8.E1.021) and FSP binaries
from a Jasper Lake Chromebook.
The following features were tested with PureOS:
* Audio (speakers, microphone, headset jack)
* Cameras
* Display
* Touchscreen and pen
* Keyboard cover, with tablet/laptop mode switch indicated via ACPI
* Power and volume buttons
* USB-C ports (USB 2/3, DP alt mode, PD charging)
* SD card reader
* WLAN
* Bluetooth
* NVMe SSD (socketed)
* Battery state information from EC
* Accelerometer
A UART is accessible with soldering via test points on the mainboard,
documented in the mainboard Kconfig with a toggle to enable it for
coreboot logging.
Change-Id: I545994889ddfb41f56de09b3a42840bccbd7c4aa
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Based on schematics and confirm with EE to remove TOF function.
BUG=b:290891557
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I1ae6a6562d87f8da5f41691a7606a1aa10989443
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78147
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The next board revision of Librem 14 (v1-02) has replaced the ALC256
codec with ALC269. Add verbs for it.
Two GPIOs were changed from SMBus native functions to NC for this
revision. They are not used on either revision, change to NC.
Change-Id: I43b6265d2f502c05d5539ff3abf53ade0da6d706
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78347
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
New Librem 14s have a newer CPU stepping, which changes them from CML
v1 to v2. The product is not significantly different and remains v1,
specifically "v1-02".
Select SOC_INTEL_COMETLAKE_1_2 to support all CPU steppings.
Change-Id: Iab37208b81e973714a2c088d2346eda518bf1214
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Define SOC_INTEL_COMETLAKE_1_2, which creates a build supporting both
Comet Lake v1 and v2 by including both sets of FSP binaries and
selecting one based on the CPUID.
A mainboard can select this instead of SOC_INTEL_COMETLAKE_1 or ..._2
to support all CML-U steppings in one build.
Change-Id: Ic8bf444560fd6b57064c47faf038643fabde010e
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78345
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
|
|
Support embedding a second FSP-M/FSP-S binary for an SoC that can
select one at runtime.
Comet Lake v1 and v2 are different steppings of the same SKUs, but they
require different FSP binaries. Supporting both in a single build
requires embedding both FSPs and selecting one at runtime based on the
CPUID. This is desirable for a product that may have different CPU
steppings but is not otherwise differentiated enough for a separate
firmware build.
An SoC can select PLATFORM_USES_SECOND_FSP to indicate that two FSP-M/
FSP-S binaries are required. Implement soc_select_fsp_m_cbfs() and
soc_select_fsp_s_cbfs() to choose one based on platform-specific
criteria. For Comet Lake, the first FSP is CML v1 and the second is
CML v2, but in principle a platform could define any meaning for the
first and second FSP.
FSP-T is not affected, only one FSP-T can be embedded if FSP_CAR is
used.
Only one set of FSP headers is used, which is sufficient for Comet Lake
v1/v2; their headers are equivalent.
ADD_FSP_BINARIES, FSP_USE_REPO, and FSP_FULL_FD are supported for both
sets of FSP-S/FSP-M but cannot be configured separately, both use the
same configuration.
Change-Id: Ied4c6c49a6bdf278238272edd47a2006258be8e5
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78344
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Within TBT PCIe, following register offsets have been updated for
production silicon. Update ASL with new offsets.
1. MPC - Miscellaneous Port Configuration Register
2. RPPGEN - Root Port Power Gating Enable
3. SMSCS - SMI/SCI Status Register
BUG=306026121
TEST= Check TBT PCIe Tunnel creation and device enumration.
Change-Id: I0497f7108ef5046c2694aece232263582514a0c5
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Commit bd9c562a9e0c6af65f5e798a17ba9a55892ef082 ("acpi: Configure
slp-s0 residency counter frequency in LPIT table") led to jenkins
reporting the following error:
!!!!! Error: defined(CONFIG_ACPI_SOC_INTEL_SLP_S0_FREQ_HZ)
used at src/include/acpi/acpi.h:457. Symbols of type 'hex'
are always defined.
Since hex Kconfig are always defined there is no need to test it being
defined but also no need to handle zero or non-zero values.
In addition:
1. This config was defined in Meteor Lake specific Kconfig file while
it should actually be define closer to where it is being used (here
soc/intel/common/block/acpi/Kconfig) and only set by the SoC Kconfig.
2. Once moved and under control of `SOC_INTEL_COMMON_BLOCK_ACPI_LPIT'
gating (lpit.c), the Kconfig name needed to be adjusted to better fit
its use.
3. Make Meteor Lake Kconfig sets the config but does not define it
anymore.
TEST=LPIT ACPI table Counter Frequency field is set to 0x2005 on rex
Change-Id: I2083c9209e61be6180cca2c9f74097e2f4b4ce9a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78458
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
The microcode for RPL-S C0 and H0 is actually available, however, the
name of the file contained a typo: 06-b7-05 vs 06-bf-05. Fix the typos
in the comments.
Moreover, the ADL-S C0/H0 microcode file 06-97-05 has the same sha256
sum as the equivalent RPL-S C0/H0 microcode file 06-bf-05. The sha256
sum of ADL-S/RPL-S C0/H0 microcode on intel-microcode tag
microcode-20230808:
5d8d4a4d5456c43b7cc04937c80aec094ccbf3bd89f34ffa5182913ef944a9f9
Update the comments to correctly indicate supported CPU steppings.
Change-Id: I4c848e0dfc40f6c8e26a9b31e7c4cf4c5a09128f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78413
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The SCI handler for the GPE associated with the Super I/O did not clear
the respective PME status bits resulting in the SCI reoccurring
endlessly. The /proc/interrupts reported millions of ACPI interrupts
generated in just a few minutes of uptime. The flood of interrupts
caused some units to be unusable in extreme cases once attempted to
boot Qubes OS for example. On systems like Qubes OS it had a huge
impact on performance due to many IPCs the SCIs caused under Xen.
Clear the PME bits of devices that report a PME event. Then clear
the global PME status bit at the end of SCI handler to prevent the SCI
from asserting again until a new event occurrs. With this change
the number of ACPI interrupts generated in the first minutes of uptime
settles at a few thousands.
TEST=Boot Qubes OS R4.1.2 on Dell OptiPlex 9010 SFF and check
/proc/interrupts in dom0 if the number of ACPI interrupts is only
a few thousands.
Change-Id: I64e03d268138a62b46084be41343ef7fb089dfc3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
|
|
Remove the existing FSP 4221.00 headers subdirectory called
4221.00_google, and have Google vendor devices use FSP 4301.01.
BUG=b:306181828
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel.
Change-Id: Ic64b3aec62f0d6302278393bf06d090f43c0d592
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Package C-state auto demotion feature allows hardware to determine lower
C-state as per platform policy. Since platform sets performance policy
to balanced from hardware, auto demotion can be disabled without
performance impact.
Also, disabling this feature results soc to enter below PC8 state and
additional power savings ~30mW in Local-Video-Playback scenario.
Change-Id: I6ff408280178a24686180f72f79522d2741607a1
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78278
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
System sleep time (SLP_S0 signal asserted) is measured in ticks, for
Meteor Lake soc in 122us (i.e. ~8197Hz) granularity/ticks.
Change-Id: I1e95cd69e941d4d72d5c36a07660ca07ee2499ba
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Intel platforms use Low Power Idle Table (LPIT) to enumerate platform
Low Power Idle states. There are two types of low power residencies
a) CPU PKG C10 - read via MSR (Function fixed hardware interface)
b) Platform Controller Hub (PCH) SLP_S0 - read via memory mapped
Ref. https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf
System sleep time (SLP_S0 signal asserted) is measured in ticks,
varies in every platform and based on PMC clock.
BUG=b:300440936
TEST=check kernel cpuidle sysfs for non-zero residency after s0ix cycle
and both must match
cat /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
cat /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I401dd4a09a67d81a9ea3a56cd22f1a681e2a9349
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78164
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch ensures that the IGD joins the MBUS when the firmware splash
screen feature is enabled (aka BMP_LOGO config is enabled).
For ChromeOS platform, it prevents the i915 driver from reinitializing
the display, which can save up to 75ms-80ms of boot time and eliminate
a brief period of blank screen between the firmware splash screen and
the OS login prompt.
BUG=b:284799726
TEST=Able to build and boot google/rex.
Change-Id: I36af167afa902053a987602d494a8830ad9b1b1a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This patch implements `.final` hooks for the IGD device to perform the
required operations before handing the control to the payload or OS.
The MBUS (Memory Bus) is a high-speed interface that connects the
graphics controller to the system memory. It provides a dedicated data
path for graphics data, which helps to improve graphics performance.
The MBUS is a key technology that helps to make the Intel i915 driver
powerful and versatile graphics drivers available. It provides the
high-speed data transfer capabilities that are essential for smooth
and responsive graphics performance.
Enable this config to ensure that the Intel GFX controller joins the
MBUS before the i915 driver is loaded. This is necessary to prevent
the i915 driver from re-initializing the display if the firmware has
already initialized it. Without this config, the i915 driver will
initialize the display to bring up the login screen although the
firmware has initialized the display using the GFX MMIO registers and
framebuffer.
Kernel graphics driver can avoid redundant display init by firmware,
which can optimize boot time by ~15ms-30ms.
Ensures hashing mode is 1x4 to enable a single pipe between Pipe A or B.
Typically, internal display is on Pipe-A, so 1x4 restricts MBUS joining
to internal display alone.
BUG=b:284799726
TEST=Able to build and boot google/rex
Change-Id: I60ae76dc783383e027e66edbcdeeb535472caeb1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78385
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enabling support of WiFi SAR table for all rex variants by
setting the option at baseboard level.
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: I17709cb5d75b56c6c1f386ab527c5c8730011bed
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78308
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Sync'ing Karis' FW_CONFIG definitions stored in CBI,
```
_FW_MASKS = struct(
DB_USB = 0x00000003, # bit1~bit0
STYLUS = 0x00000004, # bit2
AMP = 0x00000038, # bit5~bit3
FAN = 0x000000C0, # bit7~bit6
MIPI_CAM = 0x00000300, # bit9 ~ bit8
FP_MCU = 0x00000C00, # bit11 ~ bit10
KB_TYPE = 0x00001000, # bit12
WIFI_TYPE = 0x00002000, # bit13
)
_FW_CONFIGS = struct(
DB_USB_UNKNOWN = hw_topo.make_fw_config(_FW_MASKS.DB_USB, 0),
DB_USB4_ANX7452 = hw_topo.make_fw_config(_FW_MASKS.DB_USB, 1),
STYLUS_ABSENT = hw_topo.make_fw_config(_FW_MASKS.STYLUS, 0),
STYLUS_PRESENT = hw_topo.make_fw_config(_FW_MASKS.STYLUS, 1),
AUDIO_ALC5650 = hw_topo.make_fw_config(_FW_MASKS.AMP, 0),
FP_MCU_ABSENT = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 0),
FP_MCU_NUVOTON = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 1),
FP_MCU_ELAN = hw_topo.make_fw_config(_FW_MASKS.FP_MCU, 2),
WIFI_TYPE_CNVI = hw_topo.make_fw_config(_FW_MASKS.WIFI_TYPE, 0),
WIFI_TYPE_PCIE = hw_topo.make_fw_config(_FW_MASKS.WIFI_TYPE, 1),
MIPI_UF_CAM_HI556 = hw_topo.make_fw_config(_FW_MASKS.MIPI_CAM, 0),
)
```
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: I1e4965c009edc595f24c04ac82d81aa0e723bbf3
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78261
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
WiFi SAR table for karis will be place into the CBFS later on and
as a result adding the hook in coreboot to make use of the SAR
table once the table is available.
BUG=b:290689824
TEST=emerge-rex coreboot
Change-Id: Ic989024ab9eb0fc439fc701c335a85986c4cfec5
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78260
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update default fan settings(FAN_SETTING_1) in FAN field.
Bit 6-7, FAN, 0 --> FAN_SETTING_1
BUG=b:290689824, b:294155897
TEST=Dump ssdt table and check fan settings is existed
Change-Id: Id69ec67202b5d769cd3a9a68344a6d8913ebd78b
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Commit 9b230ae2955 introduced a redefinition of the config option
`BOARD_GOOGLE_BROX`, which is already defined in Kconfig.name
accordingly and thus causing a Kconfig warning. Fix that by removing the
type redefinition.
Change-Id: Iea6219a686a23d8d48a0bfb6ac642efd482fded9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78394
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure GPIOs according to schematics revision 20231013.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: I1ccab46b9f622fb98920d316c31800f39dc8ff95
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78384
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Create the anraggar variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:304920262
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ANRAGGAR
Change-Id: I95e72188679fc825c94c4043ed02b0aad310c6a3
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
For Raptor Lake, select Raptor Lake's .fd file and header.
TEST=Boot to OS on Google Brya board with RPL silicon.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib3172b06b23e19be453142af764dd027bfe8043d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Disable SD card GPIO with fw_config for quandiso units without SD
card and pull GPP_H12 to high to match the spec.
BUG=b:296506936
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Iad6789d42b9a3f9b979fd481a88cc7d69db2dcfe
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Shawn Ku <shawnku@google.com>
|
|
This patch adds support for detecting dual displays (eDP and HDMI) on
Intel platforms. This information is useful for setting the
`lb_framebuffer.has_external_display` variable, which is used to
determine whether depthchage should avoid shutting down when an
extended display is present.
TEST= Able to build and boot google/rex, where depthchage now
successfully avoids shutting down when both eDP and HDMI displays
are attached.
w/o this patch:
with eDP and HDMI attached: .has_external_display=0
with eDP attached: .has_external_display=0
with HDMI attached: .has_external_display=1
w/ this patch:
with eDP and HDMI attached: .has_external_display = 1
with eDP attached: .has_external_display=0
with HDMI attached: .has_external_display=1
Change-Id: Ie39d48da75a21e3508a1fbcf09da31caedaa1c0a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78383
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iec6e05bbe9fad7d78002560b78169dc293294af6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78341
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
This code only gets built when the SOC selects
SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO which no SoC before Genoa
does.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia5495ebf0f157fd0c456ce44acaf1ab222a188dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
Due to copy-paste error, the UART2 device name is the same as
UART1. Fix it.
Change-Id: I796d09f321101a36731a56099af738c9485df8a2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
|
|
Reserve SBREG BAR if it is outside of the PCH reserved memory range.
Desktop series processors have larger SBREG BARs, which, unlike mobile
processors, do not fall into the standard PCH reserved range
(0xfc800000 - 0xfe7fffff). Create a separate reservation for such a case. There is no telling what could happen if the reservation is not
made in ACPI.
TEST=Boot Windows 11 and Ubuntu 22.04 on MSI PRO Z690-A DDR4
Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77445
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
BUG=b:301150499
TEST=Compiled and tested on google/redrix - PERST# goes low when wwan
modem goes into runtime suspend.
Change-Id: Ib09d5a6091cedfce24da49390cf980414f97a2c9
Signed-off-by: Paweł Anikiel <panikiel@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
|
|
When battery level is below critical level or battery is not present,
cpus need to run with a power optimized configuration to avoid platform
instabilities. This will check the current battery status and configure
cpu power limits properly.
BUG=b:296952944
TEST=Build rex0 and check cpu power limits are configured with
a performance efficient configuration and the platform boots to OS if
battery level is above the critical level. And check cpu power limits
are configured with a power optimized configuration and boots to OS
without an issue if battery is not present or battery level is at or
below critical level.
Change-Id: I12fd40abda76c8e7522b06a5aee72665f32ddec8
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78322
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This adds is_battery_present_and_above_critical_threshold to check the
battery is present and the battery level is above critical level.
BUG=b:296952944
TEST=Build rex and check is_battery_present_and_above_critical_threshold
returns the correct battery status.
Change-Id: Ib38be55bc42559bab4f12d5e8580ddc3e1a6acc1
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This CL is just getting the initial brox framework to get the
baseboard building. Copied files from brask baseboard and tried to
remove contents of some files like the device tree and memory IDs.
Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to
DRAM ID 0.
BUG=b:300690448
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a
Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
SATA controller isn't used & hence disable.
Change-Id: Iab2d597e6a0f22b946e657a2851b68f752d1f7d4
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77893
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The board has three SATA controllers, so add the remaining two
on PCI device 18.0 and 19.0.
TEST=Verify in lspci the sata controllers.
Change-Id: Ia654c4ef895b52338554d89c25f61b262fbbcbbb
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77892
Reviewed-by: Annie Chen <chen.annieet@inventec.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
|
|
BUG=NONE
TEST=Tested on Rex, touch over SPI works properly.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: If339f7a010fa51bf73b8898a55643b5e921d93b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Systemagent related functions are not used in this file. Remove the
unused the header file.
Change-Id: Ifbb04898e9dcebef96d8c73771e66e0d6fabc7fb
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78312
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update overridetree base on schematics revision 20230923.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78212
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To support an RPL SKU on dochi, it must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for dochi so that it will use the RPL
FSP headers.
BUG=b:299570339
TEST=emerge-brya intel-rplfsp coreboot
coreboot-private-files-baseboard-brya
Change-Id: I51c28744bd9f21fae58bad38abb01d38965140a4
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
|
|
Pull GPP_C1 to high in ramstage to meet touchscreen power sequence.
BUG=b:302236370
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
& test touchscreen function on quandiso DUT
Change-Id: Ia9f600ec0cc4be2d77ff08c0ae8951c90aec944f
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shawn Ku <shawnku@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
This updates NVM Configuration according to EEPROM BRCA016GWZ-W
datasheet for rex World Facing Camera module - O9B13-NT01BA to
enumerate Camera module properly.
BUG=b:301226048
TEST=Build rex0 and check SSDT table is updated correctly. Check
"cros-camera-tool modules list" lists up the modules properly.
cros-camera-tool modules list:
/sys/devices/pci0000:00/0000:00:15.0/i2c_designware.0/i2c-0/i2c-PRP0001:01/i2c-PRP0001:011/nvmem
/sys/devices/pci0000:00/0000:00:19.1/i2c_designware.4/i2c-13/i2c-PRP0001:03/i2c-PRP0001:032/nvmem
[ {
"module_id": "KC6977",
"sensor_id": "OV013b",
"sysfs_name": "i2c-0/i2c-PRP0001:01"
}, {
"module_id": "CH3c6d",
"sensor_id": "HN0556",
"sysfs_name": "i2c-13/i2c-PRP0001:03"
} ]
Change-Id: I51bdf249549d3e03180e9d126a85e9dff91028db
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78211
Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This reverts commit 5c35d30ffc7382af46b62044a5cf5326b1e57708.
Reason for revert: Here we need to confirm whether the issue in
mtl-staging-MTL.3323.92 has been improved in the QS sample
in the factory build.
BUG=b:287170545
TEST=Able to idle for more than 5+ hours without any hang.
Change-Id: I4517bbbefe11d95623d7e16a5e4bba2dd6f408e1
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78320
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf4a1fd61ad1d545b1ea0ab3fcf6c7a3d0260cd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
|
|
Confirmed with vendor, Elan touchscreen HID should set to "ELAN9004".
Correct Elan touchscreen HID to "ELAN9004" for karis.
BUG=b:294155897
TEST=Dump the SSDT on karis and check the HID had been modified.
Change-Id: I6ebb02540c894460388b9b9fe03f5c4031f8186d
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78266
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The write to register 0x42 has no effect as at this point all
of the bits are read-only. Drop the line.
Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78238
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Because integrated PCI devices are hidden in chip_ops
the PCI enumeration code never sees them.
When hiding static devices mark them as hidden so the
PCI enumeration no longer complains about them being
missing, even though they are present and were working
just fine.
Test: Disabled southbridge devices no longer appear in
"Leftover static devices:" log.
Change-Id: Iae70072a85b62a456102190a5f72f4d652ad6d5a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Warn when a device took longer than usual to appear.
Use the PDS bit to detect if a root port has a downstream
device connected and warn if enumeration failed.
Test: On Lenovo X220 all PCIe device are visible, thus the
added code path is never taken.
Change-Id: I86b498b89d672b239d9951e116dc3680030666a6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78229
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use defines instead of magic values.
Test: Lenovo X220 still boots and all PCIe devices are
still working.
Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
- Use pci_find_capability() and defines from pci_def.h
- Set the 'Hotplug Capable' bit and 'Hot Plug Surprise' bit in SLCAP
for hotplugable PCIe slots.
- Assign unique slot number and set power limit for PCIe root ports
that have a slot connected. For integrated devices clear slot number
and power limit.
Test: System still boots and all PCIe devices are working.
Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This reverts commit ee4191852abf9b24f822468250c24edb993497c6.
Reason for revert: In schematic a sdcard write protection pull-down
resistor was added, so need to disable GL9750 invert WP function
Change-Id: I00a8f43094d8b3674a4bbaeed24b96aab64b9b75
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78295
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This functionality will eventually be used by the common data fabric
domain resource reporting code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieedd432c144e53e43d8099ec617a15056bb36fd1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78307
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18871af0a8dbc1423524b681d516476e63b9596a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iefe61d25367bbe5cff0cacbfbafa32607de77d0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: I79ebbcc6a4a3a93e8437ef56aebdcf72f9a3e6ab
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76507
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I2e827e9ffbb2ec1be0f1247b77660a9fdeb04f7b
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add SMI definitions as per Genoa PPR Doc #55901
Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add GPIO definitions as per Genoa PPR Doc #55901
Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The tochscreen isn't powered on yet when the detection is done, it
makes touchscren no function.
Set touchscreen power and reset GPIOs correctly in romstage and
ramstage to make the detect feature works.
BUG=b:303130400
TEST=(1) emerge-rex coreboot
(2) Test on karis, touchscreen function works
Change-Id: I6c7815b81eb47fb41e58233fde512ac6b9c000a7
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78254
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
On ICH9 the SPI control register is not naturally aligned
and a word write might be split into smaller naturally aligned
I/O transactions.
As the first byte starts a new SPI transfer, replace the existing
word write with two byte writes and write the second byte first.
This is required for platforms that do not support unaligned
word I/O instructions and would start a SPI transfer while the
second byte hasn't reached the control register yet.
TEST: Virtual SPI controller on qemu 8.0 doesn't start a transfer
early.
Change-Id: Id05b1a080911b71b94ef781c6e26d98165f02f67
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
We have a tiny HEAP_SIZE by default, except when we don't, and
mainboards that override it, or not.
Since memory isn't exactly at a premium these days, and unused heap
doesn't cost anything extra, just crank it up to the highest value
we have in the tree by default and remove all overrides.
Change-Id: I918a6c58c02496e8074e5fba06e38d9cfd691020
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78270
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is in preparation of a larger heap. I went for 2MB because why not?
Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
