diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-10-04 20:18:27 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-12 12:41:17 +0000 |
| commit | 96cd78eae73ff202156bf4af8321dc2d974a4ca8 (patch) | |
| tree | d45982b5138c131767f3ca12de389fdc37a5af5b /src | |
| parent | 653459016d9fc6f13532e4bc9d52f98918602739 (diff) | |
sb/intel/bd82x6x/pcie: Drop register write
The write to register 0x42 has no effect as at this point all
of the bits are read-only. Drop the line.
Change-Id: I7293e6eaa2d0bac5efe8316029bdecb04a5586e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78238
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pcie.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 45ce5aadd3..325bfd2cd0 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -229,10 +229,8 @@ static void pci_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); /* Enable expresscard hotplug events. */ - if (pci_is_hotplugable(dev)) { + if (pci_is_hotplugable(dev)) pci_or_config32(dev, 0xd8, 1 << 30); - pci_write_config16(dev, 0x42, 0x142); - } } static void pch_pcie_enable(struct device *dev) |