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Enable Acoustic noise mitigation for blipper and set slew rate to 1/8
which is calibrated value for the board.
BUG=b:187760191
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test
Change-Id: I187702c23712416eaaaaf1e210dcfc6b2c560041
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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- set subsystem/subvendor ID to Realtek default, as the one dumped
from the vendor UEFI firmware provides no advantages
- Add a codec reset before setting the subvendor ID using the Azalia macro
for consistency with all other Realtek HDA codecs
- disable jack detect for the external mic on the 3.5mm jack, since it's not
currently working, so that the external microphone can be manually selected
Change-Id: Ib0f99e5088973a721c0a295899012c9aea5009cf
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- set subsystem/subvendor ID to Realtek default, as the one dumped
from the vendor UEFI firmware provides no advantages
- fix the number of verb entries, which excluded the 4 following the
pin configs
- issue the reset *before* setting the subvendor, and use the Azalia macro
- disable jack detect for the 3.5mm jack, both line out and mic, since
it's not currently working, so that the outputs can be manually selected
Change-Id: Icd961c3c5aec23cf61d6a9ad65c603c6dc04697a
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enable FastPkgCRampDisable for all domains, set SlowSlewRate to fast/16
for all domains. This aligns the settings with the Librem 14.
Test: boot Librem Mini v2, observe high frequency acoustic noise reduced.
Change-Id: I10bc2a3e6b631b8c0b430e204f376aa9a81ac683
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Somehow, enabling the notification to the OS driver breaks the
functionality it was meant to enable. Until this can be resolved,
disable the driver notification, so that the key functions as intended.
Test: build/boot librem_bdw and librem_skl boards, verify trackpad
enable toggle via Fn+F1 works properly.
Change-Id: Ic7bdb3154a87c4202b5ee1fd333281ef78db1104
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55657
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Decrease SA slew rate to match other domains and reduce
high-frequency noise slightly.
Change-Id: I02cd93481f6bfba6249cb338a0e2f47d471a438e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Only enable fingerprint device when FP=FP_PRESENT in FW_CONFIG.
BUG=b:186685292
TEST=Boot guybrush, no "EC failed to respond in time" error
Change-Id: Ifaea9e23e6cdfdae024464ff36c1520b8ad05e50
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If the early crtm is not initialised there is nothing to write to PCR
in the early tpm init.
Change-Id: I9fa05f04588321163afc817de29c03bd426fc1f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I84c8470764a4e6e09220044966111ffe72078099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55674
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CSE error codes may be applicable to move than just CSE Lite SKU errors,
therefore move this enum to the intelblocks/cse.h file so that it can be
used in other CSE-related code. While copying, remove `LITE_SKU` from a few
of the enum values that are not necessarily CSE Lite SKU-specific.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0351587c67ce12f781c536998ca18a6a804d080a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55672
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These southbridges are paired with MMCONF-enabled northbridges.
Change-Id: I0416de6425bb57471856731ad12ce8194ac98be2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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On dedede boards without Cr50, the CrOS Board Info (CBI) EEPROM write
protect signal is decoupled from the hardware write protect signal.
Instead, we'd like for it to mirror the software write protect status.
This commit simply checks the software write protect status of the SPI
flash and sets the CBI EEPROM write protect if it's enabled. To prevent
changing the WP signal at run-time, the GPIO configuration is also
locked down after the level has been set. If HW WP is deasserted, the
CBI EEPROM WP will be deasserted as well.
BUG=b:191189275,b:184592299
BRANCH=None
TEST=Build and flash lalala, disable SW WP by running `flashrom -p host
--wp-disable` from a root shell and verify that the GPIO is asserted
after a reboot. Export the gpio via sysfs and verify that attempting to
change the value of the GPIO is futile. Enable SW WP via `flashrom -p
host --wp-enable` and reboot the DUT. Again, export the GPIO via sysfs
and verify that attempts to change the GPIO value are futile.
localhost ~ # iotools mem_read32 0xfd6e08d0
0x44000200
localhost ~ # cd /sys/class/gpio/
localhost /sys/class/gpio # echo 217 > export
localhost /sys/class/gpio # cd gpio217/
localhost /sys/class/gpio/gpio217 # echo out > direction
localhost /sys/class/gpio/gpio217 # cat value
0
localhost /sys/class/gpio/gpio217 # echo 1 > value
localhost /sys/class/gpio/gpio217 # cat value
1
localhost /sys/class/gpio/gpio217 # iotools mem_read32 0xfd6e08d0
0x44000200
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ic103037921ec7d2f96f86178675c11a3a1357d1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This commit adds a method called `mainboard_smi_finalize` which provides
a mechanism for a mainboard to execute some code as part of the finalize
method in the SMM stage before SoC does its finalization.
BUG=b:191189275
BRANCH=None
TEST=Implement `mainboard_smi_finalize` on lalala and verify that the
code executes in SMM.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: If1ee63431e3c2a5831a4656c3a361229acff3f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This commit simply adds the offset for the PADCFGLOCK register for the
Intel Jasper Lake platform. This enables pads to be locked.
BUG=b:191189275
BRANCH=None
TEST=Enable pad locking on lalala by calling `gpio_lock_pad` and verify
that the pad configuration is locked and cannot be manipulated from the
OS.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Iccfe536b4a881f081f22bcc258a375caad3ffcb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55648
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This commit adds a method for locking a GPIO pad configuration and its
TX state. When the configuration is locked, the following registers
become Read-Only and software writes to these registers have no effect.
Pad Configuration registers
GPI_NMI_EN
GPI_SMI_EN
GPI_GPE_EN
Note that this is only effective if the pad is owned by the host (set in
the PAD_OWN register).
Intel platforms that wish to leverage this function need to define the
PADCFGLOCK offset for their platform.
BUG=b:191189275
BRANCH=None
TEST=With some other code, call gpio_lock_pad() against a pad and verify
that the pad configuration is locked and the state of the pad cannot be
changed from the OS.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Id3c0da2f6942099c0289ca1e33a33c176f49d380
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Ports are enabled according to devicetree.
BUG=none
TEST=Boot device, TBT should be functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I57e8eb13484014c17d24ad564643f0d03d11bc58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Per the Intel External Design Specification (doc #618876), the opcode
for GPIO_LOCK_UNLOCK is 0x13. This commit fixes a bug where the opcode
was defined as 13 decimal instead of hexadecimal. Additionally, it
fixes another issue where the `pcr_execute_sideband_msg()` function
doesn't actually write the data when this opcode is selected.
BUG=b:191189275
BRANCH=None
TEST=With additional code that uses this opcode, verify that the lock
functionality works by locking a pad in firmware and attempting to
modify the configuration of the pad from the OS.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ie14fff595474cdfd647c2b36f1eeb5e018f67375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55556
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:51638 separated Chrome OS NVS from global NVS by allocating it
separately in CBMEM. CNVS is used in depthcharge to fill firmware
information at boot time. Thus, location of CNVS needs to be shared in
coreboot tables for depthcharge to use.
This change adds a new coreboot table tag
`CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the
location of CNVS in CBMEM to payload (depthcharge).
Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the
end of GNVS instead of the fixed offset 0x1000. DNVS is used on older
Intel platforms like baytrail, braswell and broadwell and depthcharge
fills this at boot time as well. Since DNVS is no longer used on any
new platforms, this information is not passed in coreboot
tables. Instead depthcharge is being updated to use statically defined
offsets for DNVS.
BUG=b:191324611, b:191324611
TEST=Verified that `crossystem fwid` which reads fwid information from
CNVS is reported correctly on brya.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the raw values of the enum elements are used, explicitly assign
the value 0 to the first element to make it clearer that the absolute
values matter here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I69f58cca7130ce5f0ebe4743754e4e31f55db289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Using existing defines instead of magic values improves readability of
the code. Also add comments to the MADT IRQ overrides to make it clearer
what those actually do.
TEST=Timeless build results in identical binary for amd/gardenia
(Stoneyridge), amd/mandolin (Picasso) and amd/majolica (Cezanne)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I224ffbe8eb65bcdd5fc70c0ff8b15d55b3f6be01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55613
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add mt6691 buck control for DRAM to run fast calibration test.
It is needed to get and set voltage during testing.
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Change-Id: I4fb9f7245d44383a6a3a0cf8d00f7f503cbdeb06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55575
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To enable display, we have to:
1. Configure panel power and backlight
2. Configure eDP driver
BUG=b:189985956
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: Ida6c157a6a3bd904d3fa3dd2001385ced34f7711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55574
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:189985956
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I37326ad053295aa4944c8291e4e7a7d69c8f3f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55573
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch fixes the storage size to reflect the proper bits instead
of bytes. It was a bug in the initial HEST patch
(https://review.coreboot.org/c/coreboot/+/52090), and commit ID d4db36e672644ac7f528d12c5ce3539725456085 . Also fixed the
comments to properly reflect the range being used.
Change-Id: I9e968bb09f1c9cd805ff1d0849551b9c2ce2e2b6
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55393
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the default rom size to 32MB and remove chromeos.fmd
because Chrome OS is not supported on EHL for now.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I49d9404eb901087037b5423a4a503c5271e14138
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add FSP_ARRAY_LOAD macro for checking and loading array type
configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ia20cabcaf9724882c68633eb9b510230e993768c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Use FSP_ARRAY_LOAD macro for checking and loading array type
configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I2562977e55f8909038697f7e19b82ec6b5e47fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Add FSP_ARRAY_LOAD macro for checking and loading
array type configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I307340a2bfc0a54f2ab7241af2f24dfbf8bb111d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55559
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=None
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I932178dc395a4a96682a2e2076131feb3342aa52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55597
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 926949d64c1d8ef49dcc6774dd8535a2cb1fd423 (drivers/intel/gma:
Restructure IGD opregion init code) accidentally dropped this print
statement. As it can be useful for debugging purposes, add it back.
Change-Id: Iebd9e02bccc77538c0eed1e549294408586322f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55567
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia91dbda44f60388324cf58dbccdbd2172dbff21d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55561
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes unnecessary __packed attribute from the structure
defined in chip.h
BUG=None
TEST=Tested WFC camera on Brya
Change-Id: I1174606cd22cd353f01d865d0c25bb6f8f8de055
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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change binary board ID to tri-state mode.
BUG=b:190250108
BRANCH=None
TEST=emerge-trogdor coreboot
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I79d1212abc227341be126969ef32e76a635cbdaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55563
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Due to latest corresponding UPD filling implementation, this is not
required.
This patch fixed the brokenness caused by
Commit hash b10afbd2e2a8326fb21dc726a6c2bd53b06eb010.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Turn on CBI and add helper functions for determining the board
configuration from the firmware config settings in CBI.
BUG=b:187316460
TEST=Built
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Factoring out those defines brings the Stoneyridge SoC code a bit more
in line with the Cezanne and Picasso SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change also restores GPIOs to their proper settings for prior board
revs.
BUG=b:189362981
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I89d7ba94dfbd5e4a000cdde7a0c65f38b53b722d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55325
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Configure I2C high / low time in device tree to ensure I2C
CLK runs under I2C_SPEED_FAST (400 kHz).
Touchpad: 387.7kHz
Touchscreen: 389.4kHz
Audio: 387.6kHz
P-sensor: 372.5kHz
BaUG=b:178092096
BRANCH=dedede
TEST=Build and EE check after tuning I2C clock is under 400kHz
Change-Id: I4f6bdd3802cd94671325a89458cde981a2ffa929
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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google_chromeec_get_event returns an event number and 0 when there's no event.
This function is usually called in a loop until there are no more events, so
it makes sense to return 0 (i.e. no event) when there's an error.
BUG=b:184074997
TEST=Boot guybrush, no ec errors
Change-Id: I6c0186e4637af9ae24f45cce3638f0913227d6a7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The GPIO_GSC_AP_INT itself is active low, but the payloads will
create the IRQ using its eint driver, which is active high.
BUG=b:188392736
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie39f3b9a5dbe15057ef3e96f6c99211949692003
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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BUG=b:189985956
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Change-Id: I2b68f6342e7d46d90ea0e7aef9a01ecfd35f8fa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Any chip entry without a device node below them are silently dropped by
sconfig. Copy the same device node from the devicetree to prevent this.
Change-Id: I778f6b2d980e78142ae12ef941e7d9bd1f753057
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55540
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"corredsponding" --> "corresponding"
Change-Id: I0b0e5d461de29583c269896911167f8a44d84c2a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55555
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I7e37d32251fa3dcc64aec62dd2d814463c4a9999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55580
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the default state of the MMIO UART devices in the chipset
devicetree is off, the mainboard devicetree entries that disable MMIO
UART devices are removed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Defining the memory mapped base in fmap for example "FLASH@0xff800000
0x80000" for a 8M flash is optional in fmap files. This will also
reflect in the generated fmap_config.h. Fix the assembly cbfs walker
walkcbfs.S for fmap lacking a definition of the flash base.
Change-Id: I96b18f675e625abee503648ffdc6031978a4269a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Create the cappy variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:190515828
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CAPPY
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Id5a3b0cb475ee77a9f62523d8322a5e4123ce3be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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devfn_disable() function is used to disable a device based on
given bus, device function number. This function checks if the
device is at enable state and disables the device.
Change-Id: Ia4a8bfec7fc95c729a5bb156f88e9aab3bf5dd41
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add camera support in devicetree.
BUG=b:190797339
BRANCH=None.
TEST=built pirika firmware and verified camera function is OK.
Change-Id: I66ded32105f3166e2faec3ea5dcfb93c29822366
Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55450
Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to meet timing requirement of WWAN reseting it in early GPIOs
and asserting Reset GPIO in ramstage
BUG=b:180166408
TEST=Build and boot Brya system and verify enumeration of L850 and FM350 devices
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Id6d69696b6c645eec3fa314a608c69214bafba82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54912
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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pmc_set_power_failure_state() is usually called twice, once upon boot
(with `target_on == true`) and once from SMM when the system is shut
down (with `target_on == false`). Assuming settings didn't change
between these calls, there is only one case where we actually need
to write the register value: when updating the state for the
MAINBOARD_POWER_STATE_PREVIOUS feature.
This suits us well as we want to avoid unnecessary writes so we
don't clobber the value set upon boot from within SMM. Due to
inaccessible option backends, SMM might not know the current
option state.
The assumption above, that the option value didn't change, may not
be true if the user changed the option on purpose. In the future,
one would have to reboot the machine for option changes to take
effect. However, this doesn't seem to make a huge difference: One
already needed a controlled shutdown for the update to take effect
before. A reboot doesn't seem much more expensive.
Change-Id: I58dd74b8b073f4f07db090bf7fddb14b5df8239a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55539
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch create separate helper functions to fill-in required
FSP-M UPDs as per IP initialization categories.
This would help to increase the code readability and in future
meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly.
TEST=FSP-M UPD dump shows no change without and with this code change.
Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55225
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix build failures in the case <vc/.../chromeos.h> is removed.
Change-Id: Ie45066f39cd6fb92cca697a6bd5bc8bb8c60b4e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Updating the APOB takes a considerable amount of time. I decided to be
granular and split out the operations so we know when we read vs read +
erase + write.
BUG=b:179092979
TEST=Boot guybrush and dump timestamps
3:after RAM initialization 3,025,425 (44)
920:starting APOB read 3,025,430 (5)
921:starting APOB erase 3,025,478 (48)
922:starting APOB write 3,027,727 (2,249)
923:finished APOB 3,210,965 (183,238)
4:end of romstage 3,210,971 (6)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I08e371873112e38f623f452af0eb946f5471c399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Always clear vector 0 entry before optionally overwriting it
with the i8259 timer redirection.
Change-Id: Ia2e96f43e6494711f9fc4fd74229f5817b04b48d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55286
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I60ce17fd7640fab064a3d62d8d2b3703993c7b59
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55309
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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APIC Serial Bus pins were removed with ICH5 already, so a choice
'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG
0x3 is also not documented since ICH5.
For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was
wrong and ignored as BOOT_CONFIG register emulation was never implemented.
For ICH4 and earlier, the choice to use FSB can be made based on the
installed CPU model but this is now just hardwired to match P4 CPUs of
aopen/dxplplusu.
For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined
and the only possible operation mode there is APIC Serial Bus, which
requires no configuration.
Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6deb2a4c632d39112dcce71f076742a1b62ee89b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This a mainly a preparation for adding the MMIO UART devices to the
chipset devicetree.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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In acpi_soc_get_bert_region after the bert_errors_region call is was
checked if the region parameter is NULL after the call; since region is
a parameter of acpi_soc_get_bert_region, it's non-NULL. What we should
be checking here is if region points to a non-NULL pointer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Coverity (CID:1457506)
Change-Id: I0523504d65725ab2d2df4db28a5dedd90697b917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie97bd6ad076f0ce35fc997d954a003a1252184e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7edae2142120dec9e11ef823b561401b7e0bc208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Even though the code is currently commented out, replace the magic
numbers with the existing defines.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0dbbadf71f2e5a4d23ee998e2aa0a8b67205845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9dfddb0d4f32a542fa652ff8c14e932c224f247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Replace the magic numbers with the existing defines.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d98ea8c5bb0e487c7eef0b0a1cdada9cb04df4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99cb03de8782a0eeeb505f567b982099b0e8a18d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:184978118
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I03554a151aa6a6d9e15d74c63cd02239b788808a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Lynx Point PCH ACPI reference code version 1.9.1 has two additional
magic steps, which were already present in Broadwell. Add them.
Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The printed values are unsigned, and should be printed accordingly.
Change-Id: Ie5edce914c389c70460b1ed3390731e3568340dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The typedef needlessly hides the actual type of the variables.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I58a58cd402ec679960f460e80b37ff2afb8e3974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This option is valid for Broadwell as well as Haswell.
Change-Id: I4f1e9663806bae279f6aca36f09a0c989c12e507
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Split up PCH Kconfig into a separate file. While we're at it, also sort
selected options alphabetically.
Tested with BUILD_TIMELESS=1, coreboot.rom for the Purism Librem 13 v1
remains identical when not adding the .config file in it.
Change-Id: Ic3ff982e7108bf2d25a22e56ac2fbb93070df164
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Lynxpont ---> LynxPoint
Change-Id: I5af67079ead389beeafd9172aa1b98980dacbd38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The BMC EEPROM layout has been updated to contain system and mainboard
serial numbers. Use these values in SMBIOS Type 1 and Type 2 tables.
Change-Id: I55b51a856b4ad28fd56b02015b2e1d49cd629735
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55275
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These macros were used to generate ACPI P-state entries, but Broadwell
now uses Haswell CPU code. These macros are unused and can be removed.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: Ib2baca2964d9177e7ab6630d4ced22c5d332fb6e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Keep deduplicating code. Have Broadwell PCH ASL borrow some equivalent
Lynx Point ASL files, and drop the now-unused files from Broadwell PCH.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: If5a8712a846bbf7c42db92167763935dee74c26f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use hostbridge.asl from Haswell instead of Broadwell. Both files are
equivalent. Then, drop the now-unused hostbridge.asl from Broadwell.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Include Haswell memmap.h from Broadwell iomap.h to deduplicate identical
definitions. This also prevents the definitions from falling out of sync
while the unification process is ongoing.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I850e5521effba3818f4e2a13b94281bf07857d50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move the inclusion of `pci_irqs.asl` into PCH scope in order to allow
deduplicating northbridge ACPI code.
Change-Id: I541913226b26662f3798ae9c25ab1ac33cf2ed45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Taken from Haswell code. These resources also exist on Broadwell and
should be reported to the OS.
Change-Id: I45f2a6a9140d72c1cc2ee8b72621dc16c815b621
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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GDXCBAR and EDRAMBAR are accounted for when reporting resources to the
allocator, but they are not present in the DSDT. In addition, coreboot
does not enable either range, but MRC.bin sets up GDXCBAR and does not
disable it afterwards. Not reporting GDXCBAR in the DSDT can result in
resource conflicts, and not enabling EDRAMBAR can cause issues on CPUs
with eDRAM.
Enable both GDXCBAR and EDRAMBAR in coreboot code, and report these
ranges in the DSDT. This matches what Broadwell does. The value for
the `GDXC_BASE_ADDRESS` macro matches what MRC.bin programs as well.
Tested on Asrock B85M Pro4 with an i7-4770S (no eDRAM):
- Still boots
- EDRAMBAR is now enabled with base address of 0xfed80000
- GDXCBAR is still mapped with base address of 0xfed84000
Change-Id: I5538873b30e3d02053e4ba125528d32453ef6572
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add defines for the sizes of northbridge MMIO windows and use them where
applicable. The macro names have been taken from Broadwell.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I845cba8acbd478cd325d2e364138336d985f9c34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Intel document 493770 (Haswell BIOS Writer's Guide) revision 1.8.0
recommends writing all ones to the IA32_MCi_CTL registers in order
to enable all MCA error reporting.
Change-Id: Ib5d2c759483026b5b4804c5a4b2b969d2269af22
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55463
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboard information can be found in the included documentation.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ic811e24bd72da84e5ca8f5b09f2eb65872153b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55111
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is only called locally.
Change-Id: Ie3eaf659a2868eee1d4688885495c413f94f42e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DP_INTF0 directly.
Add ddp gclast and output_clamp settings on mt8195 to support
multi-layer display.
BUG=b:189985956
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Change-Id: I9d5dd1025c4766218c2b1d86b9b1f97f2eab53d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55509
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1) FSP-S should not run XIP
2) Overriding the FSP-T location conflicts with the location set in
drivers/intel/fsp2_0
This fixes a regression caused by commit
0f068a600e (drivers/intel/fsp2_0: Fix the FSP-T position)
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/G6WRFITANOS2JEYG3GKB2ZNVCLUZ6W7P/
Change-Id: I381781c1de7c6dad32d66b295c927419dea7d8be
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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One of the Memory32Fixed entries covers the TXT private and public
spaces, and another covers the TPM registers. Update the comments.
Change-Id: I261d74c113fabf1d152964efd8c91de85eba4179
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Move locking CPU MSRs during CPU init instead of using
CONFIG_PARALLEL_MP_AP_WORK functions.
The AES Lock enable bit caused CPU exception errors as this should not
run on HT siblings. The set_aesni_lock() function takes care of that.
Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55098
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.
TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.
Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
TEST=Able to build and boot without any regression seen on ADL.
Change-Id: I92671992ec14fd2adca1635b0791ac8b456332e9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55292
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on EHL.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iadf9145a11f27ff0e182f146b6fe5a01e6cf3ed8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on TGLRVP.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ic9d91b711bab83de1911e0b7ea876f2ad018c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55330
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on dedede
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4919a1ec02df50bc41fd66d5f3a352108a7aa04c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type (struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled()
call.
TEST=Able to build and boot without any regression seen on CML.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib5df5fd32e2e2742d349754a942bf81ca505dd39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Replace all pcidev_path_on_root() and is_dev_enabled() functions
combination with is_devfn_enabled().
2. Remove unused local variable of device structure type
(struct device *).
3. Replace pcidev_path_on_root() and dev->enabled check with
is_devfn_enabled() call.
TEST=Able to build and boot without any regression seen on Reef.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I900038dd4b2e2d89b1236bbd26bec5f34483b9f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Trigger mode LAPIC_INT_LEVELTRIG was only used with LAPIC_DM_INIT,
specifically for (obsolete) Init Level De-assert.
Level LAPIC_INT_ASSERT is required to be set for all other delivery
modes other than LAPIC_DM_INIT.
This reverts the two above changes that X2APIC mode support introduced
to the IPI for LAPIC_DM_SMI.
Change-Id: I7264f39143cc6edb7a9687d0bd763cb2703a8265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Depending on how the "middle-end" (yes, the gcc developers are
serious about that) optimizer ends up mangling the code, there may
or may not be a complaint about x being used uninitialized when it's
clearly not used at all.
So instead, why keep x in the first place? memcpy(foo, NULL, 0) is
the same as memcpy(foo, some_uninitialized_variable, 0) in that it
does nothing.
Change-Id: Ib0a97c3e3fd1a2a6aff37da63376373c88ac595d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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