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2021-01-06nb/intel/sandybridge: Define and use `QCLK_PI` constantAngel Pons
To allow adjusting the phase shift of the various I/O signals, the memory controller contains several PIs (Phase Interpolators). These devices subdivide a QCLK (quarter of a clock cycle) in 64 `ticks`, and the desired phase shift is specified in a register. For shifts larger than one QCLK, there are `logic delay` registers, which allow shifting a whole number of QCLKs in addition to the PI phase shift. The number of PI ticks in a QCLK is often used in raminit calculations. Define the `QCLK_PI` macro and use it in place of magic numbers. In addition, add macros for other commonly-used values that use `QCLK_PI` to avoid unnecessarily repeating `2 * QCLK_PI`, such as `CCC_MAX_PI`. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: Id6ba32eb1278ef71cecb7e63bd8a95d17430ae54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-01-06soc/intel/alderlake: Update CPU microcode patch base address/sizeSubrata Banik
This patch updates CPU microcode patch base address/size to FSP-S UPD to have second microcode patch loaded successfully to enable Mcheck flow. This is new feature requirement for ADL as per new Mcheck initialization flow. BUG=b:176551651 TEST=Able to reach beyond PC6 without any MCE. Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-05mb/google/zork: enable wake on MKBP eventsPeter Marheine
The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C connections enter DP alt mode, which should wake the system from S3. Configure S3 wake events to include MKBP so this actually wakes the system. BUG=b:174121852 BRANCH=zork TEST=Generating DP event on MKBP via EC console wakes morphius Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-05nb/intel/haswell/memmap.h: Clean upAngel Pons
Drop unused definition and remove outdated comments. Change-Id: I16033b558fe4c01a9394382dc0c9d0bdc66193d9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-01-05mb/google/zork: Add INT[E-H] to FCH PIRRaul E Rangel
INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC. BUG=b:170595019 TEST=Verify ezkinil still boots Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-05mb/google/volteer/var/voema: Enable IPU for voemaDavid Wu
Enable IPU for voema for MIPI camera. BUG=b:169551066 TEST=IPU is enabled and shows in lspci. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I34736bffd4dc61a840003afe5afd6a9c8dc32e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49002 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-05mb/clevo/cml-u: Rework KconfigFelix Singer
Rework Kconfig file so that each variant has its own config option with their specific selects / configuration and move common selects to a seperate config option, which is used as base for each variant. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: I1f5b6f535597149f28dd8c8322acc2e988f11505 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-05mb/clevo/kbl-u: Rework KconfigFelix Singer
Rework Kconfig file so that each variant has its own config option with their specific selects / configuration and move common selects to a seperate config option, which is used as base for each variant. Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: I1f07b5851ece6d0943faa9c90fc518805880a27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49060 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Daniel Maslowski <info@orangecms.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-05mb/siemens/chili: Rework KconfigFelix Singer
Rework Kconfig file so that each variant has its own config option with their specific selects / configuration and move common selects to a seperate config option, which is used as base for each variant. Built chili/base with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: I5e2a09db80232457b2f78ad9b100c468d281f753 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-05mb/kontron/bsl6: Rework KconfigFelix Singer
Rework Kconfig file so that each variant has its own config option with their specific selects / configuration and move common selects to a seperate config option, which is used as base for each variant. Built kontron/boxer26 with BUILD_TIMELESS=1, coreboot.rom remains the same. Change-Id: I08bd68aa2f98f93b8c5daf1ab2f3c1bbce521c53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-05mb/kontron/mal10: Remove unnecessary includesFelix Singer
Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Ibc6833d9256800d0e50651cac18a4e81ddbe6895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48144 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04mb/kontron/mal10: Move include directories to mb levelFelix Singer
Move include directories from carriers and variants to mainboard level being able to reuse them later. Also, rename guards so that they fit their usage. Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I55af05cb84b97d567ce1fc3b6151c34d1eda183f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48142 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04mb/purism/librem_cnl: Fix HDA verb NID count for Librem MiniMatt DeVillier
Fix off-by-1 count of NID entries. Change-Id: I65f70d084022c99233144b460542a793eae2acf3 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04ACPI: Final APM_CNT_GNVS_UPDATE cleanupKyösti Mälkki
All platforms moved to initialise GNVS at the time of SMM module loading. Change-Id: I31b5652a946b0d9bd1909ff8bde53b43e06e2cd9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48699 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04mb/google/hatch (baseboard): add ACPI backlight supportMatt DeVillier
Add ACPI backlight support for boards selecting BOARD_GOOGLE_BASEBOARD_HATCH. PUFF-based variants do not have an internal panel, so do not need this. Test: build/boot Windows 10 20H2 on google/akemi, verify display backlight controls functional. Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49058 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04mb/google/reef (and variants): add ACPI backlight supportMatt DeVillier
Enables backlight control under Windows 10. Test: build/boot Windows 10 20H2 on google/reef, verify display backlight controls functional. Change-Id: I4ce613badbdcfb9c843f52408df26c6cbb4b82a2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFGMaxim Polyakov
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used: ./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m": CB:43857 - 1/3 Decode raw register values CB:43858 - 2/3 Exclude fields for PAD_CFG CB:43411 - 3/3 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical. Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04drivers/vpd: Add support to read device serial from VPDMatt DeVillier
Add functions to read the system and mainboard serial numbers from VPD tables stored in flash. Remove board-specific implementations for google/drallion and google/sarien and select the new Kconfig instead. Test: build/boot google/akemi with RO_VPD region persisted from stock Google firmware, verify system/mainboard serial numbers present via dmidecode. Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49050 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04drivers/vpd: Add VPD region to default FMAP when selectedMatt DeVillier
Currently, use of the VPD driver to read VPD tables from flash requires the use of a custom FMAP with one or more VPD regions. Extend this funtionality to boards using the default FMAP by creating a dedicated VPD region when the driver is selected. Test: build qemu target with CONFIG_VPD selected, verify entry added to build/fmap.fmd. Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-04soc/intel/baytrail/southcluster.asl: Use consistent comment formattingMatt DeVillier
Change-Id: I479e1eb5819c42621e8b17367b964124d5433378 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04soc/intel/baytrail: add LPEA resources to southcluster.aslMatt DeVillier
The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources using soc/intel/braswell/acpi/southcluster.asl as a reference. This patch alone is not sufficient for working audio under Windows on Baytrail ChromeOS devices, but it is a necessary component. Test: boot Windows 10 on google/swanky, observe LPEA device working properly. Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48745 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04arch/x86: Move .id section higherKyösti Mälkki
The (now removed) ID_SECTION_OFFSET=0x80 was actually the secondary address flashrom and FILO are looking for. The primary was 0x10, just below .reset. If .id does not collide with .fit_pointer, use the higher of the two locations. Change-Id: I0d3a58c82efd3bbf94f4bc80ec5bbc97d5b1c109 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48499 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04security/intel/txt/ramstage.c: Fix clearing secrets on CBNTArthur Heymans
intel_txt_memory_has_secret() checks for ESTS.TXT_ESTS_WAKE_ERROR_STS || E2STS.TXT_E2STS_SECRET_STS and it looks like with CBNT the E2STS bit can be set without the ESTS bit. Change-Id: Iff4436501b84f5c209add845b3cd3a62782d17e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47934 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04nb/intel/sandybridge: Replace memset with initializerAngel Pons
There's no need to use `memset` here. Change-Id: I0478bc3ff25b75bf0b554aa83ead6a63fcbd975c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-04mb/google/zork: update DRAM table for morphiusKevin Chiu
Remove index0 DRAM assignment since it doesn't use in any build. Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id BUG=b:175911098 BRANCH=zork TEST=emerge-zork coreboot Change-Id: I853a316c266afafeecff67b263005a77be316e2b Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48723 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04mb/google/hatch: set Tianocore boot timeout to 5s for PUFF-based boardsMatt DeVillier
PUFF-based Chromeboxes need more than the 2s default in order to init an external display and show the boot splash/menu prompt. Test: build/boot WYVERN variant, ensure boot splash/menu prompt visible regardless of display init type used. Change-Id: Ie6d2151d28058501498a4c501bb221919b4e1b39 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04mb/google/{beltino,fizz,jecht}: Set Tianocore boot timeout to 5sMatt DeVillier
These Chromeboxes need more than the 2s default in order to init an external display and show the boot splash/menu prompt. Test: build/boot one of each variant, ensure boot splash/menu prompt visible regardless of display init type used. Change-Id: Ib90136b7e564451aff638af4d42abd97e42b3c19 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04mb/clevo/cml-u: Configure IRQ as level triggered for HID over I2CMichael Niewöhner
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx [2] https://review.coreboot.org/c/coreboot/+/47417/2/src/mainboard/google/hatch/variants/baseboard/gpio.c#b182 Tested successfully on Clevo L141CU. Change-Id: Ia232c0a11546aa6d17614f4cab07c255e58f2fed Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-04mb/google/octopus: Add ACPI backlight controlsMatt DeVillier
Enables backlight control under Windows 10. Test: build/boot Windows 10 20H2 on google/ampton, verify display backlight controls functional. Change-Id: I779f7f3f5a111018fc7b5c50c5750a9eb815d670 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04soc/intel/apollolake: Hook up GMA ACPI brightness controlsMatt DeVillier
Add struct i915_gpu_controller_info for boards to supply info needed to generate ACPI backlight control SSDT. Hook into soc/common framework by implementing intel_igd_get_controller_info(). Add Kconfig entries to set the correct register offsets for backlight frequency and duty cycle. Change-Id: Ia62a88b58e7efd90f550000fc5b2cef0cb5fade7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03mb/clevo/l140cu: add libgfxinit supportMichael Niewöhner
Change-Id: Id58bb2ce5fdaeaf158d02d8c812ab2c331db352d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48751 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03mb/clevo/l140cu: add panel settings to the dt and hook up GMA ACPIMichael Niewöhner
Add the panel settings dumped from vendor firmware and hook up drivers/intel/gma, which will be required for brightness control. Keyboard brightness control still requires ACPI code. This will be done in a separate change later. Test: Panel gets enabled when the payload starts on Clevo L141CU. Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-03drivers/intel/gma: add macro for one internal panel in gfx structMichael Niewöhner
Add a new macro `GMA_DEFAULT_PANEL(ssc)` as shortcut for specifying one internal panel at port A (0) in the devicetree. Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-03soc/intel: Drop indirect <soc/nvs.h> includeKyösti Mälkki
Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03soc/intel: Replace <soc/nvs.h> with <soc/device_nvs.h>Kyösti Mälkki
Change-Id: Ib78e746875e330e47540a6199343be62aa7e92a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48830 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki
Change-Id: I964f4340caa20124a15e52c055d2f27ba5113687 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03vc/google/chromeos: Move chromeos_set_me_hash() prototypeKyösti Mälkki
Change allows to remove some <chromeos/gnvs.h> exposure from coreboot proper. Change-Id: I7817914cc7b248331bb8fa79baa642ed548bbc11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48782 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-02soc/amd/picasso: Separate CPUID defs into new headerJason Glenesk
Move CPUID definitions out of msr.h into new cpuid.h header. BUG=b:155307433 BRANCH=Zork Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-02acpi: Add cb support to publish CRAT ACPI objectJason Glenesk
Add cb support to publish CRAT ACPI object in native coreboot. BUG=b:155307433 BRANCH=Zork Change-Id: I5fb7c15b11414f6d807645921c0ff1ab927e6e0f Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-01soc/intel/cnl: add panel and backlight configuration codeMichael Niewöhner
Add code for panel and backlight configuration. Tested successfully with libgfxinit on Clevo L141CU. Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-01nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settingsMichael Niewöhner
There are multiple different devicetree setting formats for graphics panel settings present in coreboot. Replace the ones for the platforms that already have (mostly) unified gma/graphics setup code by a unified struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt the devicetrees accordingly. Always ensure that values don't overflow by applying appropriate masks. The remaining platforms implementing panel settings (GM45, i945, ILK and SNB) can be migrated later after unifying their gma/graphics setup code. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-01soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representationMichael Niewöhner
For easier review of the switch to a new register struct in the follow-up change, the panel delay times get converted from destination register raw format to milliseconds representation in this change. Formula for conversion of power cycle delay: gpu_panel_power_cycle_delay_ms = (gpu_panel_power_cycle_delay - 1) * 100 Formula for all others: gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10 The register names gain a suffix `_ms` and calculation of the destination register raw values gets done in gma code now. Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-01soc/mediatek: dsi: Fix EoTp flagShaoming Chen
SoC will transmit the EoTp (End of Transmission packet) when MIPI_DSI_MODE_EOT_PACKET flag is set. Enabling EoTp will make the line time larger, so the hfp and hbp should be reduced to keep line time. BUG=b:168728787 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/48868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-01mb/google/kukui: Add panel api after dsi startJitao Shi
Some bridge chip or panel requires dsi signal output before dsi receiver works. BUG=b:168728787 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I3bded27087490f32ee233e615cfad1fd05fb582d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31coreboot_table: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki
Change-Id: I1e63a419db92642df6b7956050c39540c2ae11d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48781 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-31soc/intel/skylake: Remove device_nvs.hKyösti Mälkki
Change-Id: I9d500be609d61ccf234260216bd5aae3f78e91a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48802 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-31soc/mediatek/mt8192: Move flash_controller.c to common/Yidi Lin
The flash controller driver can be shared among mt8173 and mt819x. TEST=boot to kernel on Asurada boot to kernel on Hana (w/o BL31) Change-Id: I4e5213563189336496122a0f2d8077b3e5245314 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-31soc/mediatek/mt8192: Add DDR mode register initHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31soc/mediatek/mt8192: Do dramc duty calibrationHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I317451e41774e983c07566dc71c7ba8833c7f55e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31soc/mediatek/mt8192: Add dramc 8 phase calibrationHuayang Duan
To get better PI linearity, perform 8 phase calibration to do MCK 0/180/45 training and select the best PI settings. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-31soc/mediatek/mt8192: Update initial settings of dramcHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I08326cd1e6f7415d3a91d1591678e1b2c52c6781 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-30drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier
which select INTEL_GMA_ACPI. Rework brightness level includes and platform-level asl files to avoid duplicate device definition for GFX0. Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common platforms already do. Adjust mb/51nb/x210 to prevent device redefinition. Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for the IGD to exist, even if ACPI brightness controls are not utilized. This change adds a GFX0 ACPI device for all boards whose platforms select INTEL_GMA_ACPI without requiring non-functional brightness controls to be added at the board level. Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier
Adjust platform-level includes as needed. Change-Id: I376349ccddb95c166f0836ec1273bb8252c7c155 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30soc/mediatek/mt8192: eint: unmask eint event mask registerG.Pangao
eint event mask register is used to mask eint wakeup source on mt8192. All wakeup sources are masked by default. Since most MediaTek SoCs do not have this design, we can't modify the kernel eint upstream driver to solve the issue 'Can't wake using power button (cros_ec) or touchpad'. So we add a driver here to unmask all wakeup sources. BUG=b:169024614 Signed-off-by: G.Pangao <gtk_pangao@mediatek.com> Change-Id: I8ee80bf8302c146e09b74e9f6c6c49f501d7c1c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46409 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30soc/intel/cnl: add Kconfig values for GMA backlight registersMichael Niewöhner
Add the right register values for backlight control to CNL's Kconfig. To make iasl happy about the reversed register order, split the field. Change-Id: I05a06cc42397c202df9c9a1ebc72fb10da3b10ec Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-30mb/ocp/deltalake: replace "POST complete" mb code with driver functionalityMichael Niewöhner
Replace the mainboard-specific code for "POST complete" signalling with devicetree entries for using the newly introduced IPMI driver functionality. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Tested successfully. Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Change-Id: I3441c2a971cfb564b34b3a419beceb949fe295b1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30mb/supermicro/x11ssh-tf: configure "POST complete" gpio for IPMI driverMichael Niewöhner
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI driver and set the pad's initial value to 0 since the signal is active- high and shall be set by the IPMI/BMC driver. Also add the pad to early gpio config, since it is expected to have an external pull-up like X11SSM-F, which is wrong and would confuse the BMC. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Tested successfully. Change-Id: If344b2271bfc8d50b8b64847109818f96f2abbcb Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30mb/supermicro/x11ssm-f: configure "POST complete" gpio for IPMI driverMichael Niewöhner
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI driver. Also add the pad to early gpio config, since it has an external pull-up, which is wrong and would confuse the BMC. Set the pad's initial value to zero since the "POST complete" signal is active-high and shall be set by the IPMI/BMC driver. Test: Boot the machine via the BMC web interface and check that sensors get read correctly by the IPMI firmware when the payload starts. Tested successfully. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I6409b2aca90585e44ee5d32df0ae73b259443f32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30mb/supermicro/x11ssm-f: configure the BMC jumper JPB1Michael Niewöhner
Set `bmc_jumper_gpio` to the JPB1 gpio to enable/disable BMC/IPMI according to its value. Test: Boot with jumper set to each enabled and disabled and check debug log if IPMI gets enabled/disabled accordingly. Tested successfully. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8581556d915cbad2c743a79db273479ba55798fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30drivers/ipmi: implement "POST complete" notification functionalityMichael Niewöhner
Some server boards like OCP Tiogapass and X11-LGA1151 boards use a gpio for signalling "POST complete" to BMC/IPMI. Add a new driver devicetree option to set the gpio and configure a callback that pulls the gpio low right before jumping to the payload. Test: Check that sensor readings appear in BMC web interface when the payload gets executed. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I34764858be9c7f7f1110ce885fa056591164f148 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30drivers/ipmi: add code to set BMC/IPMI enablement from jumperMichael Niewöhner
Some boards, like the Supermicro X11SSM-F, have a jumper for enabling or disabling the BMC and IPMI. Add a new devicetree driver option to set the GPIO used for the jumper and enable or disable IPMI according to its value. This gets used in a follow-up change by Supermicro X11SSM-F. Test: Boot with jumper set to each enabled and disabled and check debug log if IPMI gets enabled/disabled accordingly. Successfully tested on Supermicro X11SSM-F with CB:48095. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Icde3232843a7138797a4b106560f170972edeb9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-30soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner
This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29Revert "mb/google/brya: Initiate peripheral buses"Felix Singer
This reverts commit 5bb5c43b936f0bb01e08a71df1865343d7be9b88. Reason for revert: Build bot fails. Change-Id: I8f022514351b37be135d10ef8486e4aa5fd6361b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48980 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delayMichael Niewöhner
Correct the mask for the power cycle delay from 0xff to 0x1f, to represent the actual maximum value according to Intel graphics PRM for Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c. Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29soc/intel/alderlake: Update chipset.cb for TCSS and USBEric Lai
Follow TGL chipset.cb to add alias for TCSS and USB ports. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29soc/intel/skylake: Add 4 missing root ports to chipset dtFelix Singer
The Kaby Lake PCH can have up to 24 PCIe root ports. Thus, add 4 missing root ports to the chipset devicetree. Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48947 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29mb/google/poppy/natutilus: Add missing PR dependencyRicardo Ribalda
On commit 64c03e3c ("mb/google/poppy: Fix race condition in acpi"), we introduced a new Power Resource common to all the camera modules, in order to resolve a race condition when both modules were in use (e.g. during startup). The nautilus variant also used the Power Supply I2C2.PMIC.OVTH, which requires the new common PR, but the new dependency was not added. Depend on the new Camera Common Power Resource. Fixes: 64c03e3c ("mb/google/poppy: Fix race condition in acpi") BRANCH=poppy BUG=b:174941580 Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Change-Id: Ifa6c70b7c02aec0112189eca573e76e53175d70d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: shkim <sh_.kim@samsung.com>
2020-12-29mb/google/brya: Initiate peripheral busesEric Lai
Initiate peripheral buses based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-29sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurableArthur Heymans
More recent platforms (Cooperlake) need bigger sizes. Change-Id: Ia3e81d051a03b54233eef6ccdc4740c1a709be40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-29soc/mediatek/mt8192: Implement dramc base settings for each frequencyHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I50d5aebaf249ab7292fad7a0046099239c8b403c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-29mb/clevo/n13xwu: Disable GMM PCI deviceFelix Singer
We don't know exactly for what the GMM PCI device is used for or how it is used. Thus, remove it to fallback to default-disable. Change-Id: I4b8b33b16527cbcc21168b995cbfdb54a2fa3cac Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-29mb/clevo/n130xu: Remove disabled devices from devicetreeFelix Singer
All known on-chip PCI devices are documented in chipset devicetree now and default to disabled. There is no need to keep disabled PCI devices in the mainboard's devicetree. Thus, remove them. Change-Id: I7c537bba75d66badf854f9e7b6799303a7af018e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-28device/pnp: add register PNP_IO4Michael Niewöhner
Add the register PNP_IO4, which will be used by IT5570E in CB:48894. Change-Id: Ic820295247323f546d4c48ed17cfa4eab3dc5e92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48924 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28device + util/sconfig: introduce new device `gpio`Michael Niewöhner
Introduce a new device `gpio` that is going to be used for generic abstraction of gpio operations in the devicetree. The general idea behind this is that every chip can have gpios that shall be accessible in a very generic way by any driver through the devicetree. The chip that implements the chip-specific gpio operations has to assign them to the generic device operations struct, which then gets assigned to the gpio device during device probing. See CB:48583 for how this gets done for the SoCs using intelblocks/gpio. The gpio device then can be added to the devicetree with an alias name like in the following example: chip soc/whateverlake device gpio 0 alias soc_gpio on end ... end Any driver that requires access to this gpio device needs to have a device pointer (or multiple) and an option for specifying the gpio to be used in its chip config like this: struct drivers_ipmi_config { ... DEVTREE_CONST struct device *gpio_dev; u16 post_complete_gpio; ... }; The device `soc_gpio` can then be linked to the chip driver's `gpio_dev` above by using the syntax `use ... as ...`, which was introduced in commit 8e1ea52: chip drivers/ipmi use soc_gpio as gpio_dev register "bmc_jumper_gpio" = "GPP_D22" ... end The IPMI driver can then use the generic gpio operations without any knowlege of the chip's specifics: unsigned int gpio_val; const struct gpio_operations *gpio_ops; gpio_ops = dev_get_gpio_ops(conf->gpio_dev); gpio_val = gpio_ops->get(conf->bmc_jumper_gpio); For a full example have a look at CB:48096 and CB:48095. This change adds the new device type to sconfig and adds generic gpio operations to the `device_operations` struct. Also, a helper for getting the gpio operations from a device after checking them for NULL pointers gets added. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28drivers/intel/gma: drop unused register to resolve name conflictMichael Niewöhner
The register `ESR` conflicts with the `Exception syndrome register` in UDK2017. To resolve the conflict, drop the unused `ESR` register from gma registers. It can be readded and prefixed or renamed if it's required at a later point. Change-Id: Icfdd834aea59ae69639a180221f5e97170fbac15 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28drivers/libgfxinit: Add Comet Lake to supported platformsFelix Singer
Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I002ade555c0544e4ef738c1ad45ee3d8aa38e03e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-283rdparty/libgfxinit: Update for Cannon Point supportNico Huber
We missed that Cannon Point, the PCH usually paired with Coffee, Whiskey and Comet Lake, differs a bit from its predecessors. Hence, libgfxinit now has a new Kconfig setting for the PCH. Change-Id: I1c02c0d9abb7340aabe94185ee5e17ef4c2b0d36 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28mb/kontron/bsl6: Remove disabled devices from devicetreesFelix Singer
All known on-chip PCI devices are documented in chipset devicetree now and default to disabled. There is no need to keep disabled PCI devices in the mainboard's devicetree. Thus, remove them. Change-Id: I0f78dadd9e55a8f002394dc07ab514ca13f4e963 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28soc/intel/apl: Fix indentsFelix Singer
Change-Id: Ide10889ad01ec6d31ee83158182876625a68a5da Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48888 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28soc/intel/xeon_sp: Lock PAM and SMRAM registersArthur Heymans
The CedarIsland FSP Integration recommends locking down some things. Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47168 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28soc/intel/xeon_sp: Lock down IIO DFX Global registersArthur Heymans
This is required for CbNT. Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28soc/intel/xeon_sp: Lock down DMI3 PCI registersArthur Heymans
This is required for CBnT. Change-Id: If5637eb8dd7de406b24b92100b68c5fa11c16854 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28soc/mediatek/mt8192: add rtc MT6359P driverYuchen Huang
Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor mt8173 and mt8183 code by extracting common API. Move rtc_read and rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via pmic wrapper, while mt8192 accesses it via pmif. Reference datasheet: Document No: RH-D-2018-0101. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28soc/mediatek/mt8192: devapc: add basic devapc driversNina Wu
Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28soc/mediatek/mt8192: Do dramc pre-settings before calibrationHuayang Duan
Before calibration, dramc resets the delay of each PHY IO, calculates TX path and sets CKE to be rank independent. Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-28kconfig: remove non-existent sourceJack Rosenthal
src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the source statement. Also, no kconfig files under src/soc/intel/common/basecode/. Clean that up. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-28soc/intel/skylake: Enable CHAP device depending on devicetreeBenjamin Doron
Now that CHAP device is declared in chipset devicetree, hook it up to devicetree configuration. Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28sb/amd/pi/hudson: Enable use of common GPIO APIKyösti Mälkki
The code in soc/amd/common has an implementation of GPIO register space that is compatible with the hardware sb/amd/pi/hudson supports. Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-27mb/siemens/chili/base: Add SMBIOS slot descriptionsFelix Singer
Add SMBIOS slot descriptions for M.2 ports and remove duplicate comments. Change-Id: Ieff03ad3167aec054cdc6b67ddc20fc64394e347 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-27vpd: Add vpd_get_int() functionNico Huber
Change-Id: I1c1b5710a5236fe4a3bdda1fc978393e636e9817 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45773 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-27src/superio: trim and move Makefile.inc, instead use wildcard matchesIdwer Vollering
Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: If77d59485451c77dcea752bc4fe0dfadba8fec45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48900 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25cpu/intel/model_206ax: Add more CPU steppingsAngel Pons
The Sandy Bridge steppings appear in the BWG, and Ivy Bridge steppings appear in reference code. Add them for the sake of completeness. Change-Id: I7d17cdd04a771ca319c908fc757f868e95ea7944 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-25nb/intel/sandybridge: Move steppings to CPU headerAngel Pons
The steppings correspond to the CPUID bits 3:0, so move them to the CPU scope, and include the CPU header from files using the stepping macros. Change-Id: Idf8fba4911f98953bb909777aea57295774d8400 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48409 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-25nb/intel/sandybridge: Rewrite constant valuesAngel Pons
Rewrite some constants to make their meaning somewhat clearer. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I321f5e61d7c695ae77e61b84728e34930f69d400 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25nb/intel/sandybridge: Allow to ignore XMP voltageAngel Pons
Native raminit only supports 1.5V operation, but there are DIMMs which request 1.65V operation in XMP profiles. Add an option to force XMP to be used when the requested voltage isn't supported, which will run the DIMMs at 1.5V with XMP timings. Consider this to be overclocking. Change-Id: I64bfac8f72dadf662ceadfc7998daf26edf5a710 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-25ACPI: Allocate GNVS early in ramstageKyösti Mälkki
We need this to happen prior to SMM module loader. If there is some debugging output it's better they do not appear in the middle of CPU bringup. Change-Id: I45b4b5c0c5bf8bee258a465d1e364bfe98190e44 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25ACPI: Fix some GNVS field commentsKyösti Mälkki
Change-Id: I0d1e7b86d5b98da85bf539a4a3ec23e0eeaa4dfc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-25sb,soc/intel: Fix GNVS OperationRegionKyösti Mälkki
Structure with chromeos_acpi_t is expected to have size 0x1000. Only ones with device_nvs_t have size 0x2000. Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-25mb/google/dedede: Update galtic device treeFrankChu
Update galtic device tree override to match schematics. BUG=b:170913840 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/48656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>