diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-28 15:00:39 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-29 20:19:52 +0000 |
| commit | 3054a1927983ef07cbc147ba776ea5d990571bdd (patch) | |
| tree | 87a6860bc1846b912661ed1eb4f0edd1c87a1453 /src | |
| parent | 4ea47c32b01d1604ec2b4d0b40b433454e62c520 (diff) | |
soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delay
Correct the mask for the power cycle delay from 0xff to 0x1f, to
represent the actual maximum value according to Intel graphics PRM for
Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c.
Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/gma.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 0bca230b64..71d5ab61ec 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -273,8 +273,8 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { reg32 = gtt_read(PCH_PP_DIVISOR); - reg32 &= ~0xff; - reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + reg32 &= ~0x1f; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index d42eebc4f1..c033b499f5 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -314,8 +314,8 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power Cycle Delay */ if (conf->gpu_panel_power_cycle_delay) { reg32 = gtt_read(PCH_PP_DIVISOR); - reg32 &= ~0xff; - reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; + reg32 &= ~0x1f; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; gtt_write(PCH_PP_DIVISOR, reg32); } |