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Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL are to fix the pad's reset field
as needed. See "Intel SoCs" section in
https://doc.coreboot.org/getting_started/gpio.html for reset
definitions.
BUG=b:300690448,b:316180020
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes in this CL include fixing the pulls for
GPIOs as necessary, making sure that it matches what is in the HW
team's spreadsheet.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: Ie50cb3c6fc85f1633c1afd1330c0e040e04b0ec1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79704
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Did a pass through HW team's brox speadsheet and aligned the gpio.c
file with it. The changes here include changing the pad config to NC
because it is not being used in ChromeOS.
BUG=b:300690448
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I15471e4d7ff25c858b05ef024f15ca7c0b9e598e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79703
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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datasheet: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf
BUG=b:311336475
BRANCH=firmware-rex-15709.B
TEST=Build AP-firmware and test on karis, system can boot to OS.
Change-Id: Id952ba3a4a45a51571d3735cf6b5764cece2c5e4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79087
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add HDMI GPIO configuration to early GPIO list to support
VGA text o/p in Pre-RAM stage on HDMI.
BUG=b:316982707
TEST=Erase MRC cache and reboot, SOL text display on HDMI/eDP
Change-Id: Idb2af56baeb4d0ef9db5fc1c5dbcebecee6515e6
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79572
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Since the camera sensor and camera eeprom share GPP_A12, remove
the off timing to avoid issue of camera sensor loss, but this
will increase system power by 5mW.
(Before root cause, this is a short term workaround to unblock
function test.)
BUG=b:298126852
TEST=1. Run coldreboot/warmreboot check see if the camera sensor lost.
2. Run S0ix check to see if the camera function abnormal.
Change-Id: I49b6ecbfbf3dddd6575bdaaf9c8fd0ee6c09af25
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79647
Reviewed-by: Jason Z Chen <jason.z.chen@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
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set slew rate to 1/8 for GT domain.
BUG=b:312405633
BRANCH=none
TEST=Able to build and boot google/screebo
Change-Id: Ib5cb07b7effc4a51c2119183010a03e026f639f8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
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Some of the boards use the EC_SYNC pin to wake the AP but do not
advertise the pin as wake capable in the CREC _CRS resource. Relevant
boards were determined through empirical testing and inspection of gpio
configuration.
Update the ACPI tables for rex, brya, and brox based boards to advertise
their EC_SYNC pin as wake capable.
BUG=b:243700486
TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when
EC_SYNC_IRQ_WAKE_CAPABLE is defined
-Wake Aviko via keypress and verify chromeos-ec as wake source
-Wake Screebo via lid open and verify chromeos-ec as wake source
Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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UART0 is routed to a USB-serial converter chip on the Onyx board, so
also enable this UART in the devicetree, so that the OS will be able to
use this UART.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b2577d799fd82a0aa0c9b01324930237e204aa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:311450057
BRANCH=NONE
TEST=emerge-brox coreboot
Change-Id: I4a009076e50408a4f7ff16ddc96a0f2e47b09470
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79646
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Found-by: Coverity Scan #1489753
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4f3794cf17875cdb35010c79a6537a4c13a18224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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SATA_IDE_DEVID, AHCI_DEVID_MS and AHCI_DEVID_AMD are still kept even
though they're unused at the moment, but those might still be useful to
keep around, since the SATA controller can have different PCI device IDs
depending on in which mode it is in.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia05683b732d9748d9198225acaecbd4dc196733a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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GPP_B02 and GPP_B03 were set incorrectly previously.
This CL corrects these settings according to schematics.
BUG=b:305793886
TEST=Built FW image correctly.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id62f15f7a77ac43c72cc6b2645816d6c87133a0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Only EC will use field "PANEL_PWRSEQ_EC_CONTROL".
Add this field in coreboot for align fw_config settings.
BUG=b:314245238
TEST=emerge coreboot pass
Change-Id: Icecb44a338ddc28027e362332c6a69cc9fd268d5
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79570
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After confirm with thermal, only EC will reference FAN field in
fw_config.
Update the settings for align fw_config.
BUG=b:307822225
TEST=emerge coreboot pass
Change-Id: Id7c4cdba29c5500c06d0f2293495650bb14b9e9c
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79573
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
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Allow SoC code to set LAPIC access mode to X2APIC
Change-Id: I208cca35c328e1566a57aaaa8ee7809e0760261c
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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UART1 is selected for debug uart in Kconfig, it also needs to enabled
in devicetree. With this serial output doesn't stop during the device
enable step.
TEST:Build onyx_poc board
Change-Id: I7c910301c6eca5d3057785607139ac03b344bc15
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: I602cf024ec84b15b783d36014c725826f9d6595e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79418
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use same indent levels for switch/case in order to comply with the
linter.
Change-Id: Icf41e823c42ffea7b73bdd9112081af4d1f94bc9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
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These IDs are not used as crashlog data is not stored in CBMEM now.
(Ref CL: I43bb61485b77d786647900ca284b7f492f412aee
Title: soc/intel/common,mtl: Refactor BERT generation flow for crashlog)
BUG=b:298234592
TEST=Able to build REX.
Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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With earlier flow, a chunk of CBMEM region was allocated for each SRAM
e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM
content was copied to dedicated CBMEM region. Later in acpi_bert.c, the
BERT table was getting created for each chunk of CBMEM. This flow was
not considering creating separate entries for each region of crashlog
records. It resulted in only the first entry getting decoded from each
SRAM.
New flow aims to fix this issue. With new flow, a simple singly linked
list is created to store each region of crashlog records from all
SRAMs. The crashlog data is not copied to CBMEM. The nodes are
allocated dynamically and then copied to ACPI BERT table and then
freed. This flow also makes the overall crashlog code much simpler.
BUG=b:298234592
TEST=With this change decoding crashlog show comprehensive details,
tested on REX.
Change-Id: I43bb61485b77d786647900ca284b7f492f412aee
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The optimization of sleep time in acpi code includes reducing the sleep
duration and increasing the polling frequency within the acpi _ON/_OFF
method. StorageD3Enable is activated in Google/Rex, and this
optimization results in a saving of approximately 25ms in D3cold resume
time, reducing it from around 160ms to 135ms.
BUG=b:296206467
BRANCH=firmware-rex-15709.B
TEST=boot test verified on google/rex
verified _ON/_OFF Method in SSDT.
verifid kernel log in s0ix test -
0000:00:06.0: PM: pci_pm_resume_noirq
Change-Id: I7ba960cb78b42ff0108a48f00206b6df0c78ce7a
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Enable Acoustic noise mitigation for google/screebo and set slew rate
to 1/8 for IA domain and ignore the slew rate for SA domain.
BUG=b:312405633,
TEST=Able to build and boot google/screebo.
Before:
[SPEW ] AcousticNoiseMitigation : 0x0
[SPEW ] FastPkgCRampDisable for Index = 0 : 0x0
[SPEW ] SlowSlewRate for Index = 0 : 0x0
After:
[SPEW ] AcousticNoiseMitigation : 0x1
[SPEW ] FastPkgCRampDisable for Index = 0 : 0x1
[SPEW ] SlowSlewRate for Index = 0 : 0x2
Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79323
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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This patch allows to override acoustic noise mitigation FSP UPDs:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate
BUG=b:312405633
TEST=Able to override the acoustic noise UPDs.
Change-Id: I5295e6571121c92f363e6fd4bcb3c8335c4fedee
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79302
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Acoustic noise in PCBs is a common problem and be caused by a variety
of factors, including:
Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal
expansion.
This patch adds the UPDs to FSPM header file for mitigating the acoustic
noise.
FSPM:
1. AcousticNoiseMitigation
2. FastPkgCRampDisable
3. SlowSlewRate
BUG=b:312405633
TEST=Able to build and boot google/rex.
Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79301
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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This updates all warnings currently being printed under the files_added
and build_complete targets to the show_notices target.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCH identification functions and `pch_iobp_update` are used in multiple
stages. Move them out of `pch.c` to drop some ugly preprocessor usage.
Subsequent commits will use `pch_iobp_update` in romstage as well.
Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79624
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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when S0ix returns S0, PERST needs to delay until
Main 3V3 is stable and then pull up
BUG=b:313976507
TEST=emerge-rex coreboot,measurement waveform verify pass
Change-Id: I33a86e52fab3c5c8cba6ebed0cbdd1b88b6538b0
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79320
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For EVT SCH:
1. Use GPP_D15 to control AVDD and AFVDD simultaneously for MIPI Camera.
2. Delay reset for 5ms when device power on.
BUG=b:312663347
TEST=1. Google Camera app working
2. Passed EA verified
Change-Id: I880fb309fcef006090e2849fa6c3a0d472851851
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This option is nowhere selected and there is only a single case left
where it's used. Guarding the check in pci_rom_load() seems like a
bad idea: As the code would be copying all VGA ROMs to the same
location, it would be only working by chance (if the last encoun-
tered ROM is the right one). Hence, drop the guard and always check
for the correct device.
Change-Id: Ib283bf0a65367b99099a3bfcbd27585d44235eb9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79596
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There's neither need to remove get_hw_mem_hole_info from the code if the
Kconfig option was set to 0 nor the actual value didn't make any
difference in the behavior of the code: When node_id has still its
initial value of -1, domain_read_resources won't use the value of
hole_startk, and when node_id is set to 0, get_hw_mem_hole_info also
sets hole_startk to the actual value that then gets used by
domain_read_resources.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieffab695a3151ed7f6bf9d6c880bbb43eecf7893
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79609
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This APU is always a single-node, so the nodeid parameter of
get_node_pci is always 0. Since this SoC has a chipset devicetree, we
can just use DEV_PTR(ht_X) instead of the pcidev_on_root call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1bf9d214b4c2e5d995976fb79fef6fe43a6e9fa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79608
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This APU is always a single-node and since we're in ramstage when
domain_read_resources gets called, there's DRAM on this node, so no need
to check for this. To be extra sure, also initialize basek and limitk
before calling get_dram_base_limit with pointers to those as arguments.
This won't be necessary for the code to work as intended, but will
probably keep the compiler from complaining. Also move the declaration
of basek, limitk and sizek to the beginning of the function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ef8011eb57b16218b8f5fea295900b855c3014b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79611
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Start with the resource index 0 and increment it after reporting each
resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6fb59ff3d371b744b53093d17392d1c3510bef82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This APU is always a single-node and also only has one DRAM controller,
so there is only one valid DRAM base and limit register. It's also worth
mentioning that the assumption made in get_dram_base_limit that the n-th
node is using the n-tn DRAM range register was valid for K8, but not
necessarily on newer generations than that.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0529c66e8d0e6c8eb42eec2c6d9d2e892287865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79607
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This APU is always a single-node and also only has one DRAM controller,
so we don't need to loop over the different nodes to find the memory
hole below 4GB. We also don't need to check for the special case where
the memory hole is non-DRAM address space between the parts of the
address space decoded by different DRAM controllers.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9793d911d2d496be49168c06d83ceb802bc2b647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This APU is always a single-node, so domain_read_resources only needs to
handle exactly one node and doesn't need to loop over the nodes.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4218077cb4e11b762ce0e8694a97bdec33eaa056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This SoC only supports a single-node configuration, so all the code
related to multi-node support can be removed. In this commit only the
get_fx_devs function and related code are removed for better
reviewability. In f1_write_config32 it's no longer needed to loop over
the different devices of the different nodes, so only a single PCI
config space write remains.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dc7324d3fcd0d07ac7a3a246a740fd9e91c3840
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79604
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This APU is always a single-node system and bits 4..6 of the node ID
register D18F0x60 are also marked as reserved in BKDG #52740 Rev 3.05.
On an APU2 board with quad-core APU, this register reads back 0x00030000
which results in a value of 1 to be returned from get_node_nums, so this
patch doesn't change behavior, but stops using reserved bits.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65ed1124c0ca8e7eba54ff53dc626d35cd5e2e58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79603
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This system only has one northbridge and amd_initcpuio has already set
up the routing of the legacy VGA IO and MMIO ranges to it. Since only
the pci_dev_set_resources call remains in nb_set_resources, use
pci_dev_set_resources directly as set_resources function.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib3835db9fd83221ac2b8e34d998f938812d24413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Since the IOMMU is always function 2 of device 0 on bus 0, the device
operations can be statically assigned in the devicetree and there's no
need to bind the IOMMU device operations to the PCI device during
runtime via a list of PCI IDs.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84e949500ee86e0fcb2d15791502f5e3e7127703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79105
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Since the northbridge is always function 0 of device 0 on bus 0, the
device operations can be statically assigned in the devicetree and
there's no need to bind the northbridge device operations to the PCI
device during runtime via a list of PCI IDs.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7faaa468ff77e05c378c5555622c3584cfe3f81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.
TEST=tested on google/jinlon device and observed the issue is resolved.
BUG=b:260253945
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
datasheet: IS25WP256D Rev A13 (2023-08-03)
tested:
boot SiFive Hifive Unmatched board
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I655776258cbcf464becf38cbb5045cda5bca711c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
BUG=b:312099281
TEST=Build and boot to Karis. Verify the config from serial logs.
w/o this CL -
```
[SPEW ] ------------------ CNVi Config ------------------
[SPEW ] CNVi Mode = 1
[SPEW ] Wi-Fi Core = 1
[SPEW ] BT Core = 1
[SPEW ] BT Audio Offload = 0
[SPEW ] BT Interface = 1
```
w/ this CL -
```
[SPEW ] ------------------ CNVi Config ------------------
[SPEW ] CNVi Mode = 1
[SPEW ] Wi-Fi Core = 1
[SPEW ] BT Core = 1
[SPEW ] BT Audio Offload = 1
[SPEW ] BT Interface = 1
```
Change-Id: Icd2c42261fdcfa5aac17be28fde3804348ddf9b4
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch provides a way to mask the 3-strike error on Intel
Meteor Lake SoC platform across pre-prod and prod SoC.
This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types.
Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error.
BUG=b:314883362
TEST=Disable the 3-strike on google/screebo with QS silicon.
Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When caching the ramstage for suspend/resume, we copy the entire image
as it resides in RAM. The last part of that, CONFIG_HEAP_SIZE bytes, is
the heap that will be reinitialized when the ramstage is started again.
As such, copying doesn't make sense and complicates HEAP_SIZE
configuration (because it needs to fit the space-constrained cache
location) and costs time and space. Therefore, skip the heap.
Side notes:
- When building with ASAN, program.ld indicates that it will allocate
some more space after the heap. This is not a problem, we just copy
an ASAN-sized copy of the heap.
- Heap use is managed in src/lib/malloc with statically allocated
variables. Because ramstage is cached before it's executed, these
values will be reset to their compile-time default values, too.
Change-Id: I6553dc8b758196f2476af2e692c0421d0fa2b98e
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79525
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Update header files for FSP for Raptor Lake platform to version 4435_00,
previous version being 4301_01.
FSPM:
1. Options changed for Ppr Enable
2. Add 'Ppr Run Once' and 'Post Package Repair' UPD's
FSPS:
1. Add 'CpuPcieRpTestForceLtrOverride' UPD
MemInfoHob:
1. Structure updated
BUG=b:315234533
Kit: https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=793230
Cq-Depend: chrome-internal:6786881, chrome-internal:6787635
Cq-Depend: chrome-internal:6719974, chromium:5125983
Change-Id: I65b8a4b6c72f7ae3fff1ee6d073311d154cd6b69
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ce8ac00c015e34375c6b3c70496c97e2fe455bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
1. Anraggar doesn't support SDCard, so disable SDCard contorller.
2. Not disabling it will cause can't enter S0ix on first suspend.
BUG=b:313585586
TEST=1. check lspci
2. can enter S0ix on first suspend
Change-Id: Ie4747d9c5d6ae93d29ef78b629855e0dd320c4db
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This file is identical to the copy currently found in the blobs
repository; it is simply being relocated for consistency and since it
does not need to be in an external repo.
BUG=none
TEST=build/boot skyrim
Change-Id: I352f58e0d3965356f3282a2653c6c11b44853857
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
This file is identical to the copy currently found in the blobs
repository; it is simply being relocated for consistency and since it
does not need to be in an external repo.
BUG=none
TEST=build/boot guybrush
Change-Id: Ice4cbaccca13e9c4ae246fdcde5c89aa2086f1e1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
This file is identical to the copy currently found in the amd_blobs
repository; it is simply being relocated since it is mainboard specific
and does not need to be in an external repo.
BUG=none
TEST=build/boot morphius
Change-Id: Ia78fcd065fbf4d5ba6ec4edc3f8f937badf66ecc
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79591
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
For initial debugging, we want to disable SW syncing. Will re-enable
in the future.
BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
run gbb_utility --get --flags <image>
make sure that it returns 0xa39
Change-Id: I865e9585ab37d1328a0ff54c6343cdad2c02220c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79569
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
|
|
In commit 0a0945c6a211 (sio/nuvoton/npcd378: Use acpi_device_path_join),
some oversights were made. Instances of "strconcat(scope, ..." should be
replaced with "..._join(dev->bus->dev, ..." instead of "..._join(dev, ...".
On HP 8200 USDT, this fixes ACPI error like this on resume from S3:
ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.LPCB.SIO0.L040.RMFG], AE_NOT_FOUND (20230628/psargs-330)
ACPI Error: Aborting method \_GPE._L08 due to previous error (AE_NOT_FOUND) (20230628/psparse-529)
ACPI Error: AE_NOT_FOUND, while evaluating GPE method [_L08] (20230628/evgpe-511)
RMFG seems to be a typo of PMFG made in that same commit.
Change-Id: Ifffa7ad72cfdb644c8b5147132a5fd56511ed33b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Even though this mainboard is called 'Onyx', the openSIL implementation
and the corresponding coreboot integration is only a proof of concept
that isn't fully featured, has known limitations and bugs, and is not
meant for or ready to being productized. Adding the proof of concept
suffix to the name should point this out clearly enough so that no
potential customer could infer that this might be a fully functional
and supported implementation which it is not.
Change-Id: I157a8fffdc2a8543465fe8d444ac87f3f417389f
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77896
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
The openSIL code for the Genoa SoC is only a proof of concept, so change
the name of the Kconfig option to include this code in the build from
SOC_AMD_OPENSIL_GENOA to SOC_AMD_OPENSIL_GENOA_POC to clarify that this
is code that isn't intended or ready to be productized.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If91cdaa7c324426964bba2de2109b6c38482fab8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79574
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Even though this SoC is called 'Genoa', the openSIL implementation and
the corresponding coreboot integration is only a proof of concept that
isn't fully featured, has known limitations and bugs, and is not meant
for or ready to being productized. Adding the proof of concept suffix to
the name should point this out clearly enough so that no potential
customer could infer that this might be a fully functional and supported
implementation which it is not.
Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The default EPP is set at 50%, which is deemed insufficiently
aggressive for meeting the MTL performance expectations in
balance_performance mode.
# cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
balance_performance
# iotools rdmsr 0 0x774
0x0000000080003f06
EPP=45% is giving the required performance in MTL.
# iotools rdmsr 0 0x774
0x0000000073003d06
NOTE: Kernel changes are necessary to ensure that the EPP (Energy Performance Preference) configured in the BIOS is not overwritten: https://patchwork.kernel.org/patch/13461932
BUG=b:314275133
TEST=Build and boot.
Change-Id: I1953994cdb4e9363fdd4b4728e3e5236276c06c8
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79386
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Non-touchscreen sku will set related GPIOs to NC. If touchscreen enabled
in overridetree for non-touchscreen sku, the boot time will be 6-7s. Set
touchscreen probed to TOUCHSCREEN_UNKNOWN for reduce boot time from 6-7s
to under 1s.
BUG=b:316434359
BRANCH=firmware-nissa-15217.B
TEST=Boot time (cbmem -t) from 6,460,972 to 922,844
Change-Id: I016ce762f726b7624bd060284f74f0992cb129b6
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
Make sure that the APMC SMI command IO port is configured to what
coreboot expects and enable the SMI generation for the APMC SMI command
port.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie4fc259dea125a16556a01b80a3d5e6fb476044a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79531
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
All the resource on the host bridge are fixed resources and therefore
have the IORESOURCE_STORED flag set, so the body of this function which
configures IO or MEM ranges is never reached.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1839f030a4a365e5bc1cdaa3cf37cdf9ca382ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79385
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
This commit lays the groundwork for implementing the ACPI WDAT (Watchdog
Action Table) table specification. The WDAT is a special ACPI table
introduced by Microsoft that describes the watchdog for the OS.
Platforms that need to implement the WDAT table must describe the
hardware watchdog management operations as described in the
specification. See “Links to ACPI-Related Documents”
(http://uefi.org/acpi) under the heading “Watchdog Action Table”.
BUG=b:314260167
TEST=Mock the acpi_soc_fill_wdat function for a specific platform/soc
and enable ACPI_WDAT_WDT in the kconfig. Check if the build passes
successfully.
Change-Id: Ieb82d1f69b2b7fffacfd2928bc71f8ff10498074
Signed-off-by: Marek Maslanka <mmaslanka@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
|
|
FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:302465393
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I301a6e43f2944ffbc63431393378ab8b23450032
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This patch introduces a new API to disable signaling the 3-strike event
on Intel Meteor Lake C0 (QS) stepping and subsequent SoCs. This is
necessary because the existing event handling mechanism is incompatible
with the new hardware design.
Disabling the 3-strike event registration prevents the 3-strike count
from increasing, which addresses bug b:314883362. This issue can potentially lead to system instability.
BUG=b:314883362
TEST=disabling the 3-strike event on a Google Screebo system with QS silicon.
Change-Id: I15bd5a93da34d7f2a127c21c4cd8b5952926bccf
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79472
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The original DA7219 is designed to use a 500ohm mic detection
threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be
detected. Lower the threshold to 200ohm to match the new default
value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets.
BUG=b:314062160,b:308207450
Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Commit ea2c1d3 "cpu/x86/smm: Remove heap" removed the ability to use
heap in SMM, but the ENV_HAS_HEAP_SECTION macro was not updated
appropriately.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5ae4a63a7bd1b27ae3e9c757aa8557f329aad0f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I176182180f508a180726fca60064b16fad80e9d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Call fill_fadt_extended_pm_io directly from the SoC's acpi_fill_fadt
functions instead of calling fill_fadt_extended_pm_regs that only calls
fill_fadt_extended_pm_io.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I442bc2801cf74c1d836d3b0d88f281bceb5122b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79529
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie21bf8d436de19c23ae2176bf8d061564cd5b9cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I0a6eaf43ab6da4bb4a0cc0bbefb5b75c206348f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add the code to configure the FCH IRQ mapping registers and provide the
IRQ name strings for each FCH IRQ mapping configuration register.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I282ae35ebc4d7754121ce4544b782e3cbe7e2256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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FSP default value for LpDdrDqDqsReTraining is 1. For boards
that didn't set LpDdrDqDqsReTraining to any value, 0 was being
assigned and it caused black screen issue.
BUG=b:302465393,b:315739133
TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1
Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Previously ramdetect.c was compiled only for VENDOR_EMULATION.
Hence add Kconfig option PROBE_RAM which allows board outside
the scope of VENDOR_EMULATION to select and utilize probe_ram
function to runtime detect usable RAM in emulation environment.
PROBE_RAM is default selected if VENDOR_EMULATION is set so
that existing boards under VENDOR_EMULATION scope are not
affected.
Other boards can explicitly select PROBE_RAM to use probe_ram.
TEST=Build mb/arm/rdn2 with PROBE_RAM selected & make sure
there is no any error.
Also checked qemu-aarch64 build to make sure build is success.
Change-Id: Id909ddaee6958cfa8a6c263a11f9a90d94710aa7
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab640551d6dd246884802ced948ff8c359d922a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79470
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change GPP_B14 from UP_20K to NONE for compatible
with DVT1 and DVT2 board
BUG=b:272447747
TEST=enable usb OC2 function to ensure USBA work normal
Change-Id: Ib7720980335660f423b3a74199ceedc113ec70df
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79431
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update DTT settings based on the suggestion of the thermal.
BUG=b:313833488
TEST=emerge-nissa coreboot
Change-Id: I2296990062cadc05202e3d1ab90af04234bda885
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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1. Ref to SCH, LTE use USB3 Port3, enable it.
2. Explicitly define the use of USB3 Port1 & USB3 Port2.
BUG=b:315061146
TEST=can pass PCIe Hardware Compliance Test
Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change code style to be compatible with Nissa's format:
register "option" = "{
[0] = value /* comment */
...
}"
to
register "option[0]" = "value" /* comment */
BUG=none
TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar
Change-Id: I60659bd44813173f9b984216473a0919c5f331b8
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iadc37f2724a9be43cad1f1934403ebabd5cca245
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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- DSDT
- MADT
- SSDT CPUs
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c86694ae83e9e6aa06a50a8a35bf2b24bc8ab65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76530
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the opensil_fill_fadt_io_ports function to fill in the ACPI I/O
ports in FADT that openSIL configured.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I154a162cc8e048cadab693c0755e96c71a62983c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76529
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the existing FSP 4301.01 headers for Raptor Lake out of
subdirectory called 43101.01 to follow standard process.
Change-Id: I710f373acd37e9e0f8b50084a1a7e9fbda816e8c
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add the missing parts in soc.asl. Compared to earlier versions of this,
the includes related to S0i3 and DPTC were removed.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I89ecf469e44ca2a3b35c9fcf57c008ff29e7b9bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79468
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the 4 root bridge devices using the ROOT_BRIDGE macro.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If405a90981e5c1fea51935c520800a245473317e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79467
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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acpi/dsdt_top.asl provides some common functionality and needs to be
included at the beginning of the DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7b5ddce110b35ed65c6df6cc42995abe93a3ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79466
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Instead of including globalnvs.asl in the mainboard's dsdt.asl, include
it in Genoa's soc.asl. This aligns Genoa with Cezanne and newer and also
moves more SoC-common code to the SoC folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0e3299a95e007188a4d9de824cfff8d25a778be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79465
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Apart from the IOAPIC in the FCH which is handled by amd_lpc_ops,
there's one IOAPIC per PCI root which also needs to be initialized.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I38af5a194062e714827852e95f4e29b45311e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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There's no need for the two additional spaces between the tabs and the
'='.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6824e8c7ee870fc44c5efd70cc05677e9948a9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79464
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I00a567f417b1e22167923fc3193583138718dbbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79463
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PIRQ_SCI is already defined as 0x10 and this also brings the definitions
more in line with Phoenix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2ab954b379d2edd0167d7fb229557600cbc4e48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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To quote its repo[0]: Wuffs is a memory-safe programming language (and
a standard library written in that language) for Wrangling Untrusted
File Formats Safely. Wrangling includes parsing, decoding and encoding.
It compiles its library, written in its own language, to a C/C++ source
file that can then be used independently without needing support for
the language. That library is now imported to src/vendorcode/wuffs/.
This change modifies our linters to ignore that directory because
it's supposed to contain the wuffs compiler's result verbatim.
Nigel Tao provided an initial wrapper around wuffs' jpeg decoder
that implements our JPEG API. I further changed it a bit regarding
data placement, dropped stuff from our API that wasn't ever used,
or isn't used anymore, and generally made it fit coreboot a bit
better. Features are Nigel's, bugs are mine.
This commit also adapts our jpeg fuzz test to work with the modified
API. After limiting it to deal only with approximately screen sized
inputs, it fuzzed for 25 hours CPU time without a single hang or
crash. This is a notable improvement over running the test with our
old decoder which crashes within a minute.
Finally, I tried the new parser with a pretty-much-random JPEG file
I got from the internet, and it just showed it (once the resolution
matched), which is also a notable improvement over the old decoder
which is very particular about the subset of JPEG it supports.
In terms of code size, a QEmu build's ramstage increases
from 128060 bytes decompressed (64121 bytes after LZMA)
to 172304 bytes decompressed (82734 bytes after LZMA).
[0] https://github.com/google/wuffs
Change-Id: If8fa7da69da1ad412f27c2c5e882393c7739bc82
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Based-on-work-by: Nigel Tao <nigeltao@golang.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78271
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure UART baud rate, Line Control register as 8n1 with FIFO
enable and enable UART TX and RX.
Change-Id: I090344a20430dc370a0b93ff7fbbae54111fae24
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I926ec4c1c00339209ef656995031026935e52558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
MT62F1G32D2DS-023 WT:B 2 (0010)
BUG=b:311450057,b:315913909
BRANCH=None
TEST=Run part_id_gen tool without any errors
Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d5efa948e8bd993ca4b5af80f664db687b8a766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Early versions of CB:76519 had more devices enabled in the chipset
devicetree which shouldn't necessarily be enabled in the chipset
devicetree. Enable most of those in the Onyx mainboard's devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieeb96755a007a5ca70e4c31df09325835bb8ef47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Disable the IOMMU PCI devices in the chipset devicetree. In order for
the IOMMU devices on the Onyx mainboard still be enabled, enable them in
the mainboard devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the xPRF call to report holes in memory and report those regions as
reserved.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5605499e39931e1a1592318310112666f8a0f144
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Use the xPRF call to report holes in memory to report those regions as
reserved.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If89b08a31a9b9f8e7d2959d1bc45e91763fe565b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78922
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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