diff options
| author | Eran Mitrani <mitrani@google.com> | 2023-12-12 16:16:13 -0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-12-19 04:19:21 +0000 |
| commit | 83e9f048024ab3a527d886d4591b29513c628f79 (patch) | |
| tree | eda2924954be7d9884ac6f88a6165a60b11b6fae /src | |
| parent | 7bcf4ae4d26d5c904c95d896dedeeb23d44d979f (diff) | |
mb/google/hatch/var/jinlon: Increase reset deassert delay to 4 ms
With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.
TEST=tested on google/jinlon device and observed the issue is resolved.
BUG=b:260253945
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/jinlon/ramstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/jinlon/ramstage.c b/src/mainboard/google/hatch/variants/jinlon/ramstage.c index 5e128644b2..240bcaeb93 100644 --- a/src/mainboard/google/hatch/variants/jinlon/ramstage.c +++ b/src/mainboard/google/hatch/variants/jinlon/ramstage.c @@ -13,6 +13,6 @@ void variant_ramstage_init(void) * a minimum of 400us on Kohaku. */ gpio_output(GPP_C11, 1); - mdelay(1); + mdelay(4); gpio_output(GPP_A12, 1); } |