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This patch adds descriptions for TCSS port, including over-current
(OC) pin configuration, to the device tree.
It also includes entries that will generate ACPI code at runtime
with port definitions, locations, and type information.
Additionally, implement the TCSS PMC MUX programming.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds descriptions for USB2/3 ports, including over-current
(OC) pin configuration, to the device tree.
It also includes entries that will generate ACPI code at runtime with
port definitions, locations, and type information.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Generate 3 Samsung RAM IDs
K3KL9L90CM-MGCT Samsung
K3KL6L60GM-MGCT Samsung
K3KL8L80CM-MGCT Samsung
BUG=b:331539447,b:333145301,b:333220620
TEST=Run part_id_gen tool without any errors
Change-Id: I4ba0fb409015c24446b2ae8e224fbce3910715e3
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83501
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6155ec45408dca83573c86e6db1ead5a82a0d77a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds minimal device entries and chip configs for Trulo
overridetree.cb to boot.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83546
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves the EC configuration from the orisa variant to the
trulo baseboard, enabling reuse by other variants in the future.
BUG=b:351976770
TEST=Builds successfully for google/orisa.
Change-Id: Ib5611cf67a41950c1c4ce936a5d2bea7fdca5c68
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83544
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves the GPIO configuration from the orisa variant to the
trulo baseboard, enabling reuse by other variants in the future.
BUG=b:351976770
TEST=Builds successfully for google/orisa.
Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83545
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables SKIP_RAM_ID_STRAPS for the TRULO board variant as
this board design won't stuff MEM strap GPIO hence, sets the static
SPD ID to 0 for the MT62F512M32D2DR-031 DRAM part.
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: I1acb4680a143611c55f4fa6e032fde38c62af054
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds key DRAM configuration parameters as below:
- Rcomp
- DQ byte map
- DQS CPU<>DRAM map
- ECT
- CCC Mapping
- SPD Index
Source: Trulo Schematics Rev0.5 (dated June'24)
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: Ie7abc393a71becf26d53ae9e4fc56f66c7117051
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This patch adds Micron Technology LPDDR5 DRAM
(part: MT62F512M32D2DR-031) for Trulo.
Make use of spd_tools to generate SPD file after following the below
steps:
1. make -C util/spd_tools
2. ./util/spd_tools/bin/part_id_gen ADL lp5
src/mainboard/google/brya/variants/trulo/memory
src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
Output files are:
1. dram_id.generated.txt
2. Makefile.mk
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: Id35f6b57b716375abb66db187413f0f82361d962
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83539
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GPIOs according to schematics revision 20240712.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83449
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Vendor DRAM Part Name Type
SAMSUNG K4U6E3S4AB-MGCL LP4X
SAMSUNG K4UBE3D4AB-MGCL LP4X
MICRON MT53E1G32D2NP-046 WT:B LP4X
BUG=b:351968527
TEST=Run part_id_gen tool without any errors
Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83427
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the awasuki variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:351968527
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_AWASUKI
Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enables the driver for ITE SIOs supporting the GPIO register layout
(confirmed with datasheets for the modified ITE SIO Kconfigs, SIOs
with unavailable datasheets are unmodified).
Other ITE SIOs may select it with SUPERIO_ITE_COMMON_GPIO_PRE_RAM
and must then provide the number of GPIO sets specific to a chip
via SUPERIO_ITE_COMMON_NUM_GPIO_SETS.
Change-Id: I0868ff3e9022b135c21f4c1a6746d6440b8f0798
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add a generic driver to configure GPIOs and LEDs on common ITE
SuperIOs. The driver supports most ITE SuperIOs, except Embedded
Controllers. The driver allows configuring every GPIO property
with pin granularity.
Verified against datasheets of all ITE SIOs currently supported by
coreboot, except IT8721F (assumed to be the same as IT8720F),
IT8623E and IT8629E.
Change-Id: If610d2809b56c63444c3406c26fad412c94136a5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83355
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I2e15f26436626fbde7a93b47bea9f2601a302ffe
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83330
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add socket types for LGA1700, LGA3647_1, LGA4189, LGA4677.
Select the socket type for different boards.
For the socket types which are not defined in SMBIOS type4,
CPU_INTEL_SOCKET_OTHER could be used.
Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83329
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch adds new CNVi PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the CNVi driver's `pci_device_ids` list to
include these new IDs.
Finally, dropped unused BT PCI IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I7d80403b87537aea41ff48ff6d274180577f1ac6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83520
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes the PCI device IDs for Intel LNL and PTL UFS
devices from `pci_ids.h` as they appear to be unused in the codebase.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ic795dd2e83c361a2aa04267d4663cf6bb9a755e2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83519
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds new XDCI PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the XDCI driver's `pci_device_ids` list to
include these new IDs.
Finally, dropped unused TCSS XDCI PCI IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I51196401904e2402ac7669fa852a541bb7c2d453
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83518
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch adds new CSE0 PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the CSE0 driver's `pci_device_ids` list to
include these new IDs.
Finally, dropped unused CSE1-3 PCI IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I5656aeb8c5439c8361aeb3a3d759df1216d84f8b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83517
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds new Audio (HDA/DSP) PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the Audio driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I3c9e420a6ae19d00fb5510c99d4c219dc43ad3c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83516
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds new SRAM PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the SRAM driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ib6d62dad59965258dab453533dface9c359de586
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83515
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch adds new P2SBx PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the P2SBx driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ie1c36bc1c014bb1e219afe0cafb6c9941f253b0c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds new XHCI/TCSS XHCI PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the XHCI driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I5ae8f493374087a5e684e0a04486cd64cea6f335
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83513
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds new SMBUS PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the SMBUS driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I4b8b59cf4e005f0e17a25d0fbe761404dab432b3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83512
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch adds new Fast-SPI and GSPIx PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the SPI driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I5c7c0be6f219c93d4520494857d31ce1cf939f36
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83511
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch adds new UARTx PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the UART driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I384a753f08ae5a752cef6009d07104e8ff4b4a6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch adds new I2Cx PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the I2C driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I79ba0b563146d658521cdd40aabb3ee882f4d187
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83509
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds new PMC PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the PMC driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Iae468fdace2d9cfd532957e4f3c55b89b96a52a0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds new PCIe Root Port PCI device IDs for Intel PTL-U
and PTL-H.
Additionally, updates the PCIe driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I5913c6ac0a4766c14f23954be1e885d45f69d36a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83507
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch adds new eSPI/LPC PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the LPC driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ie9f0ea9536e2f73c2258e9e12b510d21212248ea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds new ISH PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the ISH driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I280cfdb50e8d453e957cb4bccff3a7ee2fb3bd10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83505
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds new DID2 PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the graphics driver's `pci_device_ids` list to
include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Iab499070c87e020e36901b4ea453a1893bd16ea0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83491
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds new DID0 PCI device IDs for Intel PTL-U and PTL-H.
Additionally, updates the System Agent driver's `systemagent_ids` list
to include these new IDs.
Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ie4d77eb489e16d18b996fdda3216e1275083d7e7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83490
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Most x86 platforms use CMOS as the vboot nvdata (VBNV) backend storage.
On some platforms such as AMD, certain CMOS registers must be configured
before accessing the CMOS RAM which contains VBNV. More precisely,
according to AMD's spec [1], the bit 4 of Register A of CMOS is bank
selection. Since VBNV is accessed via bank 0 (see the MC146818 driver),
the bit must be cleared before the VBNV can be successfully written to
CMOS. Saving VBNV to CMOS may fail in verstage, if CMOS has lost power.
In that case, all the CMOS registers would contain garbage data.
Therefore, for AMD platforms the bit must be cleared in verstage, prior
to the first save_vbnv_cmos() call.
Introduce vbnv_platform_init_cmos(), which is no-op by default, and can
be defined per platform. The function will be called from vbnv_init() if
VBOOT_VBNV_CMOS.
[1] 48751_16h_bkdg.pdf
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: Ic899a827bd6bb8ab1473f8c6c03b9fde96ea6823
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83494
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
The cpu_cluster device is defined in the chipset devicetree. So drop it
from the mainboards.
Change-Id: Ib84e7804c03f1c0779ab7053a09e397a267a3844
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83523
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I30a98ae4989edc97d56d2b538930b3c67565d9dc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
|
Set "option WIFI_SAR_ID_1 1" for WIFI_SAR_ID field in fw_config.
BUG=b:347108861
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I179dad5eeabc1d84aa0a2de5359be5848a2ecc39
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83478
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace integer literals with macros for CMOS addresses for readability.
Change-Id: I454662c90fabb41af864728febdefa57f5ff2cb2
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This patch removes `p2sb.c` from the bootblock build for the
Meteor Lake platform.
BUG=none
TEST=Builds successfully for google/rex.
Change-Id: Ib2beeee68bb20568888d4b555c2fa82e0bf0fd3c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
This patch updates Tiger Lake code to use the common eSPI header file
(`intelpch/espi.h`) instead of the SoC-specific one.
BUG=none
TEST=Builds successfully for google/volteer.
Change-Id: I01eca0ab132b1788c4633d0e214d4dfde25f5b98
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83488
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch updates Meteor Lake code to use the common eSPI header
file(`intelpch/espi.h`) instead of the SoC-specific one.
BUG=none
TEST=Builds successfully for google/rex.
Change-Id: Ibb37413bb6c925650f55b0dcf70e7483bf257888
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch updates Jasper Lake code to use the common eSPI header
file (`intelpch/espi.h`) instead of the SoC-specific one.
BUG=none
TEST=Builds successfully for google/dedede.
Change-Id: I93dcd26588111d848be1580220945687890ef3b8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch updates Elkhart Lake code to use the common eSPI header
file(`intelpch/espi.h`) instead of the SoC-specific one.
BUG=none
TEST=Builds successfully for Intel Elkhartlake platform.
Change-Id: Iaef308ad1c8ecfb11448e75f39285a2170bbc49c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83485
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch updates Alder Lake code to use the common eSPI header file
(`intelpch/espi.h`) instead of the SoC-specific one.
BUG=none
TEST=Builds successfully for google/redrix.
Change-Id: Ib4452547325042de48ee4fca3d3910a031b56b64
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83484
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch moves the SoC-specific `eSPI.h` file into the IA common
code to promote code reuse and reduce duplication across different
SoC generations.
TEST=Builds successfully for google/rex.
Change-Id: Icb09421eec45c1ef8ab50252543b000078f18b21
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Replace the SoC-specific `report_cache_info()` function with the
common `car_report_cache_info()` API from `car_lib`. This promotes code
reuse and reduces SoC-specific implementation for cache reporting.
BUG=none
TEST=Builds and boots successfully on google/rex platform.
Change-Id: Id5ffcab54232294ffa101f975d0ec51ac63f1910
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Replace the SoC-specific `report_cache_info()` function with the
common `car_report_cache_info()` API from `car_lib`. This promotes code
reuse and reduces SoC-specific implementation for cache reporting.
BUG=none
TEST=Builds and boots successfully on google/marasov platform.
Change-Id: I18be2c33dbe5186643af52823eb2fb185a296909
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83481
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds `car_lib.c` to the IA common code to consolidate
SoC-agnostic CAR APIs. Initially, it includes `car_report_cache_info()`
to provide a unified way to read cache information, reducing the need
for SoC-specific implementations.
TEST=Builds successfully for google/rex.
Change-Id: I2ff84b27736057d19d4ec68c9afcb9b22e778f55
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This change removes the condition that
SOC_INTEL_METEORLAKE_SIGN_OF_LIFE is only enabled for x86_32 arch.
Now, it is safe to enable eSOL for x86_64 platform as well.
BUG=b:346682156
TEST=Able to see eSOL on google/rex64.
Change-Id: I825c988800ec303a8f37141f6487115b1c7c5d3a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83498
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds the necessary Kconfig options to enable support for
the TRULO board, including selecting the appropriate baseboard,
HDA verb table, and TCSS configuration.
Additionally, corrected the TPM_TIS_ACPI_INTERRUPT from `13` to `17`
for Trulo as applicable.
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: I5c1cbd56cf2734058aced35868ae42c1c160f62e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83500
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change adds hda_verb.c to the ramstage build, but only when the
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB config option is enabled.
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: I9b17126ff1493b5714d6ae715ad2863bdff4ed46
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83499
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch sets a default value of 13 (GPE0_DW0_13/GPP_A13_IRQ) for
the `TPM_TIS_ACPI_INTERRUPT` configuration option across most Google
Brya variants. The HADES board uses interrupt 20 (GPE0_DW0_20/
GPP_A20_IRQ), and the ORISA board uses interrupt 17 (GPE0_DW0_17/
GPP_A17_IRQ).
This refactoring simplifies future additions of board-specific TPM
interrupt configurations, improving maintainability.
BUG=none
TEST=The timeless builds with this patch for both Nissa and Brya
devices produce the same binaries.
Change-Id: I9d913bf3da6957ab5c700dd746bc4b5350427d73
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83493
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fixes a pmc_mux port mapping error introduced in coreboot
commit 4fa8354
Mithrax and felwinter do not have sequential mux_conn[X] to connY
mappings which led to the kernel subsystem linking between Type C
connectors and USB muxes to be incorrect. The previous patch
attempted to fix this by changing the custom_pld layout. However
this broke USB usage except for charging.
This patch reverts the custom_pld layout and instead changes the pmc
hidden and tcss_xhci port mappings to match the hardware layout.
BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
ectool commands below are only for felwinter as a workaround for
devices without a firmware patch to connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch)
echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch)
echo host > /sys/class/usb_role/CONY-role-switch/role (should fail
as no cable attached)
BRANCH=firmware-brya-14505.B
Change-Id: Iebd259842d3affa259069cd776b46759c1c60712
Signed-off-by: Emilie Roberts <hadrosaur@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83472
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new eventLog type of ELOG_TYPE_FW_LATE_SOL to support logging
when we show late (from payload) Signs Of Life (SOL) to the user.
BUG=b:305898363
TEST=Event shows in eventlog tool after CSE sync:
```
Late Sign of Life | CSE Sync Late SOL Screen Shown
```
Change-Id: Ibbe9f37a791e5c2a0c6e982942cf3043a2bd4b45
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
|
|
The 'Radio Frequency Interference Mitigation' DSM function 11
provides the desired status of the RFI mitigation.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 8.3 specification.
BUG=b:352768410
TEST=ACPI DSM Function 11 reflects the value of the SAR binary
Change-Id: I02808b0ce6a0a380845612e774e326c698ad1adc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The 'Energy Detection Threshold' DSM function 10 provides the desired
status of the EDT optimizations.
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 8.3 specification.
BUG=b:352788465
TEST=ACPI DSM Function 10 reflects the value of the SAR binary
Change-Id: I2e2e9d4f5420020bd7540cb36fa8aebfedf62285
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
|
|
The UEFI reference firmware uses AMDI0030 instead of AMD0030 as HID for
the GPIO controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a6fa1acdca0ee5b6e1358b6279b7c501d3dfd16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The UEFI reference firmware uses AMDI0030 instead of AMD0030 as HID for
the GPIO controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8dd48d7d9cf3f6d75853bb825e5ddc32bba430b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The table "IOMUX Functional Table" in PPR #57254 rev. 1.60 was used as a
reference. This should fix the ESPI_ALERT_D1 IOMUX setting for the
boards using the Glinda SoC which previously didn't match the hardware.
Compared to Phoenix, Glinda has two more chip select outputs for the
SPI2 controller and an additional ZST_STUTTER_RAIL IOMUX function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9adfbe0c7aee90d6fe990f239d82a1d013e7f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83437
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Also set the vendor default TCC offset temperature
Change-Id: Ia187b67ae28fbcda7d5d0e35ec64a3b21d97a21b
Signed-off-by: Anastasios Koutian <akoutian2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Tested on ThinkPad T420 with the i7-3940XM.
Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad
Signed-off-by: Anastasios Koutian <akoutian2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Setting the clamp bit allows the CPU to operate below the highest
non-turbo frequency in order to obey the power limit.
Tested on ThinkPad T420 with the i7-3940XM.
Change-Id: Id0c0aedc29aca121d0fd1d8f8826089e13a026be
Signed-off-by: Anastasios Koutian <akoutian2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Ifc882c2ac9d4e9ce2ed4305bdd6859a5d1e1b09c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
In order to clean up a bit, drop devices which are equivalent to the
ones from chipset devicetree.
Change-Id: Ief199db47fc529c510709ac37be6014b63244e84
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
The cpu_cluster device is defined in the chipset devicetree. So drop it
from the mainboards.
Change-Id: I65bfeaf0b8771c123c0615531c2cc608b222949b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83440
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Several brya variants were missing VBT files, add and select them in
Kconfig.
Also select in Kconfig for VELL, which already had a VBT but was not
using/selecting it.
TEST=build/boot google/brya (marasov), verify display init functional
/ payload screen shown.
Change-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83434
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Eliminates the use of a magic number, and the resulting DID entry in
the _DOD method is the same. The first entry was already changed in
commit 1810a1841528 ("mb/google/*: Replace use of gfx/generic addr
field with display type"), this one was missed.
TEST=build/boot google/jinlon w/o privacy screen, dump SSDT and verify
DID entry is unchanged but _ADR is now correct (since the DID flags are
not part of the address field).
Change-Id: Ief22928ea831d4cb5b483406ac388218a97ad98b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Iebe5f8729d463767f5a1b52c375d11bb9d413144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
|
Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: I4769f255ce5652a9969ad6535c997ec1ad0be8d2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
|
Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Ic33bf07041a8c966dce66109c577621513147609
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78838
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Ide536c74683416b34b0984fe1bddb250e72b045b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Id3605e8e05d9d97a73af966459692276265df8bc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78836
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: I2b0e19581e0f0111a56bc57185acfcdd70588141
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78835
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: I290fcfdd7b2cff61c4f6cd153133c5205c6fd6d1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Issue: System hang occurred due to unhandled SPI synchronous SMI,
triggered by LOCK_ENABLE bit and WPD assertion.
Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration
to allow the system to handle and clear SPI synchronous SMI.
BUG=b:350623902
TEST=reboot test on 40 google/xol by ODM, all passed w/o
hang.
Change-Id: I4c14b1e3d537e46e671e950c91c9d0042fe26836
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83432
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Edward Doan <edoan@chromium.org>
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Fan control is assign to EC handle now. Remove relate setting on coreboot.
BUG=b:351917517
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Iff0776ce3db6f27e250162357abb3c7e9b1a0dc3
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83380
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
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This patch extends the crashlog IP support beyond 32-bit mode to
support Intel future generation SoCs, which may require crashlog
support for 64-bit architectures. uintptr_t data type is used for
Address pointers and void* for dereferencing
BUG=b:346676856
TEST=Successfully built Meteor Lake (rex) and tested for google/rex0
and google/rex64 images.
Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83106
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds FW_CONFIG to accommodate different Lotso BoM
components across various SKUs.
1. Fingerprint sensor - FP Present/Absent
BUG=b:350360162
BRANCH=None
TEST=Boot image on SKU2 and check FP working.
Change-Id: I1ee5fcd1c29099bdbee741ef76c00cf45fcc1189
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83388
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
This commit also updates the USB2 port 10 description and set its type
to the more appropriate `UPC_TYPE_INTERNAL' type.
BUG=b:348345301
TEST=BRDS method is added to the CNVW device and returns the data
supplied by the SAR binary blob
Change-Id: I66c9b75d2aaa1b221313b037defcd2c579fd6b61
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
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1. Add STORAGE_UNKNOWN fw_config to enable all storage devices,
this is used for the first boot in factory.
2. Add fw_config probe to enable/disable devices in devicetree
instead of variant.c, it can avoid suspend(s0ix) fail issue.
BUG=b:328580882
TEST=On riven eMMC and UFS SKUs, boot to OS and run
`suspend_stress_test -c 10` pass.
Change-Id: I518f1a5955fb88f304663112f1e3d4c744bde183
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83405
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bujia does not support Thunderbolt anymore,
therefore disable related TBT setting.
The bujia fit image CL, cf. chrome-internal:7468938.
BUG=b:349923139
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot.
Change-Id: I4301a1f744aa9d4de9f0eba4147c49a4bb3ed922
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83402
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CMOS entry for CSE partition firmware was incorrectly labeled as
`ramtop` and `partition firmware` in the error messages.
This patch corrects the messages to accurately refer to `CSE partition
firmware`.
Additionally, the alignment and size check comments are updated to
reflect this change.
Change-Id: Ib3a7fb88f52c4d0c47d828bcd1c4649e62d19654
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This patch ensures CSE boot partition (RO/RW) version information only
log when the status is "success". If the status is not successful,
log an error message indicating the failure and status code.
This change avoids logging potentially incorrect version information
when the boot partition is not valid.
BUG=b:305898363
TEST=Builds successfully for google/rex variants.
Change-Id: I1932302b145326a1131d64b04af1cbfd6d050b7b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch refactors CSE config options, moving the selection of:
* `SOC_INTEL_CSE_LITE_SKU`
* `SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2`
* `SOC_INTEL_CSE_SEND_EOP_ASYNC`
from the generic `BOARD_GOOGLE_REX_COMMON` to individual board models.
This enables finer-grained control over CSE features and sync behavior
on different Rex and variants platforms.
Specifically:
* `google/rex0`: Selects `SOC_INTEL_CSE_LITE_SKU` for CSE sync within
coreboot.
* `google/rex64`: Selects `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` and
`SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD` to defer CSE sync
to the payload.
BUG=b:305898363
TEST=Builds successfully for google/rex variants.
Change-Id: Ib5957496b1e1dad8d135b3e10541cb83dd339539
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83397
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional
on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being
enabled.
This ensures that CSE Lite PSR is only active when both ChromeOS is the
target platform and CSE sync is performed inside coreboot.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and
`ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include
`SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`.
This allows these features to be enabled even when CSE sync is performed
in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU`
config is enabled).
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch updates FSP-M UPDs conditionally to ensure CSE firmware
updates and VGA initialization control only when
`SOC_INTEL_CSE_LITE_SKU` config is enabled.
This ensures eSOL rendering is tied to CSE sync performed in coreboot,
preventing unnecessary setup when sync is deferred to the payload.
Deferring CSE sync to the payload results in the depthcharge screen.
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch refactors the handling of CSE CBMEM IDs to enable platforms
to choose whether to perform CSE sync operations within coreboot or
defer it to the payload. This separation improves code organization,
ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks.
Now, platforms can select:
* `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot
* `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync
This change ensures mutually exclusive options, avoiding unnecessary
SPI flash size increases.
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboard is identified as 0Y2MRG.
The version tested is with Nvidia dGPU (gfx 560ti).
The flash is a 4MiB Winbond W25Q32BVSIG.
It can be flashed internally with flashrom.
Add a strap on the service mode pin of the mainboard for internal flash.
Tested working:
- SeaBIOS
- All USB ports
- SATA
- dGPU
- Ethernet
- Environment control
- GPIOs
- S3 Sleep mode
- WakeOnLan
Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059
Signed-off-by: Ronald Claveau <sousmangoosta@aliel.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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A previous commit splits out Cirrus display support from Bochs display
support, with both using the pre-existing Bochs config options for the
requested display resolution. Rename these config names to clarify they
are not only specific to the Bochs display driver.
Change-Id: Ie0a5e75731231bb768d7728867196c9ab5c53a00
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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QEMU's Cirrus display device is supported along with the Bochs driver
since commit 7905f9254ebc ("qemu: cirrus native video init"). It is no
longer the default since QEMU 2.2. The code supporting it can work
independently of the Bochs display driver and depends more heavily on
port I/O and VGA support code, so split it from that code to make it
easier to support the Bochs driver in other architectures.
Change-Id: Ic9492b501ed4fdcbda6886db60b1e5348715e667
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Define the PCI I/O base address necessary to use port I/O functions on
the qemu-aarch64 mainboard, so that we can get the VGA display devices
working. The config value is from hw/arm/virt.c [1]:
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
[1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.3/hw/arm/virt.c#L164
Change-Id: I85439ba68740d64f789983b37d9c95f849ce4f72
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82059
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allows to use this driver for the SMBus console without sending an index
byte for every sent char (i.e. !CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER).
Tested with WiP VIA CX700-M2 port and FT4222H as receiver.
Change-Id: Ic368ef379039b104064c9a91474b188646388dd2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.
This fixes the issue of RAM training running on every boot on
non-vboot builds for Myst boards.
TEST=untested, but same change as made for Mendocino
Change-Id: Ib4a78a39badf0a067e22eebe5869e5ea51723f35
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The APOB NV size/base are embedded into the amdfw binary and read by
the PSP. These need to be synchronized with the FMAP region used by
coreboot to store the APOB data. soc_update_apob_cache() will only
use RECOVERY_MRC_CACHE if supported and if vboot is enabled, so the
NV base passed to the PSP needs to reflect that as well.
This fixes the issue of RAM training running on every boot on
non-vboot builds for Skyrim boards.
TEST=build/boot Skyrim (Frostflow), verify RAM training only
run on first boot after flashing.
Change-Id: I9be1699d675331b46ee9c42570700c2b72588025
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83400
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Not every I2C target requires a register address. Not sending one
for every console char saves us a lot of overhead.
Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82762
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie44fdac6904a4467e408882bb8a5e08e6ff73f32
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82761
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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