soc/amd/glinda/include/gpio: update to match hardware

The table "IOMUX Functional Table" in PPR #57254 rev. 1.60 was used as a
reference. This should fix the ESPI_ALERT_D1 IOMUX setting for the
boards using the Glinda SoC which previously didn't match the hardware.
Compared to Phoenix, Glinda has two more chip select outputs for the
SPI2 controller and an additional ZST_STUTTER_RAIL IOMUX function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9adfbe0c7aee90d6fe990f239d82a1d013e7f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83437
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

2 files changed, 15 insertions, 40 deletions

diff --git a/src/soc/amd/glinda/gpio.c b/src/soc/amd/glinda/gpio.c
index 1f7f00e8eb..271e749b92 100644
--- a/src/soc/amd/glinda/gpio.c
+++ b/src/soc/amd/glinda/gpio.c
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Glinda */
-
 #include <amdblocks/gpio.h>
 #include <gpio.h>
 #include <types.h>
diff --git a/src/soc/amd/glinda/include/soc/gpio.h b/src/soc/amd/glinda/include/soc/gpio.h
index a4d945ce97..42d8439f30 100644
--- a/src/soc/amd/glinda/include/soc/gpio.h
+++ b/src/soc/amd/glinda/include/soc/gpio.h
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* TODO: Update for Glinda */
-
 #ifndef AMD_GLINDA_GPIO_H
 #define AMD_GLINDA_GPIO_H
 
@@ -33,8 +31,6 @@
 #define GPIO_10				10
 #define GPIO_11				11
 #define GPIO_12				12
-#define GPIO_13				13
-#define GPIO_14				14
 #define GPIO_16				16
 #define GPIO_17				17
 #define GPIO_18				18
@@ -118,30 +114,21 @@
 #define GPIO_3_IOMUX_GPIOxx 0
 #define GPIO_4_IOMUX_GPIOxx 0
 #define GPIO_5_IOMUX_GPIOxx 0
-#define GPIO_5_IOMUX_DEVSLP0 1
 #define GPIO_6_IOMUX_GPIOxx 0
-#define GPIO_6_IOMUX_DEVSLP1 1
-#define GPIO_6_IOMUX_MDIO0_SCL 2
 #define GPIO_7_IOMUX_GPIOxx 0
-#define GPIO_7_IOMUX_SVI_RST_L 1
+#define GPIO_7_IOMUX_ZST_STUTTER_RAIL 1
 #define GPIO_8_IOMUX_GPIOxx 0
 #define GPIO_8_IOMUX_TMU_CLK_OUT0 1
 #define GPIO_8_IOMUX_TMU_CLK_OUT1 2
 #define GPIO_9_IOMUX_GPIOxx 0
-/* GPIO 9 IOMUX == 1 is also GPIOxx */
-#define GPIO_9_IOMUX_MDIO2_SCL 2
 #define GPIO_10_IOMUX_GPIOxx 0
 #define GPIO_10_IOMUX_S0A3_GPIO 1
+/* GPIO 10 IOMUX == 2 is also GPIOxx */
+#define GPIO_10_IOMUX_DF_VRCONTEXT_0 3
 #define GPIO_11_IOMUX_GPIOxx 0
 #define GPIO_11_IOMUX_BLINK 1
-#define GPIO_11_IOMUX_MDIO3_SDA 2
 #define GPIO_12_IOMUX_LLB_L 0
 #define GPIO_12_IOMUX_GPIOxx 1
-#define GPIO_12_IOMUX_LPC_PME_L 2
-#define GPIO_13_IOMUX_USB_SBTX_0 0
-#define GPIO_13_IOMUX_GPIOxx 1
-#define GPIO_14_IOMUX_USB_SBTX_1 0
-#define GPIO_14_IOMUX_GPIOxx 1
 #define GPIO_16_IOMUX_USB_OC0_L 0
 #define GPIO_16_IOMUX_GPIOxx 1
 #define GPIO_17_IOMUX_USB_OC1_L 0
@@ -159,13 +146,12 @@
 #define GPIO_21_IOMUX_ESPI_RESET_L 0
 #define GPIO_21_IOMUX_KBRST_L 1
 #define GPIO_21_IOMUX_GPIOxx 2
-#define GPIO_22_IOMUX_LDRQ0_L 0
-#define GPIO_22_IOMUX_ESPI_ALERT_D1 1
-#define GPIO_22_IOMUX_GPIOxx 2
+#define GPIO_22_IOMUX_ESPI_ALERT_D1 0
+#define GPIO_22_IOMUX_GPIOxx 1
+/* GPIO 22 IOMUX == 2 is also GPIOxx */
 #define GPIO_22_IOMUX_SD0_CMD 3
 #define GPIO_23_IOMUX_AC_PRES 0
 #define GPIO_23_IOMUX_GPIOxx 1
-#define GPIO_23_IOMUX_MDIO2_SDA 2
 #define GPIO_24_IOMUX_USB_OC3_L 0
 #define GPIO_24_IOMUX_GPIOxx 1
 #define GPIO_26_IOMUX_PCIE_RST0_L 0
@@ -179,24 +165,22 @@
 #define GPIO_30_IOMUX_GPIOxx 2
 #define GPIO_31_IOMUX_SPI_CS3_L 0
 #define GPIO_31_IOMUX_GPIOxx 1
+/* GPIO 31 IOMUX == 2 is also GPIOxx */
+#define GPIO_31_IOMUX_SPI2_CS3_L 3
 #define GPIO_32_IOMUX_GPIOxx 0
 #define GPIO_32_IOMUX_LPC_RST_L 1
-#define GPIO_32_IOMUX_MDIO3_SCL 2
 #define GPIO_38_IOMUX_CLK_REQ5_L 0
 #define GPIO_38_IOMUX_GPIOxx 1
-#define GPIO_38_IOMUX_MDIO1_SDA 2
 #define GPIO_39_IOMUX_CLK_REQ6_L 0
 #define GPIO_39_IOMUX_GPIOxx 1
-#define GPIO_39_IOMUX_MDIO1_SCL 2
 #define GPIO_40_IOMUX_GPIOxx 0
-/* GPIO 40 IOMUX == 1 is also GPIOxx */
-#define GPIO_40_IOMUX_MDIO0_SDA 2
 #define GPIO_42_IOMUX_GPIOxx 0
+#define GPIO_42_IOMUX_DF_VRCONTEXT_1 1
 #define GPIO_67_IOMUX_SPI_ROM_REQ 0
 #define GPIO_67_IOMUX_GPIOxx 1
 #define GPIO_68_IOMUX_SPI1_DAT2 0
 #define GPIO_68_IOMUX_GPIOxx 1
-#define GPIO_68_IOMUX_SERIRQ 2
+/* GPIO 68 IOMUX == 2 is also GPIOxx */
 #define GPIO_68_IOMUX_SD0_DATA3 3
 #define GPIO_69_IOMUX_SPI1_DAT3 0
 #define GPIO_69_IOMUX_GPIOxx 1
@@ -207,8 +191,7 @@
 #define GPIO_74_IOMUX_GPIOxx 1
 #define GPIO_74_IOMUX_GFX10_CAC_IPIO0 2
 #define GPIO_75_IOMUX_SPI2_CS1_L 0
-#define GPIO_75_IOMUX_LPCCLK1 1
-#define GPIO_75_IOMUX_GPIOxx 2
+#define GPIO_75_IOMUX_GPIOxx 1
 #define GPIO_76_IOMUX_SPI_ROM_GNT 0
 #define GPIO_76_IOMUX_GPIOxx 1
 #define GPIO_77_IOMUX_SPI1_CLK 0
@@ -221,7 +204,7 @@
 #define GPIO_78_IOMUX_SD0_DATA1 3
 #define GPIO_79_IOMUX_SPI1_CS3_L 0
 #define GPIO_79_IOMUX_GPIOxx 1
-#define GPIO_79_IOMUX_LPC_CLKRUN_L 2
+#define GPIO_79_IOMUX_SPI2_CS2_L 2
 #define GPIO_80_IOMUX_SPI1_DAT1 0
 #define GPIO_80_IOMUX_GPIOxx 1
 /* GPIO 80 IOMUX == 2 is also GPIOxx */
@@ -233,7 +216,6 @@
 #define GPIO_85_IOMUX_FANOUT0 0
 #define GPIO_85_IOMUX_GPIOxx 1
 #define GPIO_86_IOMUX_GPIOxx 0
-#define GPIO_86_IOMUX_LPC_SMI_L 1
 #define GPIO_89_IOMUX_GENINT1_L 0
 #define GPIO_89_IOMUX_PSP_INTR0 1
 #define GPIO_89_IOMUX_GPIOxx 2
@@ -243,9 +225,7 @@
 #define GPIO_91_IOMUX_SPKR 0
 #define GPIO_91_IOMUX_GPIOxx 1
 #define GPIO_92_IOMUX_CLK_REQ0_L 0
-#define GPIO_92_IOMUX_SATA_IS0_L 1
-#define GPIO_92_IOMUX_SATA_ZP0_L 2
-#define GPIO_92_IOMUX_GPIOxx 3
+#define GPIO_92_IOMUX_GPIOxx 1
 #define GPIO_104_IOMUX_SPI2_DAT0 0
 #define GPIO_104_IOMUX_GPIOxx 1
 #define GPIO_105_IOMUX_SPI2_DAT1 0
@@ -266,12 +246,9 @@
 #define GPIO_115_IOMUX_GPIOxx 1
 #define GPIO_116_IOMUX_CLK_REQ2_L 0
 #define GPIO_116_IOMUX_GPIOxx 1
-#define GPIO_130_IOMUX_SATA_ACT_L 0
-#define GPIO_130_IOMUX_GPIOxx 1
+#define GPIO_130_IOMUX_GPIOxx 0
 #define GPIO_131_IOMUX_CLK_REQ3_L 0
-#define GPIO_131_IOMUX_SATA_IS1_L 1
-#define GPIO_131_IOMUX_SATA_ZP1_L 2
-#define GPIO_131_IOMUX_GPIOxx 3
+#define GPIO_131_IOMUX_GPIOxx 1
 #define GPIO_132_IOMUX_CLK_REQ4_L 0
 #define GPIO_132_IOMUX_OSCIN 1
 #define GPIO_132_IOMUX_GPIOxx 2