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Add micron_dimm_MT52L256M32D1PF-107 for new onboard memory support.
BUG=none
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Iaec4147a64313dcd461affb492805c0453e8703d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32046
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After raminit completes, do a read-modify-write test
just below CBMEM top address. If test fails, die().
Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Add GPIO_A8 for pen detect function.
BUG=b:122765828
TEST=flash BIOS and using switch to verify GPIO_A8 value change.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ie7c888ea61dd61e60c1d184565bd95e6b03777be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31815
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove bip, as it is no longer actively developed, and its EC
overflowed storage, so the EC build is no longer viable.
BUG=b:129283539
BRANCH=none
TEST=emerge-octopus coreboot chromeos-bootimage
CQ-DEPEND=CL:1538819,CL:*1086038
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: Ie9ffa704af3523908858d382e2c188422323550e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Instead of manually filling out the lb_gpios struct,
use the newer lb_add_gpios notation, which is more
compact and less error-prone.
BUG=b:124141368
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none
Change-Id: I90795f32be5de881c94519933f36127098c184df
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32031
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As part of chromium:942901, physical dev switch functionality
is being deprecated.
This flag is no longer read after CL:1526070, and thus
does not need to be set here.
coreboot's vboot subrepository needs to be updated to include
CL:1526070 before this CL can be merged.
BUG=b:124141368, b:124192753, chromium:942901
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1526070
BRANCH=none
Change-Id: Ie5849f9e0fcb8e4e6d35d542a141bf635e751af4
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31952
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently only two devices make use of physical dev switch:
stumpy, lumpy
Deprecate this switch. If these devices are flashed to ToT,
they may still make use of virtual dev switch, activated
via recovery screen.
BUG=b:124141368, b:124192753, chromium:942901
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31943
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Add basic clock support and enable UART, SPI clocks.
Change-Id: I991bdde5f69e1c0f6ec5d6961275a1c077bc5bae
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Signed-off-by: Pranav Agrawal <pranava@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Introduce new and required GPIO APIs, using common pinmux
definitions for GPIO configuration.
TEST=build & run
Change-Id: I85ce9007c545b44371c4704a0456774d0eff12a8
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This option is duplicated in depthcharge:
https://crrev.com/c/1524811
BUG=b:124141368, b:124192753, b:128737909
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1524811
BRANCH=none
Change-Id: Id8c207ec4ad5a476e24eee1ceb9e40f24d55e725
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31926
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This option has been relocated to depthcharge:
https://crrev.com/c/1524806
BUG=b:124141368, b:124192753
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1524806
BRANCH=none
Change-Id: Ib4a83af2ba143577a064fc0d72c9bc318db56adc
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31909
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In my case, on UPsquared board with Celeron N3350 CPU,
I don't have UART2 but UART0.
Change-Id: Id9a742144eba0f1d1544aafecf44d4730d055b4a
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.
BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”
For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"
Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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There are 3 PCI-E 1x ports on p5q_pro and p5qc, which correspond to
the first three functions of 1c.
Confirmed on a p5q_pro board.
Change-Id: I779400494e27bf046996512d1f772311e6e4e091
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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gale has a button which is essentially used as a
"physical presence" button. Its only use is to emulate
^D or ^U on boot when the button is pressed.
(See depthcharge src/board/gale/board.c)
Previously (and currently in CrOS firmware branch) this
GPIO was defined as the physical developer switch,
and read as such in depthcharge. It was removed in
cleanup patch CB:18980.
Add the GPIO back as physical presence ("presence"),
which will be read by depthcharge in CL:1532492.
BUG=b:124141368, b:124192753, chromium:942901
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic144f839b7f9933d573db8f84c4bf5905eea96f6
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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The TPM driver isn't loaded in other stages but verstage so when we try
to communicate with the TPM it fails. We don't need to communicate with
it anyway since the TPM won't continue to tell us that recovery was
requested, only the first query responds with the recovery request.
BRANCH=none
BUG=b:129150074,b:123360379
TEST=1)boot arcada without recovery and notice that the "tpm transaction
failed" log lines are no longer present. 2) boot into recovery using the
ESC refresh power key combination and verify that the recovery reason
was "recovery button pressed"
Change-Id: I13284483d069ed50b0d16b36d0120d006485f7f4
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Fixes Coverity CID 1393957 (Missing Comma)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I63ee47f870081bcf081bcf6dcec764e830b4ab75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ia7a3eb2e29eb245c0e70abc23c2139aebc07cbfe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: Id4f5e1fad935645830782ba922f55f614c72cf06
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31353
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Avoid preprocessor here, also we never set loglevel
to value of >8 so the call would not be made.
The calls to ram_check() were removed, for a long
time that function has not tested start..stop region.
Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch ensures to make use of common MP Init Kconfig to
choose desire method to peform MP initialization for platform.
Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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mainboard users can select correct MP Init Kconfig in order to
perform MP initialization.
1. Native coreboot MP Init.
2. FSP to do MP Init.
3. FSP to make use of coreboot MP service PPI to perform MP Initialization
Change-Id: Ifbea463fdaf97d68c21a759c37f49492d58a056b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add support for bootblock and postcar, which were introduced on qemu
in the last few month.
Fixes non-working debugcon in those stages.
Change-Id: I553f12c2105237d81ae3f492ec85b17434d8334c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31833
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I52c852fb449de5a6512aa2556592e6dfe7b0c573
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This is the second of 2 patches upgrading the SMBIOS interface to the latest 3.2
First patch is in mosys. Newer required fields are added to various types definitions
BUG=NONE
TEST=Boot to OS on GLK Sparky
Change-Id: Iab98e063874c9738e48a387cd91341d266391156
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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We have more test data now so update the DPTF accordingly.
* Change passive temp to 50/57/55/52 C
* Change critical temp to 75C
* All interval to 20 secs
BUG=b:113101335
TEST=temp/perf looks better in thermal chamber test.
Change-Id: I872c3f1875d0cbac148c44c449954e6871c9d0b0
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change enables user to shutdown the system by shortly pressing
power button (<10sec) before OS is loaded. Main use case is shutdown
from recovery/broken screen.
BUG=N/A
TEST=Boot up into recovery screen on Sarien platform, press power button
once, and system should shutdown immediatelly.
Change-Id: I7655daf65ff058df7d9bad4567f74b4f4007acb4
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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AP communicates with FP MCU through gspi1.
BUG=b:126455006
BRANCH=None
TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg
FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32017
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add serialio settings to hatch. Only applies to CML.
BUG=b:128347800
BRANCH=None
TEST=abuild
Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32003
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bloog supports keyboard backlight feature, so enable the ASL code.
BUG=b:127736039
BRANCH=octopus
TEST=Build and boot bloog, verify that the string 'KBLT' is in the DSDT.
Change-Id: Iba66aade090816ea2376cae4baf4aae019cc97f4
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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We missed some PCIe root ports with previous cleanup.
Change-Id: I8bf8f8b2ca1836316f84fb7f01820a00d7194d51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I99b87004ea74a1ad0ec1d6e0c500df11dae4997c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I2b1f46865aa380c2a31e05e55418b27296c72136
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This one uses vendor-specific register for the write.
Change-Id: Ie36a87314054d00daed6a63b495bd5f5eabef66e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I05734515c0bbd043d489c76cf9cf8b2dbe0ff515
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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These signatures need to be consistent across different
architectures.
Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add SAR0, which is an SX9310. The schematics and layout have a second
SAR1 sensor provisioned on I2C4, with an interrupt of GPP_A6, but this
is not populated.
Signed-off-by: Evan Green <evgreen@chromium.org>
BUG=b:128540461
BRANCH=none
TEST=Boot kernel with sx9310 driver, see it come up happily
Change-Id: I63943cc7da5ff56f6ef6dcbd99bb8f8f031e8bf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable the HUNG_TASK as a wakeup host event, as it's used by S0ix failure
detection to wake the system back up if a suspend to S0ix never
asserted S0_SLP#.
BUG=b:123716513
BRANCH=None
TEST=Test S0ix on Hatch with appropriate EC and kernel changes.
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I447211892df210af97e8df0380bab032b14cbee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32004
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Depthcharge is changing how the RW_LEGACY CBFS is handled for alternate
bootloaders, see https://crrev.com/c/1528550 and
https://crrev.com/c/1530303. This means that RW_LEGACY must be marked as
CBFS in the fmap in order to work. All boards except for kahlee(grunt)
have CBFS marked.
BUG=b:128703316
TEST=Build and ran on grunt along with chromium patches on grunt and was
able to list alternate bootloader with ctrl+l
BRANCH=none
Change-Id: I843d565a9503d27e666a34e59aba263ec490c81f
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32019
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This option has been relocated to depthcharge:
https://crrev.com/c/1523248
BUG=b:124141368, b:124192753, chromium:943511
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1523248, CL:1525647
BRANCH=none
Change-Id: I8b3740c8301f9a193f4fce2c6492d9382730faa1
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31897
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previously, the size of memory made for vboot_working_data
through the macro VBOOT2_WORK was always specified in each
individual memlayout file. However, there is effectively no
reason to provide this customizability -- the workbuf size
required for verifying firmware has never been more than 12K.
(This could potentially increase in the future if key sizes
or algorithms are changed, but this could be applied globally
rather than for each individual platform.)
This CL binds the VBOOT2_WORK macro to directly use the
VB2_WORKBUF_RECOMMENDED_DATA_SIZE constant as defined by vboot
API. Since the constant needs to be used in a linker script, we
may not include the full vboot API, and must instead directly
include the vb2_constants.h header.
BUG=b:124141368, b:124192753
TEST=Build locally for eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
CQ-DEPEND=CL:1504490
Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all
DDI ports are enabled and hence configures the HPD and CLK for DDI ports.
This patch initializes only the required UPDs to enable display ports.
BUG=b:123907904
TEST=DP devices working correctly.
Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Legacy PCI-to-PCI (parallel) bridge 0:1e.0 is no
longer supported in these SKUs.
Change-Id: I954ee9cf8228c6352743cae968a0dd665865496c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch removes all local definitions of sub_system functions and make
use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus
devices as well.
Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch adds generic log to perform subsystem programming
based on header type.
Type 0: subsystem offset 0x2C
Type 2: subsystem offset 0x40
Type 1: Read CAP ID 0xD to know cap offset start, offset 4 to locate
subsystem vendor id.
Change-Id: Id8aed6dac24517e93cd55d6bb3b254b7b4d950d3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch removes local definitions of sub_system function and make use
of common function pci_dev_set_subsystem().
Change-Id: I91982597fdf586ab514bec3d8e4d09f2565fe56d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Guckian
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch will fix these checkpatch errors in src/arch/mips/.
- src/arch/mips/ashldi3.c:22: WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
- src/arch/mips/bootblock_simple.c:35: WARNING: braces {} are not necessary for any
arm of this statement
Change-Id: Ic859913b93dc8ed6ff64b551c8a6baf72d28c75a
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Use the compiler's `-include` switch to include `stdint.h` instead
of adding coreboot's include paths. This avoids leaking other coreboot
header files into lp0.
Change-Id: I321c0a2fc4a2b3941990804db4e1a691e1bed8c6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The work may be incomplete, we only have an emulation
power8 at the moment in the tree.
Change-Id: Icdaa0995c8610dcc636923cc79b8455dfaeaa057
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
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Change-Id: I3c8791a0ed7b3bc670cf1433fa58f9b3d68e0b97
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Motivation is to reduce use of !__PRE_RAM__, it does not
mean ENV_RAMSTAGE but we also exclude ENV_SMM with the change.
Change-Id: I1f96bb8c055a3da63274e1ab7f7d4bc70867cbf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This reverts commit 51169b7dda4a1978d622e329a1c40e384471c165.
I was not ready to enable this option yet, until it is enabled
in depthcharge it needs to stay off in coreboot or depthcharge
will attempt to do software sync without a proper driver.
Change-Id: I4840812d0541f822502cfc5c66bed27edf4d2ecc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32007
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To support both boards with the same firmware add a SKU for
each variant that is used to include the proper EC firmware
image to match what the EC is expecting.
BUG=b:119490232
TEST=tested by faking the EC response to ensure that the OS
and firmware update tools are able to determine the correct
model based on the value returned by the EC.
Change-Id: Iaa677975e0bccbee5ec8a39821fe1637f08270fa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This will be used to distinguish the mainboard SKU so that the
correct EC firmware can be bundled with the board.
This is read from EC RAM so it can be used by an ACPI method in
the future.
BUG=b:119490232
Change-Id: I71b8017fc4b88e793dfe709e1cb1ab0f0bcdc4fa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Commit 74aa99a (src: Drop unused '#include <halt.h>')
accidentally added '#include <halt.h>', however tegra_lp0 directory
is not linked into the rest of coreboot. So we can't use generic halt()
from halt.c file.
Change-Id: I3a67abb77846172597b8ebde779878b9aa2ff8d7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31979
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Implement reset using PSHOLD.
Change-Id: I472bf73cc7b227187b284a3730ec5dea5373695c
Signed-off-by: Santhosh Hassan <sahassan@google.com>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch adds support to copy the wifi calibration
data to CBMEM so that the depthcharge can use it to
populate the data into wifi dt node.
Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Commit 41483c9 (soc/intel/cannonlake: Add required FSP UPD changes for
CML) changed the enum values for PCH_SERIAL_IO_MODE so that 0 is
invalid and valid values start from 1. However, get_param_value was
not updated to correctly subtract 1 before returning any value. This
change adds a macro PCH_SERIAL_IO_INDEX to apply the subtract 1
operation on any value that get_param_value needs to return.
BUG=b:128946016
TEST=Verified that hatch boots successfully.
Change-Id: I4e32fcd1efe4a535251f0ec58662a2dc5f70e8b0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds support for logging EC events during S0ix resume.
BUG=b:124131938
BRANCH=none
TEST=Verified that the wake events are logged during the S0ix resume:
4 | 2019-03-05 07:55:27 | System Reset
5 | 2019-03-05 07:55:27 | Chrome OS Developer Mode
6 | 2019-03-05 07:56:54 | S0ix Enter
7 | 2019-03-05 07:57:09 | S0ix Exit
8 | 2019-03-05 07:57:09 | Wake Source | Power Button | 0
9 | 2019-03-05 07:57:09 | EC Event | Power Button
Change-Id: I624f94c29bc66dbf4d9e1fec573d259985260ed3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Check if `pcie_dev` is NULL instead of `dev`. This was flagged
as REVERSE_INULL during a Coverity scan, but is a simple typo.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Idc40574b9341d1b10cb2136cbc1a865efa3ab3ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31866
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create a new cbtable entry called VBOOT_WORKBUF for
storing a pointer to the vboot workbuf within the
vboot_working_data structure.
BUG=b:124141368, b:124192753
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none
Change-Id: Id68f43c282939d9e1b419e927a14fe8baa290d91
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31887
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove FSP 2.0 support from ICL SoC and add FSP 2.1 support.
Change-Id: Ife0c133ddbf2e0fa14f94ffec15d11830cfaf7b3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30158
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support for FSP2.1 Kconfig which is backward compatible
with FSP2.0 specification and added below coreboot impacted features as below:
1. Remove FSP stack switch and use the same stack with boot firmware
2. FSP should support external PPI interface pulled in via
FSP_PEIM_TO_PEIM_INTERFACE
Change-Id: I2fef95a783a08d85a7dc2987f804a931613f5524
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30310
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to have below listed features:
1. All required APIs to create MP service structure.
2. Function to get MP service PPI status
MP specification here:
http://github.com/tianocore/edk2/blob/master/MdePkg/Include/Ppi/MpServices.h
coreboot design document here:
../Documentation/soc/intel/icelake/MultiProcessorInit.md
Supported platform will call fill mp_services structure so that FSP can
install the required PPI based on coreboot published structure.
BRANCH=none
BUG=b:74436746
TEST=Able to publish MP service PPI in coreboot.
Change-Id: Ie844e3f15f759ea09a8f3fd24825ee740151c956
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25634
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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RK3399 SoC code still manually excludes the BL31 region from the memory
map, even though that is now automatically done with the BL31()
memlayout region. CB:31123 and CB:31538 just forgot to remove this line.
The resulting memory map stays the same.
Change-Id: I87458fa09f437b038af10e0fd9d76ef6d9394bc5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ting Shen <phoenixshen@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I0e1a66b3d1d7bd4633ad1df597f62ddbd38f46d4
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Default reserved value of used for SCI IRQ.
Configure SCIS field to use IRQ 9.
BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I09aca433528b6f64ad3ff3753ae8392c0d89cdc0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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This board is compatible with Intel Skylake and Kaby Lake generation
processors. This patch contains the minimum configuration for booting
and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15).
It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH.
Graphics init with libgfxinit.
Works:
- Integrated graphics (only DVI port, tested with 1920x1080);
- PEG x16 (FSP must be configured with BCT to enable PEG);
- all PCIe x1 slots;
- all USB and SATA ports;
- SuperIO COM port for console;
- onboard audio.
TODO:
- other SuperIO functions;
- onboard network chip;
- suspend and resume;
- documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10-
g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I6577d9a31da44be5b57bb10497d9bd02fc9bbcd3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Iee09b601045d7785a0977a4f7ed7385b1d311044
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Move these configs to Kconfig.name as well.
BUG=b:127310803
BRANCH=None
TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: I793363740fa0730a1e9e1aa7a9fa82d2789334b4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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TEST=build
Change-Id: Iea79a942c297400c88aa205da713bcfcb8c51185
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Init frequency to 19.2 MHz
TEST=build
Change-Id: I566c7ff2b7085c9dd89ea74a08f3ba862feab2ab
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Initialize 1st 4GB as Device Memory, except:
* 1st page: NULL address
* System_IMEM: Cached SRAM
* Boot_IMEM: Cached SRAM
Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Adding a new board variant 'Mistral' based on qcs405 soc.
TEST=build
Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Adding the basic infrastruture soc support for qcs405 and
a new build variant.
TEST=build
Change-Id: Ia379cf375e4459ed55cc36cb8a0a92cab18b705e
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The mmio resouces IOAPIC and ROM area not reserved.
Reserve IOAPIC and ROM resources.
BUG=N/A
TEST=Intel CherryHill CRB booting Embedded Linux
Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The .chip_info field of PNP devices in overridetree
incorrectly pointed to southbridge config structure
in generated static.c files.
Change-Id: If507c8ea9c865ff86e127226b93a8579bcf39d8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I311269967949533264e44fd3bb29ad3a06056653
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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coreboot have an option to use legacy UART or LPSS UART. FSP will use the
UART initialized by coreboot and we can choose an option to skip Uart
initialization by FSP.
For this, we need to pass correct debug interface flag to FSP through
which FSP will know which UART port to use. If we don't pass correct
interface information, FSP may try to dump logs on that port and it may
slow down the system.
BUG=none
BRANCH=none
TEST=Compile and boot with coreboot. Check FSP and coreboot logs are
coming on serial port.
Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add the include for size_t.
Fixes compilation error on source files that do not include it.
Change-Id: Ic752886d94db18de89b8b8a5e70cf03965aeb5c3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fix a potential null pointer dereference when calling
memcpy. assert should be before the memcpy call,
and not after.
BUG=b:124141368, b:124192753
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I5a2a99e906b9aa3bb33e1564d8d33a0aca7d06ac
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31923
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id3501e65a9d0c0b5ad98679f5e78f985e87cbe55
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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V1CAP is a write-once register, and it is already programmed in
intel/i945/early_init.c.
Tested on 945G-M4 board (i945G + 82801GB).
Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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SLOTCAP is R/WO, it becomes RO after the first write.
Write already done on line #583.
Tested using kprint before and after on 945G-M4 board.
Change-Id: I27579bc634e357490defabb041457aaa010fb1c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Enable software sync by default if VBOOT is enabled.
The slow update option is also needed, but this is moving
to depthcharge so it is not defined here.
Change-Id: I046661fae7315f84e96293532b4e1568558df962
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If the command does not respond the driver should not wait for
it to complete before returning.
Tested with SMI debug enabled to ensure that the final command
does not report a failure.
Change-Id: I7c1bfa19a92e8332ac1aa6ff95f94ff4cbdf789d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update the Kconfig option for disabling ESPI SMI source
to disable it entirely, not just when ACPI mode is disabled.
For the situations where this is needed (just the sarien
board) it is better to completely stop the EC from sending
any SMI events as no actions are taken.
Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add bluetooth Rfkill function to recover the Bluetooth controller in
cases where itself has entered a bad state and needs to be recovered.
Bug=b:123342945
TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under
Bluetooth devices with GPIO in.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibbe67887227af42b6c040deade7bf5da4ce3227f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Initialize the clock of the Gigabit Ethernet Controller.
Change-Id: I172dc518c9b48c122289bba5a65beece925410d4
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
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Disable the use of AMD's Secure OS through the Kconfig option.
BUG=chromium:903833
TEST=Build google/aleena, verify types 02, 0c, 0d are removed
from PSP directory table
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Fix a spelling error in the name.
TEST=Build google/aleena and compare amdfw.rom before/after
Change-Id: I727ba1d6a8991caa1cdddcfca94c55c73954320a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch overrides required LPSS FSP UPDs for CMLRVP from devicetree.cb
File devicetree-override.cb will override required UPDs and is only
applicable to CML soc for now
Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support to select CMLRVP board.
Change-Id: I5f81b47f33345edefa0a7064559d9531e1d20eff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Clone entirely from mainboard/intel/coffeelake_rvp/../whl_u
commit id: 73916defba8d036c2536e1b37a1449ac16e5f56f
Change-Id: Icc32a6e1940ba2d13f3ad74cddbb4b75a637cc18
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch creates new resource function to perform allocation
of IO resource, similar to mmio_resource() function does for MMIO.
Change-Id: I3fdcabb14302537d6074bfd6a362690c06b66bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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