diff options
author | Subrata Banik <subrata.banik@intel.com> | 2019-02-02 13:38:33 +0530 |
---|---|---|
committer | Subrata Banik <subrata.banik@intel.com> | 2019-03-18 06:20:34 +0000 |
commit | 695f7249a43c36a674601cf3185149566e2d7492 (patch) | |
tree | 7b4a288ee90c318c77e9f5f2f79e7eb6ef745fff /src | |
parent | 1a27b0bc38fb3483ad8fcebbd3d876633698c1ea (diff) |
mb/intel/coffeelake_rvp: Add cml_u board support
This patch adds support to select CMLRVP board.
Change-Id: I5f81b47f33345edefa0a7064559d9531e1d20eff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/intel/coffeelake_rvp/Kconfig | 9 | ||||
-rw-r--r-- | src/mainboard/intel/coffeelake_rvp/Kconfig.name | 3 | ||||
-rw-r--r-- | src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c | 3 |
3 files changed, 11 insertions, 4 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index d2d4b81013..185d7569bd 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP config BOARD_SPECIFIC_OPTIONS def_bool y @@ -13,8 +13,8 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 - select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP - select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP + select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU + select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 @@ -28,10 +28,12 @@ config VARIANT_DIR default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8 + default "cml_u" if BOARD_INTEL_COMETLAKE_RVP config MAINBOARD_PART_NUMBER string default "whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP + default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVP default "cflrvp" config MAINBOARD_VENDOR @@ -41,6 +43,7 @@ config MAINBOARD_VENDOR config MAINBOARD_FAMILY string default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP + default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVP default "Intel_cflrvp" config CHROMEOS diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 70652eff66..35c0f0ff4a 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -12,3 +12,6 @@ config BOARD_INTEL_WHISKEYLAKE_RVP config BOARD_INTEL_COFFEELAKE_RVP8 bool "-> Coffeelake S U-DIMM DDR4 RVP8" select SOC_INTEL_COFFEELAKE +config BOARD_INTEL_COMETLAKE_RVP + bool "-> Cometlake U DDR4 RVP" + select SOC_INTEL_COMETLAKE diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index b0091bd41a..e34514679a 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -264,7 +264,8 @@ static const struct pad_config gpio_table[] = { /* H21 : GPPC_H_21 */ /* H22 : GPPC_H_22 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), -#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) +#if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) || \ + IS_ENABLED(CONFIG_BOARD_INTEL_COMETLAKE_RVP) PAD_CFG_GPO(GPP_H22, 1, PLTRST), #else PAD_CFG_GPI(GPP_H22, NONE, DEEP), |