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2022-07-13cpu/x86/mp_init: retype do_smm element in mp_state struct to boolFelix Held
The do_smm struct element in the mp_state struct was an int even though it only had two possible states, so change it to bool to make this more obvious. Also change the return type of is_smm_enabled from int to bool. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d2d95f0497649d67565243d14a5ab9c9cdda412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-13mb/google/nissa/var/craask: Move codec item to SSFCTyler Wang
Move audio codec item from fw_config to SSFC. BUG=b:238353613 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I361ef54cd2ee3e0a423ed5086184936d6f09e099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-13soc/mediatek: Move SPMI device table to SoC folderHui Liu
The SPMI devices on MT8188 are different from previous SoCs, so we move them to SoC folder. We also move SoC-specific definitions to soc/pmif.h. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I666c2a8222a2bd8cd460e2225a7ae48b001da9d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65757 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13mb/google/geralt: add usb host supportShaocheng Wang
Add usb host function support. TEST=read usb data successfully. BUG=b:236331724 Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Change-Id: I52174306eb0c87c6e5a3665051099b5c0e8f45a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65755 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek/mt8188: add usb host supportShaocheng Wang
Add usb host function support. TEST=read usb data successfully. BUG=b:236331724 Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com> Change-Id: I3494b687b811466cb6b988164d3c5b6fecc3016a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65754 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek/mt8188: Enable mmu operation for L2C SRAM and DMARex-BC Chen
- Turn off L2C SRAM and reconfigure as L2 cache: Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. - Configure DMA buffer in DRAM: Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I10f1cb8c62dfa78f59a4a5ea6087609668a0c2aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65753 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-13soc/mediatek/mt8188: Add video/audio mtcmos settingRex-BC Chen
Add power domain data for video and audio. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: Ic5fd496cbc6904b42eae28a62bf00a71f0ef508d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13soc/mediatek/mt8188: Add PLL and clock init supportgarmin chang
Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. For usb clock setting, we also implement mt_pll_usb_clock_setting() to enable usb clock for all ports. TEST=build pass BUG=b:233720142 Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Change-Id: I03cb5a4c6fa5ddad7da6f955d0c6d0b3395503e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-13mb/google/nissa: Remove GPP_B11 PAD configurationHarsha B R
Remove the pad configuration for GPP_B11 as this is not used in Nereid/Nivviks BUG=b:227694137 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3a213ffece75b9a706b96dc142a7e35c8b5973f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-13soc/intel/meteorlake: Use double digit GPIO pad numbersKapil Porwal
Google uses two digit GPIO pad numbers for internal GPIO references and Intel has updated their GPIO naming schemes too (see the GPIO implementation worksheet #641238) so use double digit GPIO pad numbers. Format - "GPP_%c%02d", gpio_group, gpio_pad_num e.g. GPP_A0 -> GPP_A00, GPP_V2 -> GPP_V02, GPP_C9 -> GPP_C09 etc. BUG=b:238196741 TEST=Able to build meteorlake based google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ieb7569c1a35b08c0970a604ec7b4b91e6179dd28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65719 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-13vc/intel/fsp2_0: Update partial headers to MTL.FSP2253.00Kapil Porwal
Update partial headers to MeteorLake FSP v2253.00 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: If2d6c80bd35afd68588fef57e38064c5b1e1a888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-12soc/samsung/exynos5420: Use int instead of char for count variablePaul Menzel
This micro optimization of using unsigned char instead of unsigned integer actually generates one more instruction. .LVL296: .LVL296: .L198: .L198: .loc 1 912 16 is_stmt 1 discriminator 1 view .LVU1740 .loc 1 912 16 is_stmt 1 discriminator 1 view .LVU1740 uxtb r2, r3 | cmp r7, r3 cmp r7, r2 < bhi .L199 bhi .L199 .loc 1 916 1 is_stmt 0 view .LVU1741 .loc 1 916 1 is_stmt 0 view .LVU1741 add sp, sp, #36 add sp, sp, #36 .cfi_remember_state .cfi_remember_state .cfi_def_cfa_offset 20 .cfi_def_cfa_offset 20 @ sp needed @ sp needed pop {r4, r5, r6, r7, pc} pop {r4, r5, r6, r7, pc} Fix it, so nobody can copy that. Change-Id: If5ffeacc7ac3c53a82b260cfb81ef7debc40034a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-12soc/mediatek: Add mt_pll_set_usb_clock() to enable usb clockRex-BC Chen
There are clock settings for usb in mt8195 and mt8188, so we add a new function which is implemented in pll.c to do this. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40b358b197541bc5281645879553340059829db3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-12soc/mediatek/mt8188: Add I2C driver supportkewei.xu
Add I2C controller drivers. TEST=build pass BUG=b:233720142 Signed-off-by: kewei.xu <kewei.xu@mediatek.corp-partner.google.com> Change-Id: I7d19df3571e5588c7b20d9c7f26fa177b2221851 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-12mb/google/dedede/var/shotzo: Update GPIO GPP_S2/S3 pin definitionTony Huang
Based on latest schematic: Set GPP_S2 DMIC1_CLK/ GPP_S3 DMIC1_DATA to NC. BUG=b:235303242 BRANCH=dedede TEST=build Change-Id: I4044cb7ba963153e1e478294dbf960fb79b97b5c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-07-12mb/google/brya/var/agah: Disable thunderbolt interfaceTony Huang
Agah doesn't support TBT interface so disable it in devicetree, for fitimage configuration is at chrome-internal:4846869. BUG=b:224423318 TEST=Build and check DUT boots. Change-Id: I1eb43e86de5debf24ebde6eace14fe04bad5e5b1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65699 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mb/google/brya/var/banshee: Update VR domain settingsFrank Wu
Update the VR domain settings based on the request of internal team. - IA ac_loadline from 2.3mOhms to 2.4mOhms. - IA dc_loadline from 2.3mOhms to 2.28mOhms. - GT ac_loadline from 3.2mOhms to 3.13mOhms. - GT dc_loadline from 3.2mOhms to 2.94mOhms. BUG=b:237044562 BRANCH=firmware-brya-14505.B TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I665665ab8e3bcd6d4643f8b954b86fad3ef78ccd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-11soc/samsung/exynos5420: Add space between comment markers and commentPaul Menzel
Change-Id: Ica9014ee077ea416fdb4c7316c9619cf81fca510 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-07-11soc/intel/meteorlake: Align TCSS functions through SBIJohn Zhao
This change aligns the Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication through the sideband access. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I393f6e1c7d322878cbb684cd95bfa2477195b23a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-11soc/intel/common/block/pmc/pmclib: Use same loglevel as print_num_status_bitsPatrick Rudolph
Use same log level as print_num_status_bits to make sure the status bits are properly prefix and the newline is added. Change-Id: Ib33798eec7cba601d0d49646c5fc429de5268417 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65715 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-07-11mb/msi/ms7d25: Properly handle CnvDdrRfim parameterMichał Żygowski
CNVi DDR RFIM feature should be reported via _DSM function. Add the generic WiFi device which will generate the proper ACPI code and pass the CnviDdrRfim parameter to FSP by SoC driver. TEST=Connect to WiFi network on Ubuntu. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ice2abe972f38dd819f7f0103f7b9a697096f1cd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63835 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Add USB macros and port designation commentsMichał Żygowski
Add the comments about port designation after mapping the root hub ports to board connectors. Add macros reflecting the length of the USB signal traces. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib2e842ef240ab25e2a9f7fa2e0766206fde7943d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-11mainboard/msi/ms7d25: Add default vboot configurationMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9590a33e828906de083cb23c8b647ed2da0750ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/64222 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Add FIVR configurationMichał Żygowski
Reflect the vendor's firmware FIVR settings. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I97b3b4f9470267961c138fea70703606373f6d52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64051 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Fill board-specific SMBIOS dataMichał Żygowski
Add board connectors and headers descriptions to SMBIOS. Specify type 1 and type 2 fields as in vendor firmware. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie64be21ff302274769b77550c29e58d4ea1376d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64050 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Add NCT6687D configurationMichał Żygowski
TEST=Boot Ubuntu 22.04, load nct6687 kernel module and use lm-sensors to display information about sensors on the SIO EC. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I55445a94f0de3510324b12558c4343e819412ac0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63928 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mainboard/msi/ms7d25: Enable PTTMichał Żygowski
Original firmware ships with PTT enabled by default on poweron. PTT takes priority over SPI/LPC TPM so enable the CRB interface until coreboot implements a way to select the interface and adapt the API to handle any TPM detection. TEST=Boot the board and see PTT is detected by Windows and Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I74dc2c4245388a9f134b27e313ef26124b952594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63834 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mb/msi/ms7d25: Configure HD AudioMichał Żygowski
Apply correct configuration of HD Audio. TEST=Launch ubuntu 20.04 and launch a YouTube video, check if microphone detects an input in the system sound settings. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6acc22aa58f6cc99df1d48d651122e74fe08ec02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63723 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-11mb/msi/ms7d25: Configure PCIe Root PortsMichał Żygowski
Add the full PCIe root port configuration. Proper initialization of the root ports depends on the correct GPIO programming including virtual wires. Do not program the CLKREQ signals in coreboot to let FSP detect and configure CLKREQ pads. Otherwise the CLKREQ pads are reprogrammed by FSP despite having GpioOverride=1. The pads that should not be touched by coreboot are left commented in the board GPIO file. CLKREQ reprogramming caused undefined behavior when ASPM and Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed a lot of exceptions and simply halted). TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots populated and check if they are detected and functional in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-10mb/lenovo/haswell: Convert to variant setupFelix Singer
In preparation to CB:63514, make use of the variant concept and convert the existing T440p mainboard into a variant. Change-Id: I3c7e06607135ce0a62c158e296b51e5311234505 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-07-09mb/google/brya/var/kinox: Override tdp pl1 valueDtrain Hsu
Override tdp pl1 value to 30W in CPU MSR. BUG=b:238268367 TEST=Boot to Chrome OS and check cpu log show "CPU PL1 = 30 Watts". Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ibbd5ecc4b87ede5a62799020c741e5bff2952144 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-09ec/system76/ec: Hide ACPI device S76DJeremy Soller
Hide the device so that Windows does not warn about a missing driver. Tested on system76/lemp10: - EC functionality remains functional on Linux 5.18.6 and Windows 10. - Windows 10 does not report the device in Device Manager. Change-Id: Iffcb873b85e077535d4de5806d01ba309f46c017 Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-09*/fsp/exit_car: Push stack address into %espArthur Heymans
Fixes: 5315e96abf ("arch/x86/postcar: Use a separate stack for C execution") Resolves: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/TGIWAKZKELJRAEMKJNYRJ55MX2CXYNCV/ Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/ thread/2JC3GNJSGXUD6DRVUY7O2O3W6OM3E2MY/ 5315e96abf broke platforms using FSP-M to tear down CAR. It was pushing the value at '_estack' into %esp rather than the address '_estack'. Change-Id: Ie1fc70bd60fe3a2519ffb71625a35630fa732ff6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65716 Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-08mb/google/brya/var/ghost4adl: Update GPIO tableJack Rosenthal
Based on comments on CL:65534, update the non-early GPIO table. These are cases where Arbitrage wasn't able to find a useful heuristic, or the memory straps, where Arbitrage sees them as NC in the schematic. BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I6e00892243cd6af99dc1921ee3fc712f6cbb58c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65710 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08mb/google/brya/var/ghost4adl: Add early GPIO tableJack Rosenthal
Customize brya baseboard early GPIO table to add mem straps for ghost4adl, change I2C bus for TPM to pins H6/H7, and remove pins which are not used on ghost4adl (E16, H13). BUG=b:234626939 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I126a66fc5d24fbefec99abf87862c55b50c5e398 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65534 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08soc/intel/apollolake/meminit.c: Remove unuseful commentElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia81b4397c92f100abad9b1e974bbebfe49008439 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08mb/google/guybrush: Remove duplicated includeElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I19cd9360a2571e8b88b1ed1005ce8564bdacb297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08soc/amd/common/block/lpc/lpc.c: Remove duplicated includeElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Idd214893f304ce767633ffbf905f47a5092c2ee4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-08superio/nuvoton/nct6687d: Add ramstage driver and ACPIMichał Żygowski
TEST=Boot MSI PRO Z690-A WIFI DDR4 with SP1, KBC and EC exposed to OS via ACPI. Configure SP1, ACPI, KBC and EC devices via devicetree. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia489a39956c1448c7f11845ecc9e1df83ccb25ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/63927 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08mb/msi/ms7d25: Enable displaysMichał Żygowski
Add VBT from vendor firmware v5.24 and configure display outputs in devicetree. TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the connected display via HDMI or DisplayPort on rear panel. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-08mb/msi/ms7d25: Add correct memory init configurationMichał Żygowski
Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs. TEST=Include the microcode from vendor firmware and FSP blob from Intel R&DC. Boot the platform and see ramstage is executing. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-08soc/intel/apollolake: Fix incorrect GPE numberReka Norman
BUG=None TEST=None Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I2eb6e94e5d87bb19b11e27461e2b5bdaee9d59bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65691 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08mb/google/brya/variants/felwinter: Add fw_config to control TBT PCIe RP0John Su
Use USB4 fw_config to enable TBT PCIe RP0. BUG=b:237619214, b:237623610 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ie3e51a0f30e0c9d20127c017436813d4ede95639 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65696 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-08soc/intel/common/pch: Fix incorrect GPE numberReka Norman
BUG=None TEST=None Change-Id: I7a4081f0f57e0faa968ad142debdc40a9e26dc9b Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65690 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-08mb/google/nissa: Don't put WLAN into D3coldReka Norman
On nissa, WLAN should be a wake source, so don't put it into D3cold during suspend. BUG=b:233325709 TEST=Wake-on-WLAN works on nereid Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-08soc/intel/alderlake: Hook-up public Alder Lake microcodeMichał Żygowski
CPUIDs and Engineering Samples decoding based on DOC #618427. Keep MICROCODE_BLOB_UNDISCLOSED for PCH-N SKUs as microcode blobs are still missing. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ibb1337e5cbf5b82fdaceb7eb4661d708a32ff0ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65564 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-07-08mb/google/nissa: Enable Cnvi BT Audio Offload featureV Sowmya
This patch enables Cnvi BT Audio Offload feature and also configures the virtual GPIO for CNVi Bluetooth I2S pads. BUG=b:233834597 TEST=Verified BT offload feature on Nivviks P1. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iffbd08351d083d2b550f309994af931bceb257d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-08mb/google/nissa: Confiure the unused virtual Cnvi BT GPIOs to NCV Sowmya
Configure the unused virtual CNVi BT GPIOs to NC since we are using BT over USB mode for Nissa. BUG=b:233834597 TEST=Verified BT offload feature on Nivviks P1. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Id84823b9ad921ebd7ff773d6cce581563613745f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65669 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-07-08mb/google/nissa: Disable the Package C-state demotionV Sowmya
Disabling the Package C-state demotion feature for nissa baseboard as a work around to the S0ix issue and also this doesn't have any impact on the power and performance measured and verified by the PNP team. This feature will be enabled after its functionality is verified with no issues and also based on its impact on PNP. BUG=b:235005582 TEST=Boot and verify that S0ix issue is resolved. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I4d586b962c27b86ee75651dcd655bc0868504646 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65664 Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-08soc/intel/adl: Add support to configure package c-state demotionV Sowmya
This patch adds the support to enable/disable package c-state demotion feature from the devicetree based on mainboard requirement. BUG=b:235005582 TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I9e254988bc3d20b9f9e42a605cc0ebd419ab49ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/65663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-08lib/fit.c: Don't align memory regions to 1MBArthur Heymans
Aligning the "memory" ranges in devicetree is supposedly only needed on very old arm32 kernels. So let's get rid of it. Incidentally this fixes smaller than 1MB memory regions where the size would end up being 0. Change-Id: Ibbf5e331c79ed4ae3ed8dd37bf7a974d2412ce12 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-07soc/intel/common/graphics: Add another Meteor Lake device IDWonkyu Kim
Add 0x7d55 as another ID for Meteor Lake graphics controllers. TEST=Boot with MTL silicon to check coreboot log for DID2 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2022-07-07mb/google/brya/var/ghost4adl: Update the PCIE and USB settingEric Lai
Based on latest schematic to update the PCIE and USB setting. BUG=b:237659398 BRANCH=firmware-brya-14505.B TEST=emerge-ghost coreboot Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I97989b7a8d9104379ffb0b454d7248d49855f680 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
2022-07-07mb/google/brya/var/crota: Add DPTF setting in CrotaJohnny Li
DPTF Policy and temperature sensor values from thermal team. BUG=b:237640264 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: I43340bd1acfe6ec2036ea80339dbf896615a456a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65563 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/alderlake: change functions arguments to constEran Mitrani
Change-Id: Ib8d9a9e94d16ad291d9cc8576db845a634ae026e Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65614 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07mb/starlabs: Rename LabTop to StarBookSean Rhodes
The LabTop was renamed to StarBook since the release of the Mk V. This change keeps the directory name more relevant, as there are more boards using the name StarBook. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3513fb56c1adf663ed7bcdade2cc52cd8c0d6f4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65640 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-07mb/lenovo/t420s: Reorder selects alphabeticallyFelix Singer
Change-Id: I76e4438dea6a7fcce06211af808eee51465f19c5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-07-07mb/lenovo/x220: Reorder selects alphabeticallyFelix Singer
Change-Id: I4fd7f86a61d1a1a8133a633eb257275222f27af9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-07-07mb/lenovo/x131e: Reorder selects alphabeticallyFelix Singer
Change-Id: I65f8e6860a7f734a7d2b8c0055cb18d851f38ad0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-07-07mb/lenovo/s230u: Reorder selects alphabeticallyFelix Singer
Change-Id: I62d8374eb7c2499d34c3f43c9f7fd01caaa3e2f4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-07-07mb/lenovo/t430: Reorder selects alphabeticallyFelix Singer
Change-Id: Ia8a78e9947466e88fb9abf1b91ef21ce763240c1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-07-07mb/lenovo/x1_carbon_gen1: Reorder selects alphabeticallyFelix Singer
Change-Id: I25d0f5a97ec5dd023e2acb458de1b20427fe353e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-07-07mb/google/brya/var/kinox: Enable SaGvDtrain Hsu
Enable SaGv support for Kinox BUG=b:238153479 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Id4646f1621a414a1ec4e272c826b0baea2bb4e19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-073rdparty/blobs: Advance submodule pointerSean Rhodes
This contains the following commits: * d55c315 mb/starlabs: Remove padding from logo * 6412d38 mb/starlabs/starbook/cml: Update EC from 1.03 to 1.07 * fb72ac5 mb/starlabs/starbook/tgl: Update EC from 1.00 to 1.03 * cda5eaa mb/starlabs: Rename labtop to starbook * f16020a Revert "soc/mediatek/mt8186: Update SPM firmware to pcm_suspend_v0215… This also changes starlabs/labtop Kconfig to use the new paths for the EC binaries from the above commits. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I83143118af422276ee335ad4ef9eca76f54a9fc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-07-07mb/google/brask/var/kuldax: modify ddi_ports_configDavid Wu
Modify ddi_ports_config based on schematic. DDI_PORT_A = DP DDI_PORT_B = HDMI DDI_PORT_1 = Type-C DP DDI_PORT_3 = HDMI BUG=b:237419696 TEST=Boot to Chrome OS and check all display port working Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I7c0458f0dbd4637b91af9e01664073e1f8a7a614 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07soc/intel/alderlake/acpi/gpio.asl: Add GPIO Commnity 3 for ADL-SMichał Żygowski
This patch fixes the issue with INTC1056 invalid resource reported by alderlake-pinctrl Linux driver on ADL-S platform. The driver also includes GPIO Community 3 in the GPIO list compared to ADL-N which was missing in GPIO ACPI device. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A DDR4 WIFI and check there is no invalid resource error reported by alderlake-pinctrl Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I23da68c247de86438cc2eef2b5a5a9aa711c1d7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07soc/intel/alderlake/acpi/gpio.asl: Fix lower case typoMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If66c2799d4d74ff9f309665a0336b5f679796f9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-07mb/google/brya: Change GPP_F17 programmingTim Wawrzynczak
Currently the EC's MKBP interrupt line is programmed as dual-routed to both SCI and IOAPIC. The brya EC will pulse the MKBP GPIO and also send a host event when there is an MKBP event for host to service. This causes an extra SCI to be generated, and the kernel will respond to each MKBP event with an extra unnecessary host command. Changing the pad configuration for the MKBP GPIO to APIC only fixes this issue. BUG=b:236706977 BRANCH=firmware-brya-14505.B TEST=excess GET_NEXT_EVENT host commands are gone from EC log Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic7dd596987f6d34c69d46674bdd07785235e2d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65480 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07mb/google/brya/var/agah: Update FBVDD power-down delayTim Wawrzynczak
The EEs have observed the ramp down delay on this signal in more detail and 40 ms can still meet the sequencing requirements. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-07mb/google/brya/var/agah: Remove variant_fill_ssdt()Tim Wawrzynczak
Since the GPU will be left powered on, the kernel has the opportunity to save context and this method to save the BARs is not required. BUG=b:233959099, b:236289930 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I19cf12426361a53e3672c1e05aa6d68d5dd6627c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Zieba <robertzieba@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-07mb/google/geralt: Add NOR-Flash supportRex-BC Chen
Initialize NOR-Flash in the bootblock. TEST=read nor flash data successfully. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I8ee24b5b24643bce57eb29682d6d0234a6fe8641 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65622 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/mediatek/mt8188: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers for flash read/write. TEST=read nor flash data successfully. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I4e84fc023111b86f7f4984020d24811e3361ba03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65621 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/meteorlake: Remove `ADL` instancesSubrata Banik
This patch removes all instances of the `ADL` from Meteor Lake SoC directory. TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8153b2070467beb582ce1f70be97272ce09ca04c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65667 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07soc/intel/meteorlake: Update IFD_CHIPSET kconfig valueSubrata Banik
This patch updates IFD_CHIPSET kconfig value from `ifd2` to `mtl`. TEST=Able to build and boot Google/Rex image on MTL emulation platform. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I416f881bcbe3dd7494ead636d6b593366a51b31c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-07mb/google/brya/var/kinox: Configure TDC currentDtrain Hsu
Configure TDC current for VR domains. +-----------+-------+-------+---------+-------------+----------+ | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | +-----------+-------+-------+---------+-------------+----------+ | IA | 2.8 | 2.8 | 80 | 43 | 28000 | +-----------+-------+-------+---------+-------------+----------+ | GT | 3.2 | 3.2 | 40 | 23 | 28000 | +-----------+-------+-------+---------+-------------+----------+ - IA TDC current from 20A to 43A. - GT TDC current from 20A to 23A. - Others comes from 'commit c6d716694272 ("soc/intel/alderlake: Configure the SKU specific parameters for VR domains")' BUG=b:237230877 TEST=Build and boot to Chrome OS Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ie9cf8975309b57b4189e2b50f37bd61ac0105e14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65659 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-07mb/google/brya/var/kinox: Support DPTF oem_variablesDtrain Hsu
Enable DPTF oem_variables and override based on charger type. BUG=b:230803675 TEST=1. With 90W adapter, check ACPI object ODVX and oem_variable[0]=1 Name (ODVX, Package (0x06) { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }) 2. With 65W adapter, check ACPI object ODVX and oem_variable[0]=0 Name (ODVX, Package (0x06) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }) Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I78929ecbc9db56aa234b3f46c641d1f2f3b7cba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-07mb/google/brya: Disable SaGV support for agah variantAnil Kumar
agah proto boards with i7 silicon face boot issues due to high power consumption during MRC training. This patch is a temporary WA to run in SAGV disabled mode while the thermal issue is being investigated. BUG=b:234402102 BRANCH=firmware-brya-14505.B TEST=Build CB image and boot on agah board. Change-Id: I431d233b23fb4f5c68117ea380fdec5646b88346 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65300 Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-07mb/msi/ms7d25: add basic FSP configuration in devicetreeMichał Kopeć
Configure some basic FSP parameters in devicetree for to allow for booting an OS. Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63499 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mb/msi/ms7d25: add GPIO configurationMichał Kopeć
Based on the output of: - inteltool from CB:63374 - intelp2m from CB:63403 TEST=Build coreboot binary for msi/ms7d5 and boot the board. Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-07mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFIMichał Żygowski
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-07-06soc/intel/common: Update the comment on CSE Region layoutSridhar Siricilla
The comment indicates CSE's data partition is placed after BP2. But, it was place after BP1.So, the patch updates the comment to reflect the CSE Region layout correctly. TEST=Build the code for Brya and didn't notice any compilation errors Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic871e2e395de17157f4f526064a26bfad538707f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-07-06soc/mediatek: Move FLASH_DUAL_READ to commonRex-BC Chen
FLASH_DUAL_READ is a common configuration for all MediaTek SoCs, so we move it to common folder and select it in SoCs' Kconfig. As suggested in CB:58837, we also rename FLASH_DUAL_READ to FLASH_DUAL_IO_READ to reduce confusion. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If267a332519412a7919c5b7817047fabe4a564c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65620 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-06soc/mediatek/mt8188: Add GPIO driversGuodong Liu
Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:233720142 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I0a2a5178949e9ad3e033ac332e0f1e8565e39b3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/65619 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek: Move some gpio functions to common/gpio_op.cRex-BC Chen
gpio_set_pull(), gpio_set_pull_pu_pd() and gpio_set_spec_pull_pupd() can be reused for mt8192, mt8195 and mt8186, so move it to new file "gpio_op.c" in common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I81ab9b01ee20fccf3ef29c5902597b5045d3e36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65641 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek/mt8188: Add timer supportBo-Chen Chen
Add timer drivers to Makefile. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I0e3e58c7118a18e738a5abba391db0be9cfd7bf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65588 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek: Make timer_prepare() a common functionRex-BC Chen
timer_prepare() is the same for MT8195 and MT8186, so move it to common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I91a6f4ecc665a058cb7a0ba96c15b27d6dc97d13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65602 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/mediatek/mt8188: Initialize watchdogBo-Chen Chen
Add watchdog support for MT8188. This implementation is based on chapter 3.10.10 in MT8188 Functional Specification. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iaf56c78d89af53d0272583b463c050e69bbeb07a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65587 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-06soc/mediatek: Move wdt_set_req() to common folderBo-Chen Chen
There are more and more variables which are SoC-specific, so add soc/wdt.h for each SoC and rename common/wdt.h to common/wdt_common.h. wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so move it to a common file wdt_req.c. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-07-06soc/amd/sabrina,vc/amd/fsp/sabrina: Add UART support for SabrinaJon Murphy
Sabrina previously didn't support UART mapping in psp verstage. Now that it has been enabled, add the relevant uart code here. BUG=b:218709292 TEST=Set serial soft fuse, boot to kernel, check logs Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I591fa69b6e722929839babfff62e9d56c68e1112 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65532 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06soc/qualcomm/ipq40xx: Do resource transitionKyösti Mälkki
Change-Id: I93c16b563c7a4f4c653d2ebfd001170cb0fca82e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-06mb/google/nissa/var/joxer: Add lock gpio pinsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ia087b62904fd515bf73960a188b225f1d49197dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65646 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-06mb/google/nissa: Select Kconfig to perform CSE FW update in ramstageKrishna Prasad Bhat
Alder Lake-N based nissa boards use compressed ME_RW blobs for CSE FW Update. Choose SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE Kconfig to perform CSE FW sync in ramstage. BRANCH=firmware-brya-14505.B TEST=Perform CSE FW upgrade/downgrade on nivviks. Change-Id: I00630096c52434f44914f3ae82ff043ecf77b80d Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65368 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06common/intel/cse: Add function to perform CSE FW update in ramstageKrishna P Bhat D
When compressed ME RW blobs are used for CSE FW update, it has to be loaded into memory to decompress. So perform CSE FW update in ramstage. Alder Lake-N based nissa boards use compressed ME RW blobs to save on SPI flash size. Enable CSE FW update in ramstage. BRANCH=firmware-brya-14505.B TEST=Perform CSE FW update on nivviks and verify upgrade/downgrade works. Change-Id: Ide9471146d186dca11fb020e5006eeaa01442669 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06soc/intel/alderlake: Add check for CSE FW sync in romstageKrishna P Bhat D
Some Alder Lake-N boards will use compressed ME RW blobs to obtain savings on the SPI size (1916KB before compression, ~1132KB after compression). So add an additional check before calling cse_fw_sync() from romstage. When compressed blobs are used, the call to CSE firmware update has to be in post-RAM stages. BRANCH=firmware-brya-14505.B Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087 Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-06mb/google/nissa/var/pujjo: Add lock gpio pinsEric Lai
There is a new ground rule, variant should honor baseboard lock gpios. Thus, lock the gpio which is locked in baseboard. BUG=b:216671701 TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I9f0fcf52b6b7d622e4fd182e007de6401856c7fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65645 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05soc/intel/meteorlake: Enable X2APICSubrata Banik
This patch enables X2APIC to avoid hang-ups due to `Switching from X2APIC to XAPIC mode is not implemented.`  BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP) TEST=Able to enable X2APIC on rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05soc/intel/baytrail,braswell,quark: Drop RES_IN_KIBKyösti Mälkki
Change-Id: I2360a1a79f07ff8466ed01aa7f180d410e019292 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05mb/google/brask/variants/moli: set tcc_offset to 0℃Raihow Shi
Set tcc_offset value to 0 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUG=b:236294162 TEST=emerge-brask coreboot Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I8d4c631e07873923226683c8aa0cf36cb872e2d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-07-05mb/starlabs/labtop/tgl: Nit - minor format changeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I068c6e46d85d869afc72280509a03d5ff682b917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65618 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 10:36:53 +0000