diff options
| author | Reka Norman <rekanorman@google.com> | 2022-07-07 14:49:58 +1000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-08 15:28:41 +0000 |
| commit | b146c7a7c0b1ad78d7171bf88111be93ce233b03 (patch) | |
| tree | 5f1b11c7a76e7680cd5a7a33a9b06dd9271715ed /src | |
| parent | 6297df85d625548ae9ec2f2c1ab8616f4fb11829 (diff) | |
mb/google/nissa: Don't put WLAN into D3cold
On nissa, WLAN should be a wake source, so don't put it into D3cold
during suspend.
BUG=b:233325709
TEST=Wake-on-WLAN works on nereid
Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/nereid/overridetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/xivu/overridetree.cb | 6 |
2 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index 3cc7dc37a2..8dbc1f461a 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -210,12 +210,6 @@ chip soc/intel/alderlake register "wake" = "GPE0_DW1_03" device pci 00.0 on end end - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" - register "srcclk_pin" = "2" - device generic 0 on end - end end device ref pch_espi on chip ec/google/chromeec diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index 3f36594a5b..9268434463 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -188,12 +188,6 @@ chip soc/intel/alderlake register "wake" = "GPE0_DW1_03" device pci 00.0 on end end - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" - register "srcclk_pin" = "2" - device generic 0 on end - end end device ref pch_espi on chip ec/google/chromeec |