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2024-11-07soc/intel/cmn/block/cse: Add API to check the current boot partitionSubrata Banik
This patch introduces an API to check whether CSE is booting from the RW slot. This information can be used to determine if a CSE firmware update is pending, which would help to optimize the boot flow by knowing if any reset is expected due to CSE sync. TEST=Able to build google/brox. Change-Id: I1a63ae9992d83b439a0f995d599ee475f7abd75b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-07soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSIONRonak Kanabar
This patch introduces support for storing the MRC cache based on the MRC version for RPL platforms. This patch selects the MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_RAPTORLAKE is chosen. BUG=b:281846937 TEST=Able to build and boot google/brox and verify MRC version in CBMEM. Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-07drivers/spi/spi_flash: introduce 'spi_flash_cmd_multi'Felix Held
A following patch that adds some support for reading the serial flash discoverable parameters (SFDP) data structures needs to send more than just the one command byte that 'spi_flash_cmd' supports. To be able to do this, introduce the 'spi_flash_cmd_multi' function which supports sending multiple bytes before reading back some bytes. The prototype is added to drivers/spi/spi_flash_internal.h since only other files in the same directory are supposed to be using that function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/84789 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07soc/amd/common/psp/rpmc: bring debug output in line with fmap sectionFelix Held
Call the PSP RPMC NVRAM 'PSP RPMC NVRAM' instead of 'PSP NVRAM' in the debug console output to not be misleading, since the RPMC feature uses the 'PSP_RPMC_NVRAM' fmap section and not the 'PSP_NVRAM' fmap section. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie89dfcfe4b8780f422c222477bb627e03bd3662d Reviewed-on: https://review.coreboot.org/c/coreboot/+/85007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2024-11-07mb/google/rauru: Add new board variant HyliaYang Wu
Add a new Rauru follower 'Hylia'. BRANCH=rauru BUG=b:376357839 TEST=emerge-rauru coreboot chromeos-bootimage Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84924 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-07mb/dell: OptiPlex 3050 Micro port (Intel KabyLake)Mate Kukri
- Boots Linux 6.11 (Debian) - GRUB and SeaBIOS payloads work - SMSC SCH5553 SIO/EC + Serial port works + PWM fan control works - Realtek Gigabit LAN works - WiFi slot works - NVMe SSD slot works - Extra: LPSS UART0 + Stock FW sets undocumented power gating bit, RTC battery needs to be pulled for it to work. + Signals exposed on test points on the back of the board. FIXME: add documentation about this - Needs 'deguard' to bypass BootGuard + See https://review.coreboot.org/admin/repos/deguard,general - Audio works - All USB ports work - Currently limited to the Micro form factor, but others are very similar - HDA verbs and VBT by Leah Rowe Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82053 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-11-07soc/intel/xeon_sp: Add acpigen_write_PRT_pre_routedLu, Pen-ChunX
acpigen_write_PRT_pre_routed writes _PRT covering all direct subordinate child devices based on interrupt line/pin info from their PCI configuration spaces. It is required that IRQ routing and PCI configuration space update to be done ahead of time. TEST=Build and boot on intel/archercity CRB Change-Id: Ic54888f76d2ec9804442bec5aec54267d9a16d7c Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82253 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2024-11-07soc/mediatek/common: Use write32p and read32p for trackerYidi Lin
TEST=emerge-geralt coreboot Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84959 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07soc/mediatek/common: Refactor `struct tracker`Yidi Lin
Rather than using a static array size for the `offset` variable, use a pointer named `offsets` that points to a dynamically allocated array. A separate variable called `offset_size` stores the size of this array. TEST=emerge-corsola coreboot && emerge-geralt coreboot Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-11-07mb/cwwk/ald: Remove DIMM_MAXArthur Heymans
For ADL DIMM_MAX is a soc property and not a mainboard property. Change-Id: I834b631ffb9b7b2272ec631122de61136e55651a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84207 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07mb/google/nissa/var/rull: Add Fn key scancodeRui Zhou
The Fn key on rull emits a scancode of 94 (0x5e). BUG=b:372211281 TEST=Flash rull, boot to Linux kernel, and verify that KEY_FN is generated when pressed using `evtest`. Change-Id: Idb02d7013fa78233abff556bc6fa1d224c434338 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-07mb/google/nissa/var/rull: Change padbased_override to rtd3 of wifiRui Zhou
The previous method made cnvi wifi6 configuration cumbersome and unusable. And delete unused pins. We abandoned the fw_config judgment method and changed to the better rtd3. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. wifi7&wifi6 function is normal Change-Id: Ia95dc9f6b707db63840de9b15b38bdaea48ea192 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85000 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-07mb/google/nissa/var/rull: add touchpad init config of Synaptics&PIXARTRui Zhou
Add Synaptics&PIXART init cpnfig, enable touchpad function BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. touchpad function normal Change-Id: Iacf09cd46d4a97fb79f91043c84452f76689462f Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84999 Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-07mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3Rui Zhou
The previous GPIO config will cause the SSD device to not be recognized. Based on schematics NB7559_MB_SCH_V1_2024_1010.pdf. So we adjust the position of the enable and reset pins. BUG=b:374629673 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: Idb36f67206450612655cb3efd3cce240475ef3ab Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-07mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3HFabian Groffen
This board is based off ga-b75m-d3h, which uses the same SuperIO chip. It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with 2 SATA3 ports next to the 4 SATA2 ports. Flashing notes: These boards come with dual-BIOS feature. This is set of two unremovable what appears to be identical chips marked M_BIOS and B_BIOS. Flash the B_BIOS chip, and boot the system. Ensure you have a payload and setup ready to boot a Linux system with iomem=relaxed or similar. Immediately use flashrom -p internal to flash the same firmware again. If you skip this step your next boot will show weird exception traces in either coreboot or your payload. Flashing from there via the chip is very difficult (you have to try many times in order to get a booting run), which can all be remedied by doing a flash from internal. I suppose the dual-BIOS feature is somewhat in the way here. Tested with: - CPU Core i7-3770S - RAM single bank 4GB CL11, two banks 4+4GB CL11 - OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72) Working: - GRUB2 payload - Intel ME stripped - Integrated graphics with libgfxinit - (boot from) SATA2, SATA3 ports - Rear and mainboard connector USB ports, supporting boot - Atheros GbE NIC - 2.0 channel audio via lineout jack output - ACPI (power button triggers OS events) - S3 suspend/resume - PWM FAN control, FAN speed readings - Temperature sensor readings Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Reviewed-on: https://review.coreboot.org/c/coreboot/+/77046 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07mb/asrock: Add Asrock Industrial IMB-1222 motherboardMaxim Polyakov
ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX motherboard [1]. Working: - Dual Channel DDR4 2933/2666/2400 MHz; - Intel UHD Graphics (VGA Option ROM, libgfxinit, GOP driver); - DP (both), HDMI; - PCIe x16 Slot (Gen3); - SATA ports; - USB 2.0 ports; - USB 3.2 ports; - M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi); - M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1); - M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3); - LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps; - LAN2 Intel I219LM, 10/100/1000 Mbps; - Realtek ALC887 HD Audio (line-out, mic-in); - COM 1/2/3/4 ports; - onboard speaker; - HWM/FANs control (fintek f81966); - S3 suspend and wake; - TPM; - disabling ME with me_cleaner [2]; Payload: - Linux as payload; - LinuxBoot; - SeaBIOS; - edk2 [3]. Bootable OS: - Ubuntu 22.04 (Linux 6.5.0-15-generic); - Ubuntu 24.04 (Linux 6.8.0-41-generic); - Microsoft Windows 10 Pro (10.0.19045.4780, 22H2 2022); - Andoid 13, Bliss OS x86_64 (16.9.7, Linux 6.1.112-gloria-xanmod1). Unknown/untested: - USB3.0 in M.2 Key-B 3042/3052 slot; - eDP/LVDS; - PCIe riser cards; - SPDIF. There is no schematic/boardview, reverse engineering only. This port is based on system76/bonw14 because it has a similar topology. [1] https://web.archive.org/web/20220924171403/https:// www.asrockind.com/en-gb/IMB-1222 [2] XutaxKamay's me_cleaner fork, https://github.com/XutaxKamay/me_cleaner, v1.2-9-gf20532d [3] MrChromebox's edk2 fork, https://github.com/mrchromebox/edk2 uefipayload_2408 branch Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83107 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/intel/alderlake: Fix uninitialized usb_cfg pointerKarthikeyan Ramasubramanian
This patch addresses uninitialized usb_cfg pointer warning which is also an error - src/soc/intel/alderlake/fsp_params.c:936:48: error: 'usb_cfg' may be used uninitialized in this function [-Werror=maybe-uninitialized] BUG=None TEST=./util/abuild/abuild Change-Id: I764fed561dfe2a571f3404fe505997edd7aa5ff7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84939 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/brox: Hint romstage init about upcoming resetKarthikeyan Ramasubramanian
Add support for the mainboard to check for any potential firmware component update and hence the assosicated reset. This indication can be used to avoid any redundant resets during the boot flow. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Ensure that the hints are provided correctly and 2 redundant resets are filtered out. Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-06ec/google/chromeec: Fix typo in google_chromeec_get_pd_chip_infoKarthikeyan Ramasubramanian
An unintended suffix got added in google_chromeec_get_pd_chip_info. Fix the typo by removing that suffix. BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I76048ec1ed6b4387098fecf35ccc5b1c1742abb0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-06mb/google/brox: Reduce PL4 only for battery disconnected scenarioSowmya Aralguppe
This patch reduces PL4 only for no battery condition i.e. when battery is disconnected or not physically present. BUG=b:377305625 TEST=Build Brox and boot when the battery is disconnected Change-Id: I59a1028ce9cd3a6cf98f865d9c085a64f391f201 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06vc/intel/fsp/raptorlake: Add FspProducerDataHeader.h headerRonak Kanabar
This patch is to add FspProducerDataHeader.h header file to support MRC version Info in RPL. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: Iaf7983fbe8f103d9f51065cd160177e2bde7fd3d Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06soc/intel/alderlake: select UDK_202305_BINDING for RPLRonak Kanabar
RPL FSP v5311 uses 202305 Edk2. Select UDK_202305_BINDING Kconfig for RPL SoC. BUG=b:281846937 TEST=Able to build and boot google/brox. Change-Id: I8dcc7d85cddadcce148ded5a81658253e8598413 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84722 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-06vendorcode/intel: Add edk2-stable202305 supportRonak Kanabar
Add edk2-stable202305 support for MTL and RPL FSPs. This patch includes (edk2/edk2-stable202302) all required headers for edk2-stable202302 EDK2 tag from EDK2 github project using below command: git clone -b edk2-stable202305 https://github.com/tianocore/edk2.git commit hash: ba91d0292e593df8528b66f99c1b0b14fadc8e16 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Add following fixes from older Edk2 060492ecd2 Safe guard enum macro in SmBios.h 2bf9599cf1 Use fixed size struct elements cf4c6fd225 Remove FSPM_ARCH_UPD config guard dc781d3a83 Define FSP_SIG macro for FSP 2.x compatibility d045074b91 Remove wchar_t asserts Change-Id: I96f0d0e393d31b325f9e42e3494556a2f6e1228e Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8Hualin Wei
Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:366383364 TEST=Tested on Awasuki with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-06soc/intel/jasperlake: add support for RP LTR mechanismLawrence Chang
Reserve Root Port LTR mechanism in FSP, in case some devices need to optimize LTR. BUG=366383364 TEST=Tested on Awasuki with RTL8852BE use lspci -xxx to get PCIE config space dump, and LTR Mechanism Enable bit is offset 68h[10]. 00:1c.0 PCI bridge: Intel Corporation Device 4dbf (rev 01) 00: 86 80 bf 4d 07 05 10 00 01 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 20 20 00 20 20: c0 7f c0 7f f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 12 00 40: 10 80 42 01 00 80 00 00 00 00 10 00 13 4c 72 08 50: 43 00 11 70 00 b2 3c 00 00 00 40 01 08 00 00 00 60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00 70: 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00 90: 0d a0 00 00 86 80 bf 4d 00 00 00 00 00 00 00 00 a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 10 00 07 42 18 01 40 08 00 9e 09 00 00 00 00 e0: 00 03 e3 00 00 00 00 00 16 00 10 00 00 00 00 00 f0: 50 01 00 00 00 00 00 4c b5 0f 02 01 04 00 00 84 Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Signed-off-by: Lawrence Chang <lawrence.chang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84866 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Ruth <druth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/dedede/var/drawcia: Update ext_vr for board version > 0xbRobert Chen
ext_vr_update should be run after board version 0xb, but skipped by return. Drawper LTE board version was set after 0x9, but there are more board added after that. Specific Drawper board version as 0xa, 0xb and 0xf. BUG=b:376828839 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage and test on DUTs. Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-11-06soc/intel/meteorlake: Remove SOC_INTEL_GFX_MBUS_JOIN configSubrata Banik
This patch removes the SOC_INTEL_GFX_MBUS_JOIN configuration option. Support for fast modeset joining has been added to the mainline i915 kernel driver (https://patchwork.freedesktop.org/series/130480/), making this coreboot-specific workaround unnecessary. BUG=b:291885733 TEST=Successful build and boot of google/screebo with single and dual displays, no redundant boot splash. Change-Id: Ifb0416df53a453ce16815f9fd52ec6b53fade5e2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81034 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paz Zcharya <pazz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/intel/coffeelake_rvp/cml_u: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. As I do not own this board, I cannot test whether is change is "functionally correct". However, I believe it is more likely that the original authors forgot to update the verb table size, rather than them adding additional verb data which was not meant to be used. TEST=`_Static_assert()` mentioned above does not fail anymore. Change-Id: I8df44e056bc841bfb344749ba214e6fb71a1955b Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84487 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/nissa/var/glassway: Add initial LTE related settingsDaniel Peng
1. Add DB_1C_LTE 4 on DB_USB fw_config. 2. Implement WWAN power sequencing. 3. Disable LTE-related GPIOs based on fw_config. 4. Add I2C SX9324 (P-sensor) support. Refer Schematic file: CA31AC_R10_MB_SUB_240903A_P.pdf BUG=b:374666995 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Confirm the device node i2c-STH9324:00 created correctly, and command for # i2cdump -f -y 11 0x28 is workable. Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84925 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-11-06soc/mediatek/mt8196: Disable irq2axi featureRunyang Chen
Irq2axi translates wire-based interrupt into message signal interrupt. Since MT8196 uses legacy wire-based interrupt, this feature needs to be disabled. If the interrupt is not handled, it will cause the system fail to boot. TEST=Build pass, check irq2axi_disable log and the interrupt can be correctly handled by checking /proc/interrupts. BUG=b:317009620 Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84896 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06soc/mediatek/mt8196: Enable EARLY_MMU_INITYidi Lin
The boot time is improved by 58ms in bootblock. (78ms -> 20m) BUG=b:361729697 TEST=check cbmem Change-Id: I27ce378ba8e3744cfb3921835e34b32bbba991cb Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84897 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/rauru: Complete PCIe reset in romstageYidi Lin
De-assert PERST# at romstage to reduce the waiting time in ramstage. BUG=b:361728592 TEST=The boot time improves 62ms Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-11-06mb/cwwk/adl/devicetree: correct PCIe RP 12 clock configurationFelix Held
Looking at Intel document 759603 revision 001, Alder Lake N only has 5 PCIe clock outputs and clock request pins. I only have the version 2 of this board which has a significantly different USB port configuration to version 1, but there the Ethernet controller on RP 11 and the E key m.2 slot on RP 12 share the last PCIe clock output. The on-board TUBF0304 clock buffer chip takes the clock output form the last PCH PCIe clock generator output and drives the clock inputs of both the last Ethernet chip and the E key m.2 slot. Since the last clock output is always active, since RP 11 has the PCIE_RP_CLK_REQ_UNUSED flag set, using the non-existent clock output and request for RP 12 didn't break things. ASPM L0s might still work though, since that one doesn't involve switching off the PCIe reference clock, but haven't tested that yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I103f7c3fe0b806f5c0a5202b8221f522a4b1c378 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83911 Reviewed-by: coreboot org <coreboot.org@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05mb/lenovo: Add ThinkCentre M920q (Coffee Lake)Maciej Pijanowski
It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here. Works: - Serial adapter from daughter board (COM1 connector) - USB ports front and back - USB-C port (charging, data) - HDMI - Ethernet - SATA - NVMe - internal speaker - TPM2.0 - PCIe x8 port (x8 riser tested, x4 not) Does not work: - front audio jacks Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80609 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05soc/amd/common/psp_smi_flash: refactor SPI controller busy checkFelix Held
Since the functions that call 'spi_controller_available' end up checking if the SPI controller is busy, refactor the function into 'spi_controller_busy' to simplify the logic on the caller's side. Also move printing of the notice that the SPI controller is busy to 'spi_controller_busy' to not have that duplicated in caller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibc21ab6eacf07c4adffdb4658142c2f9dfcbf2a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84920 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05soc/amd/common/psp_smi_flash: factor out get_flash_deviceFelix Held
Since the RPMC-related functions will only need the spi_flash struct, but not the region_device struct of the store region corresponding to the 'target_nv_id', factor out 'get_flash_device' from 'find_psp_spi_flash_device_region'. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia99d3454df2c1c4182c193da7de1bbb4eef18313 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84905 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ana Carolina Cabral
2024-11-05soc/intel/alderlake: Disable UFS controllers only on S5 resumeSubrata Banik
Disable UFS controllers during romstage initialization only when resuming from S5 (full power off). On warm reboot, the UFS controllers are already disabled by the previous boot cycle, so disabling them again is unnecessary. TEST=Able to ensure UFS controller is already disabled in warm reboot path and not causing any problem during S0ix cycle test. Change-Id: Ia27d2156a002cef032d5f57d212cf4eb520b3bdf Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-11-05soc/intel/meteorlake: Disable eSOL for Ovis/DekuSubrata Banik
Disable the `FSP_UGOP_EARLY_SIGN_OF_LIFE` option (eSOL) for the Ovis baseboard. eSOL currently only supports display output over eDP and HDMI. Ovis/Deku exclusively use Type-C for display, and eSOL cannot render output over Type-C during early boot because it depends on Type-C firmware loaded in a later stage. TEST=Able to build and boot google/deku. Change-Id: I5ddbd340f667b1631a42d130a793f0b1831aa0ba Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-11-05mb/google/nissa/var/glassway: Add touch screen ILIT2901 supportDaniel Peng
1. Extend 1 bit [34] for the TOUCHSCREEN_SOURCE. SSFC range for TOUCHSCREEN_SOURCE is bit[32:34]. 2. Touchscreen panel: MUTTO A153728S1Y, and set TOUCHSCREEN_ILIT2901 to value "4" 3. Datasheet: #153728S1V1.0 SPEC_20240923.pdf BUG=b:375986645 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Confirm command evtest and touchscreen function is workable. Change-Id: I6e13c948edca5a894e1a00a1954f0f88c4a079cf Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84894 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05ec/google/chromeec: Add API to get PD Chip infoKarthikeyan Ramasubramanian
Add API to get Power Delivery (PD) Chip info which includes vendor ID, product ID and firmware version(if any). BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I4cc4493ac64d44076877fee633488c95cd09807e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-11-04mb/google/fizz: Fix USB port defintionsMatt DeVillier
commit 6c83a71b0a80 ("skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope") not only moved the USB port definitions under the XHCI device reference, but also combined multiple register definitions. In doing so, it broke the inheritance from the baseboard, since the variant overridetree registers now replaced the entire usb2_ports/usb3_ports structs, rather than replacing individual array elements therein. This resulted in any USB ports inherited from the baseboard and not overridden by the variant being non-functional as they were not included in the resulting combined devicetree. To fix this, return to overriding individual array elements in the usb2/3_ports structs. TEST=build/boot google/fizz/var/karma. Verify all USB ports present and functional. Verify mainboard/static.c in built shows all ports. Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84955 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-04mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIOSukumar Ghorai
This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as NC to enable S0ix low power entry. TEST=Build fatcat and check the platform boots without an issue. Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84957 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2024-11-04mb/google/fatcat: Disable package c-state auto-demotionSukumar Ghorai
Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. TEST=Build fatcat and check the platform boots without an issue. Change-Id: I01f2cb8ac1093ae98cc076e35ad1924baa53aa59 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-11-04ec/google/chromeec: Add is_battery_present()Sowmya Aralguppe
This patch adds is_battery_present() to check if the battery is physically present BUG=b:335046538,b:329722827 TEST=Build Brox and check is_battery_present returns the correct battery status. Change-Id: Ie49ed8f6d8b0fa59ec0e7b06efea9cac4d253957 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83735 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-11-04mb/google/dedede/var/awasuki: Tune I2C touchpad for freq and THWei Hualin
1. Modify the I2C frequency of the touchpad between 380 Khz and 400 Khz to meet the spec. 2. Increase clk the time of high (TH) to greater than 600ns. Before: I2C0 - 420KHz TH - 557ns After: I2C0 - 398Khz TH - 630ns BUG=b:351968527 TEST=Check that the wave form meets the spec. Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84898 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2024-11-04mb/google/fatcat/var/francka: Generate RAM ID for MT62F2G32D4DS-020 WT:FAmanda Huang
Add Micron part MT62F2G32D4DS-020 WT:F only for Francka. DRAM Part Name ID to assign MT62F2G32D4DS-020 WT:F 0 (0000) BUG=b:373394046 TEST=emerge-fatcat coreboot Change-Id: I2de56c8c7a028edefbd3dc53f8b1e26dee3286f7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84781 Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-04soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcsYu-Ping Wu
The size of the inner array of the 2-dimensional array pad_funcs should be 4 instead of SPI_BUS_NUMBER (6). This bug leads to two extra gpio_set_mode() calls with unexpected GPIOs. Inspecting spi.o, the data immediately after the .rodata.pad_funcs section is .rodata.spi_ctrlr_bus_map, with the following data: 00000428 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00000438 00 00 00 00 00 00 00 00 ... This is equivalent to the following calls: gpio_set_mode(GPIO(GPIO05), 0); gpio_set_mode(GPIO(GPIO00), 0); The second call is already included in the pad_funcs array, so the first call is the only practical impact of this bug. Change-Id: I9c44f09b3cdadbbf039b95efca7144f213672092 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-11-03soc/intel/alderlake: Do lazy reset after disabling UFSKarthikeyan Ramasubramanian
If the mainboard expects upcoming reset, then skip the reset after disabling UFS. This will reduce the number of resets during firmware update. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Perform a firmware update and confirm that the number of reset is reduced by 2 resets. Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84935 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-11-02mb/google/fatcat: Add devicetree for MAX98357A codecAnil Kumar
Update device tree to support speaker o/p on MAX98357A AIC. BUG=b:357011633 TEST=build coreboot image and test audio playback on Google/Fatcat board. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I20de87f673e947f0e2332b818ebca01c0fa5e200 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84888 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-01mb/google/brya/var/banshee: select SOC_INTEL_RAPTORLAKEIan Feng
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as banshee is using a converged firmware image. This effort also helps to save banshee boot time by 80-100ms as RPL FSP is better optimized. Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which saves 10ms of the boot time. BUG=b:358254132 TEST=Able to build and boot google/banshee. cold boot time w/o this CL ``` Total Time: 1,399,888 ``` cold boot time w/ this CL ``` Total Time: 1,295,334 ``` Change-Id: If22e07a4c1b35fe1d060ca523743c6c503937287 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2024-11-01mb/google/nissa/var/riven: Increase the VccIn Aux Imon IccMax to 30ADavid Wu
From power team's recommendation, increase the VccIn Aux Imon IccMax to 30A to meet HW settings. BUG=b:376306118 TEST=Build firmware and check the value is changing as expected. Paste the firmware log. [SPEW ] VccInAuxImonIccImax= 0x78 [SPEW ] (MAILBOX) VccInAuxImonIccImax = 120 (1/4 Amp) [INFO ] Override VccInAuxImonIccImax = 120 Change-Id: I71020c2f631cb517a52d4bb65e35277eb731ced7 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-31mb/google/rauru: Pre-initialize PCIe at the bootblock stageJianjun Wang
According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. Right now we simply wait for 100ms in ramstage for that. To speed up the boot time, pre-initialize PCIe by asserting PERST# earlier in the bootblock stage. The pre-initialization time is stored in the early init data region, so that the PCIe initialization in ramstage could make sure the required 100ms delay is still reached. This pre-initialization will speed up the boot time by 100ms on rauru. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-10-31mb/google/nissa/var/teliks: Match VBT with SSFCzengqinghong
We want to configure different VBT timings for panels of different sizes and distinguish them through SSFC. We select the reserved bit 6 of SSFC as the flag bit. When using a 12-inch panel, set this bit to 0; when using an 11-inch panel, set this bit to 1. Without splitting, the platform_BootPerf test will fail. BUG=b:374428465 TEST= 1. can match VBT with SSFC -When SSFC is set to 0x40: $ cat /sys/firmware/log | grep vbt Bit 6 of SSFC is 1, use vbt-teliks_panel_11_inch.bin CBFS: Found 'vbt-teliks_panel_11_inch.bin' @0x1c6140 size 0x50f in mcache @0x76adda14 -When SSFC is set to 0x0: $ cat /sys/firmware/log | grep vbt Bit 6 of SSFC is 0, use vbt-teliks.bin CBFS: Found 'vbt-teliks.bin' @0x1c5bc0 size 0x50e in mcache @0x76add9b0 2. can pass platform_BootPerf test The platform_BootPerf time measured for all SKUs is less than 1.55s. Change-Id: Ia8fb45aede5ead4826d983760506c366a70643ee Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84871 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-31mb/google/fatcat: Adjust EC host command range for microchip ECSubrata Banik
This commit adjusts the EC host command range for the Fatcat board to 0x800-0x807 & 0x200-0x20f. This change is necessary because the microchip EC used on the Fatcat board has a smaller host command range than the ITE/Nuvoton ECs used on other Fatcat variants. The `gen1_dec` register in the devicetree is updated to reflect this change. As per boot log, the `gen1_dec` aka offset 0x84, base address is 800 and size is 8 bytes. AP FW Boot log: [SPEW] PCI: 00:00:1f.0 resource base 800 size 8 align 0 gran 0 limit 0 flags c0000100 index 84 BUG=b:376207365 TEST=Able to build and boot google/fatcat w/o any error. without this patch: [SPEW ] LPC: Trying to open IO window from 800 size 8 [ERROR] LPC: Cannot open IO window: 800 size 8 [ERROR] No more IO windows with this patch: [SPEW ] LPC: Trying to open IO window from 800 size 8 Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84919 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
2024-10-30soc/intel/pantherlake: Populate and pass DRAM info for SMBIOSSubrata Banik
This patch implements the `save_dimm_info()` API to populate and pass DRAM-related information to the next stage. This information is used to generate the SMBIOS memory table, providing details about installed DIMMs. This addresses the issue where SMBIOS lacked detailed DIMM information. Verified that `dmidecode` correctly dumps the DIMM information from the SMBIOS table after this change. BUG=b:376103463 TEST=Built and booted successfully. Verified DIMM info in SMBIOS using `dmidecode`. > dmidecode -t 17 ``` Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ... ... Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-3-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-3-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ``` Change-Id: I3b942610272de401589ee0463de9cd0985974774 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-10-30soc/intel/pantherlake: Add ACPI names for missing devicesSubrata Banik
This patch adds ACPI names for the following devices: - THC0 (PCI: 00:10.0) - THC1 (PCI: 00:10.1) - SRAM (PCI: 00:14.2) - FSPI (PCI: 00:1f.5) TEST=Able to build and boot google/fatcat without any error. w/o this patch: [ERROR] Missing ACPI Name for PCI: 00:10.0 [ERROR] Missing ACPI Name for PCI: 00:10.1 [ERROR] Missing ACPI Name for PCI: 00:14.2 [ERROR] Missing ACPI Name for PCI: 00:1f.5 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84910 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-30soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0Subrata Banik
This change sets the SMBUS device to min sleep state D0 in the ACPI sleep state table. TEST=Able to build and boot google/fatcat. w/o this patch: [WARN ] Unknown min d_state for PCI: 00:1f.4 w/ this patch: No Error or Warning. Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84909 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-30mb/google/fatcat: Define EC_SYNC_IRQ and GPIO_PCH_WP for variantsSubrata Banik
This commit defines the EC_SYNC_IRQ and GPIO_PCH_WP macros for different Fatcat variants. The EC_SYNC_IRQ macro is used for tight timestamps and wake support, while the GPIO_PCH_WP macro is used for the WP signal to the PCH. These macros were previously undefined or incorrectly defined for some variants. This commit fixes these issues and ensures that the macros are defined correctly for all variants. Specifically, this commit: - Defines EC_SYNC_IRQ and GPIO_PCH_WP for Fatcat Nuvo and Fatcat ITE. - Defines EC_SYNC_IRQ as 0 (not connected) for Fatcat. - Defines GPIO_PCH_WP as GPP_D02 for Fatcat. - Leaves EC_SYNC_IRQ and GPIO_PCH_WP as 0 (TODO) for Francka. TEST=Able to build and boot google/fatcat. w/o this patch: ``` cros_ec_lpcs GOOG0004:00: couldn't retrieve IRQ number (-22) cros_ec_lpcs GOOG0004:00: probe with driver cros_ec_lpcs failed with error -22 ``` w/ this patch: ``` cros_ec_lpcs GOOG0004:00: Chrome EC device registered ``` Change-Id: I9bd248496f08869c08cf6daafeed6584d0b166b7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-30mb/google/fatcat: Ensure RW_SECTION_B at 16MB boundary for debug FMDSubrata Banik
This patch updates the flash map layout to guarantee that the RW_SECTION_B section starts at the 16MB boundary. Additionally, fix typo in flash descriptor comment, where comment incorrectly referred to "MTL" instead of "PTL". TEST=Successfully builds google/fatcat. Change-Id: Ia6dba611fba50f9694a75670d954a4630cde4d70 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84899 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-29tree: Fix cast an object of type 'nullptr_t' to 'uintptr_t' errorElyes Haouas
This to fix the error when using C23: cannot cast an object of type 'nullptr_t' to 'uintptr_t' (aka 'unsigned long') return (uintptr_t)NULL; ^ Change-Id: Ibdc8794513a508fc61a5046692f854183c36b781 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-10-28uncore_acpi: Clean up resource codePatrick Rudolph
Use the resource size to determine Vtd BAR size and drop the code to calculate the Vtd BAR size. While on it do not truncate the resource address to 32-bit, since the DMAR entry is 64-bit wide anyway. TEST: Booted on intel/archercity_crb Change-Id: Ibaadc25c44345ba2eb9e6f75989d32b43d00d7a5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-28soc/intel/xeon_sp: Fix iiostack.aslPatrick Rudolph
Align DSDT names with SSDT naming scheme, as provided by iio_domain_set_acpi_name() and hide unused devices by implementing the _STA method as done on newer platforms. Change-Id: I8488907f28a78a6f71046dba54ba9cbd4b0652eb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-28soc/intel/xeon_sp: Add SAD PCI driverPatrick Rudolph
Get rid of some helper functions by properly using a pci_driver. Configure SAD if necessary and lock SAD if necessary in the newly added SAD PCI driver. This allows to drop lock_pam0123(), unlock_pam_regions() and socket0_get_ubox_busno(). - Fixes SAD instance on secondary sockets not decoding the C-F segments as DRAM, which would prevent those sockets to access the ACPI/SMBIOS table anchor - Adds PCI multi segment support (SKX and CPX only, other were working properly already) - Moves locking of PAM0123_CSR and PAM456_CSR from SoC to driver code Change-Id: I167b6ce48631fe3f97359ee33704f52ca854dbd1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84794 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28lib/smbios: Improve Type9Patrick Rudolph
Set characteristics 1 based on slot type and scan PCI capabilities to update the characteristics 2 field in SMBIOS type 9 accordingly. Change-Id: If96e0381b10c25cf73b3797a0f02a40dc933993e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2024-10-28pci: Add method to read PME capabilityPatrick Rudolph
Add a helper method to read the PME capability. Will be used in the following commit. Change-Id: Id1fdc98c9ce86d3ddf8056bb609afc58008cf2e9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84793 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-28soc/amd/common/psp: add RPMC provisioning codeFelix Held
Add the code to request the provisioning of the RPMC root key from the PSP. When RPMC hasn't already been provisioned enabled and the PSP has detected a SPI flash chip that both supports RPMC and has monotonic counters that can still be provisioned, we send the PSP mailbox command to request the RPMC provisioning and then reset the system, so the PSP can do the actual provisioning. TEST=On an out of tree AMD reference board using the Cezanne SoC code, provisioning RPMC works as expected when selecting the corresponding PERFORM_RPMC_PROVISIONING Kconfig option: 1st boot to initiate the RPMC provisioning: [DEBUG] PSP: Querying PSP capabilities...OK [DEBUG] PSP: Querying HSTI state...OK [SPEW ] RPMC isn't provisioned [SPEW ] SPI flash supports RPMC [SPEW ] RPMC revision 0 [SPEW ] PSP NVRAM isn't healthy [SPEW ] PSP NVRAM is using RPMC protection [SPEW ] SPI flash RPMC counter 0 can still be provisioned [SPEW ] SPI flash RPMC counter 1 can still be provisioned [SPEW ] SPI flash RPMC counter 2 can still be provisioned [SPEW ] SPI flash RPMC counter 3 can still be provisioned [SPEW ] SPI flash RPMC counter 0 is in use [SPEW ] SPI flash RPMC counter 1 is not in use [SPEW ] SPI flash RPMC counter 2 is not in use [SPEW ] SPI flash RPMC counter 3 is not in use [SPEW ] SoC RPMC slot 0 can still be provisioned [SPEW ] SoC RPMC slot 1 can still be provisioned [SPEW ] SoC RPMC slot 2 can still be provisioned [SPEW ] SoC RPMC slot 3 can still be provisioned [DEBUG] RPMC: perform fusing using RPMC counter address 0 [DEBUG] OK [NOTE ] RPMC: Rebooting [INFO ] warm_reset() called! 2nd boot after the provisioning is done: [DEBUG] PSP: Querying PSP capabilities...OK [DEBUG] PSP: Querying HSTI state...OK [SPEW ] RPMC is provisioned [SPEW ] SPI flash supports RPMC [SPEW ] RPMC revision 0 [SPEW ] PSP NVRAM isn't healthy [SPEW ] PSP NVRAM is using RPMC protection [SPEW ] SPI flash RPMC counter 0 has already been provisioned [SPEW ] SPI flash RPMC counter 1 can still be provisioned [SPEW ] SPI flash RPMC counter 2 can still be provisioned [SPEW ] SPI flash RPMC counter 3 can still be provisioned [SPEW ] SPI flash RPMC counter 0 is in use [SPEW ] SPI flash RPMC counter 1 is not in use [SPEW ] SPI flash RPMC counter 2 is not in use [SPEW ] SPI flash RPMC counter 3 is not in use [SPEW ] SoC RPMC slot 0 has already been provisioned [SPEW ] SoC RPMC slot 1 can still be provisioned [SPEW ] SoC RPMC slot 2 can still be provisioned [SPEW ] SoC RPMC slot 3 can still be provisioned Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7760c0bf7618ca60ef160329d0110ac8109032a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84707 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/amd/common/psp: add code for reporting RPMC statusFelix Held
Add the code to query the status of the replay-protected monotonic counter (RPMC) infrastructure from the PSP and display it in a decoded form. Certain SPI flash chips have 4 32-bit monotonic counters in addition to the actual flash storage. During the RPMC root key provisioning process, which is done at the end of manufacturing, a 256 bit RPMC root key is generated by the PSP and programmed into both SoC fuses and the RPMC SPI flash chip. After that, commands to read or increment the monotonic counters can be sent to the SPI flash which are protected by a HMAC-SHA-256 signature using a key derived from the provisioned RPMC root key. The code to do the RPMC provisioning is added in a follow-up patch. TEST=On an out of tree AMD reference board using the Cezanne SoC code and with the SOC_AMD_COMMON_BLOCK_PSP_RPMC Kconfig option selected, the newly added code prints this on the console after the provisioning was done: [DEBUG] PSP: Querying PSP capabilities...OK [DEBUG] PSP: Querying HSTI state...OK [SPEW ] RPMC is provisioned [SPEW ] SPI flash supports RPMC [SPEW ] RPMC revision 0 [SPEW ] PSP NVRAM isn't healthy [SPEW ] PSP NVRAM is using RPMC protection [SPEW ] SPI flash RPMC counter 0 has already been provisioned [SPEW ] SPI flash RPMC counter 1 can still be provisioned [SPEW ] SPI flash RPMC counter 2 can still be provisioned [SPEW ] SPI flash RPMC counter 3 can still be provisioned [SPEW ] SPI flash RPMC counter 0 is in use [SPEW ] SPI flash RPMC counter 1 is not in use [SPEW ] SPI flash RPMC counter 2 is not in use [SPEW ] SPI flash RPMC counter 3 is not in use [SPEW ] SoC RPMC slot 0 has already been provisioned [SPEW ] SoC RPMC slot 1 can still be provisioned [SPEW ] SoC RPMC slot 2 can still be provisioned [SPEW ] SoC RPMC slot 3 can still be provisioned Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I498eec58189da710b725ac6575c68ba7ab0bcc43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84706 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/amd/common/block/psp: fix logic bug in psp_get_* functionsFelix Held
The functions psp_get_ftpm_capabilties, psp_get_hsti_state, and psp_get_psp_capabilities which were added in commit 5e7ab1a23346 ("soc/amd/common/psp: add helper functions to retrieve capability bits") have a bug in the 'cmd_status' error handling logic. In case of an error, 'cmd_status' is non-zero, while the check somehow expected the opposite. Fix the bug by returning an error if 'cmd_status' is non-zero. Change-Id: Iafcd185ec4a8a4c0e463b0ac5bac3ef78a0af305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84836 Reviewed-by: Ana Carolina Cabral Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-10-28mb/google/nissa/var/telith: Modify touchscreen form ILITEK to ELANKun Liu
When creating variant, it was copied from teliks, and according to the requirements of telith project, update the override devicetree to use ELAN touchscreen. BUG=b:373510302 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power on proto board successfully 3. touchscreen is functional Change-Id: If0da85a38f3a68b6f50cfd096a628174b313fcc9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84865 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-28mb/google/brya: Create rull variantRui Zhou
Create the rull variant of the nissa reference board by copying the template files to a new directory named for the variant. And based on schematics NB7559_MB_SCH_V1_2024_1010.pdf update devicetree settings. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=b:374673463 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_RULL Change-Id: If48273f3e9db69507b41ea0313916d94ecabe309 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-10-28mb/google/fatcat/var/fatcat: Enable iGPU display using FW_CONFIGSubrata Banik
This change enables the integrated GPU (iGPU) display on the Fatcat board based on the FW_CONFIG setting (specifically the DISPLAY bit). By conditionally probing the display based on FW_CONFIG, the iGPU is dynamically enabled or disabled according to the SKU configuration. TEST=Verified display functionality on Fatcat with the iGPU: > cbi set 6 0x58A814 4 (DISPLAY_ABSENT): - lspci does not list the iGPU. - No display output, but the device boots to the OS (verified via console). > cbi set 6 0x5CA814 4 (DISPLAY_PRESENT): - lspci lists the iGPU. - Display output is functional, showing firmware and OS UI. Change-Id: I5762adf5ec8a86a00c16544670cb2f998055bd35 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84877 Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-10-28mb/google/fatcat: Remove redundant iGPU device entrySubrata Banik
The iGPU device is enabled by default in the Pantherlake chipset configuration. Remove the redundant device entry in the Fatcat devicetree. This change ensures that the iGPU remains enabled without explicit configuration in the board-specific devicetree. TEST=Able to build google/fatcat and able to see firmware and OS display/UI. Change-Id: I9a2ec9b47acb389f5bb6b30e61352aaefa327328 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84876 Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-10-28mb/google/rauru: Add PCIe domain supportJianjun Wang
Add PCIe domain support. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I3e06dfaf79924cd5352348afaa526fc7dedbb540 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84700 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/mediatek/mt8196: Enable PCIe supportJianjun Wang
Enable PCIe support for mt8196. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I9c0aaa1c6da8c247b319e7ed2317dd871e276461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84698 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28mb/google/rauru: Add mainboard_needs_pcie_initJianjun Wang
Add a trivial mainboard_needs_pcie_init implementation that always return true. For now, the storage types of rauru SKUs are still unknown. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I6b4f08e15f62da18aa37226075894f2827a9e7ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/84697 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28soc/mediatek/mt8196: Add PCIe driver and early init supportJianjun Wang
Add PCIe driver for MT8196 platform. According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met and to save delay time in the ramstage, add an early init data region to store the elapsed time since assertion. This will speed up the boot time by 100ms. PCIe port 1 and port 2 share the same PCIe resources, but PCIe port 2 is not used. Therefore, in mtk_pcie_pre_init(), make sure PCIe port 2 is reset to prevent interference with PCIe port 1. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I826a96822e88972bcd4966b6681797a646adf3d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-28soc/mediatek/common: Move PCIe definition to the common directoryJarried Lin
To reduce duplicate pcie.h in other SOC folder, mocw pcie.h to mediatek/common folder TEST=Build pass BUG=b:317009620 Change-Id: I8e29ed4027433700652b07b3461eeb8546d45c9b Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-27soc/intel/skylake/Makefile: Remove dead codeFelix Singer
This code is never reached since the hardware uses different SoCs. Besides, mainboard specific code should not be added to SoC code. Change-Id: Id82d5d0b829442c35c093974c06a029259838a9a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-10-26soc/intel/cmn/fast_spi: Improve debug message for SPI flash windowsSubrata Banik
This commit improves the debug messages when initializing SPI flash windows by adding the window type (Fixed Decode or Extended Decode) to the log output. This makes it easier to understand which window is being initialized and can help with debugging issues related to SPI flash access. w/o this patch: [INFO ] MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] MMAP window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000 w/ this patch: [INFO ] Fixed Decode Window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] Extended Decode Window: SPI flash base=0x900000, Host base=0xf9900000, Size=0x700000 Change-Id: I904f70f42fa70ea06e6f49bd44631a8491463207 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-26mb/google/fatcat: Drop LOCK_CONFIG for GPP_D15 in early GPIO configSubrata Banik
Ideally lock configuration is not applicable for early GPIO configuration (like bootblock/romstage) and is only required for GPIO PAD configuration by later statge (like ramstage). The GPP_D15 pin was previously configured with LOCK_CONFIG in the early bootblock GPIO configuration. This is not necessary and prevents later boot stages from configuring this GPIO. Change-Id: Ie0e648b750d7579def39ed95eab862dc3245499c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com>
2024-10-25mb/google/brox/lotso: Enable BT audio offload configWentao Qin
Enable BT audio offload of WIFI_CNVI_WIFI6E or unprovisioned based on fw_config. BUG=b:373510270 TEST=Build and boot to Lotso. Verify the config from serial logs. w/o this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 0 ``` w/ this CL - ``` [SPEW ] -- CNVi Config -- [SPEW ] CNVi Mode= 1 [SPEW ] Wi-Fi Core= 1 [SPEW ] BT Core= 1 [SPEW ] BT Audio Offload= 1 ``` Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Change-Id: I36f8c3fb24166c86d5fc4099fa9cde8cdecb9d49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84768 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-10-24soc/intel/common: Add PCIe device IDs for Snow RidgeYuchi Chen
This patch adds SPI and some accelerator device IDs for SNR platform. IDs are from Intel Atom Processor C5100, C5300, P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0. Change-Id: I7bd135d788816e4c3c42ac937450cf8cdcea00bc Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84782 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-24mb/google/fatcat: add GPIO pad configure based on fw_configJeremy Compostella
BUG=b:348678529 TEST=on Google Fatcat board. Set the proper CBI fw_config bit(s) and check that the corresponding GPIO PADs are configured as expected value accordingly. Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d54 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamirbohra@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-24mb/google/fatcat: Ensure RW_SECTION_B starts at 16MB boundarySubrata Banik
This patch updates the flash map layout to guarantee that the RW_SECTION_B section starts at a 16MB boundary. TEST=Successfully builds google/fatcat. Change-Id: I74ea21a8a4107d438bc03a0da182ea7e991e74bc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-24mb/google/brya/var/nova: Disable Thunderbolt deviceKenneth Chan
Nova doesn't support thunderbolt, so disable the TBT setting. Enabling TBT also causes the system to fail to enter S3/S5 state. S5 fail log: 24-10-21 20:23:34.610 Port 80 writes: 24-10-21 20:23:34.610 9a02 9a32 9a14 9c15 9c18 9c19 9c20 9c22 9c25 9c28 9c3f 9c43 9c44 9c4f 9c23 9a50 9a5f 9a33 9b40 9b41 24-10-21 20:23:34.620 9b42 9b47 9c80 9c81 9c82 9c83 9a61 9a63 9a03 9a04 9a05 9a06 9a07 9a0f 9a65 9a64 9c6a 9c71 9c7f 99 24-10-21 20:23:34.626 a0 a1 72 24 25 24 25 55 24 25 55 55 73 74 75 75 75 75 75 75 24-10-21 20:23:34.633 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 24-10-21 20:23:34.639 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 24-10-21 20:23:34.643 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 76 77 79 9c 24-10-21 20:23:34.649 93 7a fe 7b f8 aa ab 96 <--new powerinfo 24-10-21 20:23:59.424 powerinfo 24-10-21 20:23:59.424 power state 4 = S0, in 0x00ff The correct power state for S5 is G3, not S0. BUG=b:374213121 TEST=emerge-constitution coreboot chromeos-bootimage. Booting to OS and verify S3/S5 by EC log. Change-Id: I2bae8ae396f001dbef3322e361f9563792e1a1ef Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84838 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-24mb/google/nissa/var/glassway: Add touch screen ELAN9004 supportDaniel Peng
1. 2nd touch panel: INX N140HCN-EA1 C5 2. Set TOUCHSCREEN_ELAN9004 to value "3" BUG=b:374899470 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Confirm command evtest and touchscreen function is workable. Change-Id: Ic25bd46c7cb7948e920de4fd44edb87f20cf01c4 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84834 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-24mb/google/nissa/var/glassway: Support Samsung K3LKBKB0BM-MGCPDaniel Peng
Add the new memory support: Samsung K3LKBKB0BM-MGCP BUG=b:374880584 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: I47d9fd64fa841a2cf60930c5e319a9130019b0a5 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84831 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-23device/dram/ddr3: Use boolean for spd_dimm_is_registered_ddr3()Elyes Haouas
Change-Id: I8c9d66777b69b35f4df147c141fe94694f57be31 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83902 Reviewed-by: coreboot org <coreboot.org@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23device/dram/ddr2: Use boolean for spd_dimm_is_registered_ddr2()Elyes Haouas
Change-Id: I475f0c7582148e9b9f86b542f753a6654e9f9135 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-23soc/intel/broadwell; Use boolean for pch_is_wpt_xxElyes Haouas
Use boolean for pch_is_wpt() and pch_is_wpt_ulx(). Change-Id: Ifd1a46ebdbe08df6cc21ada100b94930b02cd7de Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: coreboot org <coreboot.org@gmail.com>
2024-10-23mb/erying: Add Erying Polestar G613 Pro (TGL-H)Alicja Michalska
Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E 0x3f8) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports - M.2 NGFF WiFi - PCI-E Resizable BAR (ReBAR) - VT-x WIP/Broken: - PCI-E ASPM (also broken on vendor's FW, clocks are messed up) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (seemingly a simple fix) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor hasn't enabled any protections on SPI chip. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-23device/pciexp: Add hot-plug capable helper functionPatrick Rudolph
Add and use a new helper function to determine if a device is 1) a PCIe device 2) it's mark hot-plug capable Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-23soc/intel/xeon_sp: Report PCIe integrated end points under DRHDJincheng Li
In case of a PCH-less platform, no DRHD_INCLUDE_PCI_ALL flags are used, all PCIe integrated end points should be explicitly listed under the DRHD they are affiliated to. Otherwise, the device MSI setting could fail. TESTED = Build and boot on intel/beechnutcity CRB In CentOS Stream (5.14.0-479.el9.x86_64) 9 5.14.0-479.el9.x86_64, without the changes, below failure logs will occur, [ 6.908347] ------------[ cut here ]------------ [ 6.908353] WARNING: CPU: 0 PID: 8 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908374] Modules linked in: [ 6.908379] CPU: 0 PID: 8 Comm: kworker/0:0 Not tainted 5.14.0-479.el9.x86_64 #1 [ 6.908385] Hardware name: Intel Beechnut City CRB/Beechnut City CRB, BIOS c1e9362c93be-dirty 09/25/2024 [ 6.908389] Workqueue: events work_for_cpu_fn [ 6.908401] RIP: 0010:pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908411] Code: 90 90 90 0f 1f 44 00 00 48 8b 87 00 03 00 00 89 f2 48 85 c0 74 14 f6 40 28 01 74 0e 48 81 c7 c8 00 00 00 31 f6 e9 19 de ac ff <0f> 0b b8 ed ff ff ff c3 cc cc cc cc 66 66 2e 0f 1f 84 00 00 00 00 [ 6.908417] RSP: 0000:ffffac47c0137c80 EFLAGS: 00010246 [ 6.908423] RAX: 0000000000000000 RBX: ffff9a0a874e2000 RCX: 000000000000009c [ 6.908428] RDX: 0000000000000001 RSI: 0000000000000001 RDI: ffff9a0a874e2000 [ 6.908433] RBP: 0000000000000000 R08: 0000000000000004 R09: 0000000000000001 [ 6.908437] R10: ffff9a0a8adcb258 R11: 0000000000000000 R12: 0000000000000001 [ 6.908440] R13: 0000000000000001 R14: ffff9a0a8738be00 R15: ffff9a0a874e20c8 [ 6.908443] FS: 0000000000000000(0000) GS:ffff9a0ded000000(0000) knlGS:0000000000000000 [ 6.908448] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 6.908451] CR2: ffff9a11fffff000 CR3: 00000003cd410001 CR4: 0000000000770ef0 [ 6.908455] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 6.908457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7: 0000000000000400 [ 6.908460] PKRU: 55555554 [ 6.908462] Call Trace: [ 6.908465] <TASK> [ 6.908470] ? show_trace_log_lvl+0x1c4/0x2df [ 6.908484] ? show_trace_log_lvl+0x1c4/0x2df [ 6.908492] ? msi_capability_init+0x193/0x280 [ 6.908501] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908509] ? __warn+0x7e/0xd0 [ 6.908519] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908527] ? report_bug+0x100/0x140 [ 6.908537] ? handle_bug+0x3c/0x70 [ 6.908545] ? exc_invalid_op+0x14/0x70 [ 6.908551] ? asm_exc_invalid_op+0x16/0x20 [ 6.908561] ? pci_msi_setup_msi_irqs+0x27/0x40 [ 6.908569] msi_capability_init+0x193/0x280 [ 6.908577] __pci_enable_msi_range+0x1a3/0x230 [ 6.908586] pci_alloc_irq_vectors_affinity+0xc3/0x110 [ 6.908594] pcie_port_enable_irq_vec+0x3f/0x250 [ 6.908604] ? __pci_set_master+0x31/0xd0 [ 6.908614] pcie_portdrv_probe+0xdf/0x300 [ 6.908620] local_pci_probe+0x4c/0xa0 [ 6.908627] work_for_cpu_fn+0x13/0x20 [ 6.908635] process_one_work+0x194/0x380 [ 6.908643] worker_thread+0x2fe/0x410 [ 6.908649] ? __pfx_worker_thread+0x10/0x10 [ 6.908655] kthread+0xdd/0x100 [ 6.908665] ? __pfx_kthread+0x10/0x10 [ 6.908673] ret_from_fork+0x29/0x50 [ 6.908686] </TASK> [ 6.908688] ---[ end trace 0000000000000000 ]--- Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84315 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23util/cbfstool: Add Intel platform boot policy supportGang Chen
Intel platform boot policy setting blob is linked into FIT table as an FIT4 entry. It is required for server executing CBnT and/or PFR without a PCH. Please refer to chapter 4.6 of the document in below link: https://www.intel.com/content/dam/www/public/us/en/documents/ guides/fit-bios-specification.pdf Tool usage: ./util/cbfstool/ifittool -f <binary> -a -n <cbfs name> -t 4 \ -r COREBOOT -s <max table size> Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Li, Jincheng <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84305 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/intel/xeon_sp/ibl: Remove unused logicsJincheng Li
Change-Id: I79b08630753b3aceb94becc8b9d682a3d3ca8310 Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84308 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-23soc/intel/xeon_sp/ibl: Update registers for reach bootableShuo Liu
Change-Id: Id2a2946b7fdfd7fd245835afe6abc9a3f7e1a508 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Co-authored-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23soc/intel/xeon_sp: Add Kconfig SUPPORT_SIMICS_SIMULATIONShuo Liu
Xeon-SP simics doesn't provide simulation of writable PAM-F (Programmable Attribute Map) segment and hence coreboot needs to enable SHADOW_ROM_TABLE_TO_EBDA to write system table pointers to EBDA (Extended BIOS Data Area). Change-Id: I216204987ad646a5d1655323d2725cfd3415a2d7 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23mb/ocp/deltalake: Clean codePatrick Rudolph
Use dev_find_all_devices_on_stack() to find the PCI device on a given stack. That way open coded duplicated code can be dropped and there's no need to call socket0_get_ubox_busno(), which allows to drop socket0_get_ubox_busno(). In addition it adds PCI multi segment support. Change-Id: Ib0ed177ae22112a9f2ed32199409d91cb5851ede Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84790 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/mediatek/common: Add more definitions for SPMIYidi Lin
The newly added enums and struct members will be used by MT8196. BUG=none TEST=emerge-corsola coreboot; emerge-geralt coreboot Change-Id: I32e758cc4244114073606c418a69e0467cdf1039 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84773 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-23soc/mediatek/common: Maintain common pmif data in pmif_init.cYidi Lin
MT8196 has different pmif_spmi_arb and pmif_spi_arb configurations. Move the common pmif data to a separate file in order to reuse common/pmif.c as much as possible. BUG=none TEST=emerge-corsola coreboot; emerge-geralt coreboot Change-Id: I24643ce58a57b9cc3c5220bc06a85b141b366eee Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 09:22:41 +0000