summaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2017-08-31lenovo/g505s: Enable XHCI device in devicetreeKyösti Mälkki
Enabling XHCI is additionally controlled with Kconfig option HUDSON_XHCI_ENABLE. Even when it is enabled, it EHCI debug works on the USB port next to the DVD drive door. Change-Id: I83738da6015f58ecd0819c553d333a176365dc78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31AGESA: Remove separate f15rlKyösti Mälkki
Change-Id: I18c62ad034249c5ad14e5d5e708b4f0d4bcbf400 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-31lenovo/g505s: Switch from f15rl to f15tnKyösti Mälkki
Support code for Trinity and Richland is identical now. I have also come across a unit with Trinity model CPU, whose CPUID was not listed in f15rl while f15tn already had support for f15rl. Change-Id: Ia869429b75a9b308b4d4a84f16914ca629b1b1b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-31cpu/x86 asm: Just use the correct op suffixEdward O'Callaghan
LLVM AS doesn't support as much GNU junk extensions, data16/32 is almost never needed in truth if we just use the correct op suffix. So do that here, fixes clang/llvm builds with the integrated-as toggled on. Change-Id: I6095d03d0289b418a49a10f135de5eb0e117cae0 Also-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-31AGESA f15 vendorcode: Remove unused sourcesKyösti Mälkki
Change-Id: Id1ed36e7e76d25cdc9e86254b108deaca0f8b423 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f15 vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: I1b7d7c017a4dfd93c5befbc0d5858278eacc6c89 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f16kb vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: Id3d9a365469f7d73788cad4095ec3495fc9baf3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f15tn vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: I2a6e53e5555a1b1e19c45a196b21f8505e275a76 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f14 vendorcode: Remove unused sourcesKyösti Mälkki
Change-Id: Ie4a735b156ded934fac0c9248fbb9042bf9be781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f14 vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: I6dbcd23b0ea03b1b965d43346ae1cf7cf1971eb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f12 vendorcode: Remove unused sourcesKyösti Mälkki
Change-Id: Ia22c96ee19babb3fc64d57966ea923eb5ec4b48f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f12 vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: I8438dc468e59174bd6f88c0c02b2fbf60587dbfd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-30soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLESubrata Banik
This patch to avoid build bot hang issue due to no active default value for UART_FOR_CONSOLE kconfig option. Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21287 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30mainboard/google/soraka: Add stop gpio control to touchscreen deviceFurquan Shaikh
BUG=b:64987428 TEST=Verified that touchscreen works on boot-up and after suspend/resume. No power leakage via stop gpio in suspended state. Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-30acpigen: Add stop gpio control to power resourceFurquan Shaikh
There is at least one I2C device (being used by Soraka) that has 3 controls -- enable, reset and stop. If the stop gpio is not put into the right state when turning off the device in suspend mode, then it causes leakage. Thus, we need control in power resource to be able to stop the device when entering suspend state. BUG=b:64987428 TEST=Verified on soraka that touchscreen stop is correctly configured on suspend. Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21249 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-30mainboard/google/soraka: Remove Atmel TouchscreenFurquan Shaikh
We no longer use this touchscreen device, so get rid of it. BUG=b:64987428 Change-Id: I67af787d231317a80998fb483eed5674de19aeb4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30google/cyan: update SPD functionsMatt DeVillier
Update cyan's SPD-related functions to more closely mirror those of other Braswell boards, in order to simplify the upcoming baseboard/variant setup for Braswell ChromeOS boards. TEST: boot google/cyan, observe SPD correctly identified in cbmem log, RAM-related data correct in SMBIOS tables. Change-Id: Iafe99ec0795764f645e0a91f5b321be5b4c6fd88 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-30drivers/i2c/ck505: Add generic driver to configure clockgenArthur Heymans
Replaces the ics/954309 driver with a more generic version to accommodate clockgens with a different amount of registers. It also features a mask to only touch certain bits of the clockgen. TODO: set appropriate mask for X60/T60 since the datasheets for their clockgens can be found. Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-30soc/intel/common: Add functions into common SMM librarySubrata Banik
This patch to add helper function to get SMM region start and size based on systemagent common library. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: If10af4a3f6a5bd22db5a03bcd3033a01b1cce0b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/common: Add functions into common system agent librarySubrata Banik
This patch to add helper function to get tseg memory base and size for HW based memory layout design. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: I4c8b79f047e3dc6b2deb17fdb745f004004526b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/cannonlake: Add PrmrrSize and C6DRAM configSubrata Banik
This patch ensures coreboot can set PRMRR size and C6DRAM enable FSP-M UPDs. Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30mb/google/eve: rt5514: Add 16ms delay on dmic initDuncan Laurie
Add a 16ms delay to DMIC init by the kernel driver in order to prevent an audible 'pop' noise when starting to record. BUG=b:63413023 TEST=manual testing to ensure this device property is present in SSDT: Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package () { Package () { "realtek,dmic-init-delay", 0x10 } } }) Change-Id: If9160ce6992153ba49719029de336595bbf4ae72 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30drivers/i2c/generic: Support additional device propertiesDuncan Laurie
Add support for providing additional free form device properties via devicetree in order to make this driver suitable for kernel drivers that need additional board-specific device properties. This currently allows adding up to 10 additional properties to a device. BUG=b:63413023 TEST=manual testing to ensure that newly added properties are in SSDT Change-Id: I2b8ceb208f4aba01053746547def6d07c8f8f3a2 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30acpi_device: Provide a new function to add a list of propertiesDuncan Laurie
Provide a new function that will allow adding arbitrary properties to devicetree entries without needing a custom driver for the device. This will allow the 'generic i2c' driver to support kernel drivers that need additional device properties exposed and have those board specific properties set with values from devicetree. BUG=b:63413023 TEST=not used yet, compiles cleanly Change-Id: Id272256639a8525406635e168a3db5ab1ba4df6b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21269 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30sb/intel/*: add option to lockdown chipset on normal boot pathBill XIE
On platforms with a PCH, some registers within host bridge should be locked down on each normal boot path (done by either coreboot or payload) and S3 resume (always done by coreboot). A function to perform such locking is implemented in src/northbridge/ intel/*/finalize.c, and is designed as the handler of an #SMI triggered with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only triggered during s3 resume, and not on normal boot path. This problem has beed discussed in https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html . This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/ intel/common/Kconfig is added to control the actual locking, which depends on several compatibility flags, including "HAVE_INTEL_CHIPSET_LOCKDOWN". In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint" have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected. The change is only well tested on Sandy Bridge, my Lenovo x230. Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-30ec/google: Use feature flag layout that matches the EC host commandPatrick Georgi
The EC side of the feature bits in ACPI EC space isn't stable yet, and we're now going for matching them up with the EC host command of the same purpose. Change-Id: I9c1f0e5390e840ea0c32315a3da8eea6f3e12f54 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30AGESA: Drop Kconfig CPU_AMD_SOCKET_AM3R2Kyösti Mälkki
Never selected in our tree. Change-Id: I5065903ebf74d281ecccaf53e0cc9fa24317e1cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-30AGESA f15 vendorcode: Remove AM3r2 refcodeKyösti Mälkki
We never had a board in the tree that implements this. If you are interested in implementing such board, note that also f12 and f14 had copies of the same refcode. As part of the sourcetree cleanup it was not studied which was the most up-to-date one for AM3r2. Change-Id: Ic7dd065c0df08c22af6f3a2dcfc7ff47d6283a46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-30AGESA f14 vendorcode: Keep only Ontario refcodeKyösti Mälkki
The only subtree we build is /ON. Change-Id: I8cb11211a2a5ab7d8ae6296b601ee09146a9c9f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-30AGESA f12 vendorcode: Keep only Liano refcodeKyösti Mälkki
The only subtree we build is /LN. Change-Id: I035932a4be41fa0451a3f3c7be33442afeeb5571 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-30AGESA vendorcode: Remove AMD_INIT_RECOVERYKyösti Mälkki
These files were never built in our tree. Furthermore, AMD_INIT_RECOVERY was already deprecated in AGESA spec rev 2.20 from Dec 2013. Change-Id: Ifcaf466ca0767bf7cfa41d6ac58f1956d71c7067 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-29sb/intel/bd82x6x: make hotplug map consistent to remapped portsBill XIE
"pcie_port_coalesce" will cause pcie being remapped under certain conditions, but flags within "pcie_hotplug_map" should be updated along with ports. Test on my lenovo t430s. Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21178 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-29mainboard/google/soraka: Tune I2C params (hcnt, lcnt, hold time)Furquan Shaikh
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:35948024 TEST=Verified for 25 iterations that the frequency on each bus ranges <= 400KHz. I2C0: 393 - 397 I2C1: 393 - 400 I2C2: 392 - 400 I2C4: 392 - 400 I2C5: 392 - 400 Change-Id: I3e12c75eb7e82a83aa6a6bcfcc11c12f83f2d3d4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-29soc/intel/cannonlake: Fix Coverity scan errorLijian Zhao
Add return in case of null pointer to avoid coverity scan error, fixed 1.Coverity ID 1379849: Null pointer dereferences (FORWARD_NULL) 2.Coverity ID 1379848: Null pointer dereferences (FORWARD_NULL) Change-Id: Ica19735307736c8a55c29af88db8b1372f8779e4 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-08-29amd/stoneyridge: Change ACPI _PR.CPxx to _PR.PxxxMarc Jones
This is a bug introduced by this commit: stoneyridge: Fix CPU ASL \_PR table [commit I870f81] The following error is found in dmesg ACPI Error: [\_PR_.P000] Namespace lookup failure, AE_NOT_FOUND... ACPI Exception: AE_NOT_FOUND, During name lookup/catalog... ACPI Exception: AE_NOT_FOUND, (SSDT:AGESA ) while loading table... ACPI Error: 1 table load failures, 3 successful... ... acpi-cpufreq: overriding BIOS provided _PSD data And, "ls -la /sys/devices/system/cpu/cpufreq/" doesn't work The cause is that the Pstate SSDT table generated by AGESA expects CPU variables \_PR.Pxxx, not \_PR.CPxx as generated by coreboot. Use Kconfig to set the required string. BRANCH=none BUG=b:64885241 TEST= Check dmeg and ls -la /sys/devices/system/cpu/cpufreq/ Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-29arch/x86: Add Kconfig option for ACPI \_PR CPU name stringMarc Jones
Add a Kconfig option to change the \PR.CPxx name string. This provides some flexibility when working with table not generated by coreboot. Change-Id: Ibc0c56783c6da80501e2177de96a414b592cb74f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-28mb/lenovo/t400/blc.c: Add B141EW05 V3 to whitelistKevin Keijzer
TESTED on Lenovo T400 Change-Id: I365aeb7e997def225c23d3287558bdc4eefa4298 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/21230 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-28google/Bruce: Add Raydium touch screen supportSheng-Liang Pan
Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64705535 BRANCH=master TEST=emerge-coral coreboot Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/21233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-28soc/amd: Standardize guards on header filesMartin Roth
The guards in the header files were inconsistent. Some had no leading or trailing underscores, some had one, some had both leading and trailing. Change all to double leading & trailing underscores. Change all comments to have a space before them instead of tabs BUG=b:62235990 Test=Build Kahlee Change-Id: I4466df529ab201c922096a31d7438381778b582f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-28mainboard/winnet/g170: Add ACPI supportLubomir Rintel
What is present is APIC and legacy interrupt routing and the soft-off sleep state. Other sleep states are missing, so are the SuperIO devices. Boots Linux with and without "noapic" and a Windows XP (installed with factory BIOS, the installer reportedly requires legacy keyboard). Change-Id: Iee3ede8683d1ea51317228d4f782af27043cc945 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28mainboard/winnet/g170: Initialize the IRQ routingLubomir Rintel
Initialize IRQ routing for legacy non-PNP OSes the same as the factory firmware would do. Change-Id: I0c7a7d584a2c47471456ab54ef6da815a2dc4e7c Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28mainboard/winnet/g170: Add WinNET G170 boardLubomir Rintel
Change-Id: I0d7aba827fb87f69f542edd2f7ac7a66d949f865 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28mainboard/winnet/g170: Copy from mainboard/bcom/winnetp680Lubomir Rintel
G170 is a board manufactured by WinNET, used in thin clients including HP Neoware CA19 and IGEL 2110. Copied from mainboard/bcom/winnetp680 which seems to be a similar board with an extra PCI slot. The p680 should probably be moved to winnet/ too, since the board is an OEM WinNET board, with BCom being just a machine that happens to it. Change-Id: I90b89ee634d90cfba2e56cca5b76cfd2bd7a8d0b Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28southbridge/via/vt8237r/acpi: Add IRQ routingLubomir Rintel
Includes objects for interrupt links, the LPC bridge and interrupt routing tables for the internal devices for both APIC and legacy modes. The default routing tables only includes peripherals internal to the VT8237R, if a mainboard has PCI slots (mine does not have), it needs to supply its own routing table. Change-Id: I3a0cdafc19159fe6c38e4dde08ad0bf2bd0dd6b8 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28soc/amd/stoneyridge: Increase preram console sizeMarshall Dawson
Increase the default setting to add more CAR space for the early console. This avoids truncation of the log. BUG=b:64980233 Change-Id: Ia11d1c6c186a7025510c240206743ebe8d741461 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21186 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-28mb/gigabyte/ga-b75m-d3*/acpi: Remove redundant codePatrick Rudolph
Remove obsolete code. The same settings are always done in southbridge. Change-Id: Ic893ddbace73ae8b122c4fb675febc7d1e0b5da9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-28AGESA: Remove Kconfig AMD_AGESA_FAMILY10Kyösti Mälkki
Never selected in our tree. The vendorcode source for fam15 also includes fam10 support if required. Change-Id: Ifff328ecdd8afa988f844b6fd631818b51bd5b5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28AGESA f15: Remove f10 referencesKyösti Mälkki
Vendorcode for f15 also has f10 support, so AMD_AGESA_FAMILY_10 was never selected. Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28AGESA f15tn vendorcode: Remove f10, f12 and f14 referencesKyösti Mälkki
Files themselves were never committed. Change-Id: I41ebdd98c10b6a80f8e110fb265203a5d06072ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28AGESA f14 vendorcode: Remove f10, f12 and f15 referencesKyösti Mälkki
Change-Id: I08ee5a6c50d7eee2c39df326a6c6acd40212f093 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28AGESA f12 vendorcode: Remove f10, f14 and f15 referencesKyösti Mälkki
Change-Id: I5a9ff6eae3940d70edaf551a9d37d3d1464fbd31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28AGESA f10 vendorcode: Remove refcode sourcesKyösti Mälkki
We never had a board in the tree that implements this. Change-Id: Idce32a20c24e31eb52f8509d4a7cccfc24cf17cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28AGESA f10 vendorcode: Remove unused sourcesKyösti Mälkki
These fam10 sources under fam12 and fam14 were never built. Change-Id: Iff0964aba0a061b43144427388c07aea57d6d566 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculationSubrata Banik
This patch ensures skylake device using FSP1.1 can use HW based DRAM top calculation which was broken due to skylake fsp1.1 not honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size. This WA is not needed for FSP2.0 implementation due to PrmrrSize UPD is available and considering into hw based dram top calculation. BRANCH=none BUG=b:63974384 TEST=Build and boot lars which is using skylake 1.1 fsp. Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-08-28mainboard/google/poppy: Tune I2C params (hcnt, lcnt, hold time)Furquan Shaikh
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:35948024 TEST=Verified for 25 iterations that the frequency on each bus ranges <= 400KHz. I2C0: 375 - 400 I2C1: 377 - 400 I2C2: 377 - 400 I2C4: 375 - 397 I2C5: 375 - 397 Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-27nb/intel/pineview: Fix typo in DRAM timing computationArthur Heymans
This problem was introduced in: 12a4e98cea nb/intel/pineview/raminit: Refactor timings selection Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-27mb/lenovo/*/acpi_tables: Add critical and passive thresholdPatrick Rudolph
Add critical and passive threshold to be advertised in thermal zone 0. Change-Id: Ic75a80994b27ac19651ed52b7fc3c00c65cd9c01 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-27ec/lenovo/h8/acpi/thermal: Don't hardcode limitsPatrick Rudolph
Add support for board specific critical and passive limits using GNVS table. Use default values if no board specific limit exists. * Add ACPI methods _TZP, _TSP and _PSV. * Update ACPI method _CRT to use board specific if available. Tested on Lenovo T500. Change-Id: If438a909f4415f50cd7a764fb5fba7ec29599606 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-27sb/intel/*/nvs: Rename registerPatrick Rudolph
Rename register to match recent intel models. Required for Lenovo H8 to operate on all generations. Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-26drivers/intel/fsp2_0: Link Post PCI enumeration Notify with BS_DEV_ENABLESubrata Banik
This patch to ensure that coreboot is able to store memory training data into SPI and perform platform lockdown after PCI enumeration is done before handing over control to NotifyPhase() - Post PCI enumeration. Modified coreboot bootstate execution order below: BS_DEV_ENUMERATE - BS_ON_EXIT - Store Memory training data into SPI BS_DEV_RESOURCES - BS_ON_EXIT - Platform Lock Down after PCI enumeration BS_DEV_ENABLE - BS_ON_ENTRY - NotifyPhase() post PCI enumeration TEST=Please find test case and results for Chrome Devices as Apollolake- Reef, Kabylake-Eve and Poppy and Non Chrome Devices with Yocto OS. 1. Without patches Cold Boot MRC: no data in 'RW_MRC_CACHE' ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Warm Reboot from Chrome CMD Line: $ reboot MRC cache found, size 18c8 bootmode:2 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state MRC cache found, size 18c8 bootmode:17 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. 2. With patches Cold Boot MRC: no data in 'RW_MRC_CACHE' ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Warm Reboot from Yocto CMD Line: $ reboot MRC cache found, size 18c8 bootmode:2 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state MRC cache found, size 18c8 bootmode:17 ... MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. Tested the patches more thoroughly, from the S5->S0, S3->S0 bootlog there is no noticeable difference. On a reboot, suspend resume from Chrome console, the mrc cache is found, and utilized. Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-26soc/intel/skylake: Move SPI lock down config after resource allocationBarnali Sarkar
This patch to ensures that coreboot is performing SPI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence SPI lock down programming has been moved right after pci resource allocation is donei, so that SPI registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set. Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-26soc/intel/cannonlake: use __packedAaron Durbin
Now that there is a handy macro utilize it. Change-Id: I560bc7a591075235229952cdea63d4e667f323ee Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-26soc/intel/skylake: Move DMI lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing DMI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence BIOS Interface lock down through Sideband access has been moved right after pci resource allocation is done, so that BILD lock down is getting executed along with LPC and SPI BIOS interface lockdown settings before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure DMI register offset 0x274c bit 0 is set. Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25jetway/nf81-t56n-lf: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: I6ad0c4cf2f0398f0b1efac1282822acf0d4a3610 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25amd/union_station: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: I706de64ae5d940df70701c8b9dd717f8e212cd0e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25amd/south_station: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: I09fe0e903a1241212f81e2a897898356a7e372a9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25amd/persimmon: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: Id2ef3e5aa0ea3f6e714eda6d9dbdf62fb96c0a74 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25amd/inagua: Switch away from AGESA_LEGACYKyösti Mälkki
Change-Id: Ie76291a8e227e49aae6fc6339cec2009ebd67fff Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25elmex/pcm205400: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: Ib386b5d9ba636614016c3f9ac042fee43eac53f2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25asrock/e350m1: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: I6ad99af55975b21b0a7671553246cdb5a1e19091 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25gizmosphere/gizmo: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: I26e2450babfde1580e0e794c519344112d4019ee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25pcengines/apu1: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: I10b3e53a5e39764e3b199561d07391779804407c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25google/beltino: fix LED polarity for mccloud variantMatt DeVillier
The LED polarity was set incorrectly, fix using values derived from original Chromium sources: branch firmware-mccloud-5827.B, ToT src/mainboard/google/mccloud/smihandler.c src/mainboard/google/mccloud/romstage.c TEST: boot google/mccloud, observe power LED on normally, blinking in S3/S4, and off in S5. Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-25google/cyan: Increase RO coreboot size on flashMatt DeVillier
Commit 05627831826cab096789bd19f004b33a4cd70c0e applied this change to other Google boards, but cyan was left out. Bring cyan in line with other Google boards. Change-Id: Id86bea538a7b82367ea6ddbd3fe3efb1b1c0078d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-25google/cyan: Remove support for pre-EVT boardMatt DeVillier
Cleaning up code to remove support for pre-EVT rev of cyan board. Analogous to what was done for intel/strago in commit 103f00d. Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Use GpioInt for Keyboard IRQJagadish Krishnamoorthy
Cherry-pick from Chromium commit a162348. Remove the hard coded IRQ number for the keyboard interrupt. IRQ number can change based upon the gpio bank index ordering. Hence pass the gpio bank and index number so that kernel calculates the IRQ number. Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Disable L1 sub stateT.H. Lin
Adapted from Chromium commit dc59188. Disable L1 sub state to prevent WiFi randomly disappear condition. Original-Change-Id: I8975bb4bbbc2fc89b91b06ae02716367890c672d Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Rajat Jain <rajatja@chromium.org> Original-Reviewed-by: Vincent Wang <vwang@chromium.org> Oriignal-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Change-Id: I51a1bcca6431e6bc28baf9b09433cec13db925c3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/braswell: Put SERIRQ in quiet modeHannah Williams
Cherry-pick from Chromium commit 1568761. Original-Change-Id: If459c3cab8fb7ca13d8bff3173a94855ec2e2810 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: Ibb2e6d316adcfcc0d56d242501aac9c4c0bbdf62 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/braswell: Populate NVS SCC BAR1Hannah Williams
Cherry-pick from Chromium commit f92d7be. This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put SD controller in D3 Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Add 2nd source memory 2-channel 4G (Micro/Samsung)T.H. Lin
Cherry-pick from Chromium commit 7f0cdf0. Cyan board add 4G DDR3L 2nd source memory (Micro/Samsung) Original-Change-Id: I12f82082d8227e61a97ce0a001d7d2b1f6613e06 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Change-Id: Ieca7201346414d7a962f9619dbe846c67c0f02d6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Add 2nd source memory (Micro/Samsung)T.H. Lin
Cherry-pick from Chromium commit 3b578ef. Cyan board use new 2nd source memory (Micro/Samsung) Original-Change-Id: I6f4e8438faede7ac742776a622c265922e498898 Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Change-Id: Ie2febe4de57c00c269def15d57f2b5a6f0f378aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Fix Touchscreen InterruptJagadish Krishnamoorthy
Cherry-pick from Chromium commit 1138727. Elan touchscreen driver expects the first gpio resource in asl to be the reset line. The driver considers the gpio based irq line as reset gpio resource and changes the direction to output. This will cause irq registration to fail. Solution is to pass Interrupt resource for touchscreen irq instead of GpioInt. Original-Change-Id: Ia72d4ad80117f3c0014098113c9027416026e65e Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Enable CA MirrorShobhit Srivastava
Cherry-pick from Chromium commit e49deb1. Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is board specific. Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Disable unused lines on Gpio North BankJagadish Krishnamoorthy
Cherry-pick from Chromium commit 1940eb6. The unused lines leads to spurious interrupts on few of the systems. Original-Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Tested-by: Bernie Thompson <bhthompson@chromium.org> Change-Id: I6f4f7cec8ef11e781c66b6efff4188259469e41c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Clean-up the devicetreeRavi Sarawadi
Cherry-pick from Chromium 2b51633. Disable unused PCI devices. Update PCI DeviceID. Original-Change-Id: I34fa6e25f9178de959aad30cc979d787cf76b8ad Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I7a06a1d44ce933000cbfe2eb71823ee66cb46a34 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25google/cyan: Support reading Memory strap GPIOs to select SPDSubrata Banik
Cherry-pick from Chromium commit 8f63720. SoC GPIO to read Memory strap not getting configured correctly causing incorrect RAMID read during ROMSTAGE TEST=Build and boot the platform with differnt Memory type and read RAMID correctly inside spd.c RAMID = 0 => 4GB Samsung Memory RAMID = 1 => 4GB Hynix Memory RAMID = 2 => 2GB Samsung Memory RAMID = 3 => 2GB Hynix Memory Original-Change-Id: Ide9d4b5f73565cddd74cedf7afe4b7d168dde74c Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-25soc/intel/braswell: select GENERIC_GPIO_LIBMatt DeVillier
Needed for to-be-added Google Braswell boards which make use of common GPIO library function to determine installed RAM type. Change-Id: Ie9b0c6513f10b252bf0a5014bd038d24879421be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25mainboard/intel/cannonlake_rvp: SMBus, SAGV and Skip FSP MPInit in devicetreePratik Prajapati
Set SMBus, SAGV and Skip FSP MPInit configuration from devicetree.cb Change-Id: Ic810b003bf7fb13447d5d5dcd49cfcc31785b440 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/cannonlake: Init UPD params based on configPratik Prajapati
Initialize UPD params based upon config Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21175 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25soc/intel/skylake: Remove TCO lock down programmingSubrata Banik
FSP is doing TCO lock inside Post PCI bus enumeration NotifyPhase(). Hence remove TCO Lock down programming from coreboot. TEST= Ensure TCO_LOCK offset 8 bit 12 is set. Change-Id: Iec9e3075df01862f8558b303a458126c68202bff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/common: Add function to DLOCK PR registersBarnali Sarkar
Add a function in FAST_SPI library to discrete lock the PR registers 0 to 4. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Move PMC lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing PMC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence PMC register lock down has been moved right after pci resource allocation is done, so that PMC registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Remove ABASE lock down programmingSubrata Banik
FSP is doing PMC ABASE lock inside Post PCI bus enumeration NotifyPhase(). Hence remove ABASE Lock down programming from coreboot. TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set. Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Move LPC lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/common: Move update_mrc_cache after BS_DEV_ENUMERATESubrata Banik
This patch ensures that MRC cache data is already written into SPI chip before SPI protected regions are getting locked during BS_DEV_RESOURCES-BS_ON_EXIT. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence storing mrc cache data into SPI has been moved right after pci enumeration is done, so that SPI registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure MRC training data is stored into SPI chip and power_ Resume autotest is passing. Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Add LPC and SPI lock down config optionSubrata Banik
This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25mainboard/google/coral: Add USB2 phy setting override for SantaTim Chen
In order to pass type C USB2 eye diagram for sku Santa, USB2 port#1 PHY register needs to be overridden. port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 BUG=b:64880573 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25amd/XX/hudson: Remove #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)Kyösti Mälkki
Remove the unnecessary #if from around the #include "fchec.h". Turn #if statements into if(). Change-Id: Ia0582b3ce24c55dd439dfadb727507240accd9d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25amd/pi/hudson: Fix FCH ECMartin Roth
Move the fchec.h files, which do not seem mainboard specific, out of the mainboard directories into the southbridge/soc directories. Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25soc/amd/stoneyridge: Move IMC ASL sourceKyösti Mälkki
This is not specific to a board but the binary IMC firmware used on the platform. Also remove unused IMSP and IMWK methods. Change-Id: I80026bca55f5ba236c080bcd882fc374559942e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 19:27:05 +0000