mainboard/winnet/g170: Copy from mainboard/bcom/winnetp680

G170 is a board manufactured by WinNET, used in thin clients including
HP Neoware CA19 and IGEL 2110.

Copied from mainboard/bcom/winnetp680 which seems to be a similar
board with an extra PCI slot.

The p680 should probably be moved to winnet/ too, since the board is an
OEM WinNET board, with BCom being just a machine that happens to it.

Change-Id: I90b89ee634d90cfba2e56cca5b76cfd2bd7a8d0b
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

7 files changed, 273 insertions, 0 deletions

diff --git a/src/mainboard/winnet/g170/Kconfig b/src/mainboard/winnet/g170/Kconfig
new file mode 100644
index 0000000000..c328c3fa79
--- /dev/null
+++ b/src/mainboard/winnet/g170/Kconfig
@@ -0,0 +1,25 @@
+if BOARD_BCOM_WINNETP680
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CPU_VIA_C7
+	select NORTHBRIDGE_VIA_CN700
+	select SOUTHBRIDGE_VIA_VT8237R
+	select SUPERIO_WINBOND_W83697HF
+	select HAVE_PIRQ_TABLE
+	select HAVE_OPTION_TABLE
+	select BOARD_ROMSIZE_KB_512
+
+config MAINBOARD_DIR
+	string
+	default bcom/winnetp680
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "WinNET P680"
+
+config IRQ_SLOT_COUNT
+	int
+	default 10
+
+endif # BOARD_BCOM_WINNETP680
diff --git a/src/mainboard/winnet/g170/Kconfig.name b/src/mainboard/winnet/g170/Kconfig.name
new file mode 100644
index 0000000000..5b09e7a366
--- /dev/null
+++ b/src/mainboard/winnet/g170/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_BCOM_WINNETP680
+	bool "WinNET P680"
diff --git a/src/mainboard/winnet/g170/board_info.txt b/src/mainboard/winnet/g170/board_info.txt
new file mode 100644
index 0000000000..0ba2657f1a
--- /dev/null
+++ b/src/mainboard/winnet/g170/board_info.txt
@@ -0,0 +1 @@
+Category: settop
diff --git a/src/mainboard/winnet/g170/cmos.layout b/src/mainboard/winnet/g170/cmos.layout
new file mode 100644
index 0000000000..d9ec5520bf
--- /dev/null
+++ b/src/mainboard/winnet/g170/cmos.layout
@@ -0,0 +1,36 @@
+entries
+
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+456          1       e       1        ECC_memory
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/winnet/g170/devicetree.cb b/src/mainboard/winnet/g170/devicetree.cb
new file mode 100644
index 0000000000..f0a086b642
--- /dev/null
+++ b/src/mainboard/winnet/g170/devicetree.cb
@@ -0,0 +1,64 @@
+chip northbridge/via/cn700			# Northbridge
+  device domain 0 on			# PCI domain
+    device pci 0.0 on end			# AGP Bridge
+    device pci 0.1 on end			# Error Reporting
+    device pci 0.2 on end			# Host Bus Control
+    device pci 0.3 on end			# Memory Controller
+    device pci 0.4 on end			# Power Management
+    device pci 0.7 on end			# V-Link Controller
+    device pci 1.0 on end			# PCI Bridge
+    chip southbridge/via/vt8237r		# Southbridge
+      # Enable both IDE channels.
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      # Both cables are 40pin.
+      register "ide0_80pin_cable" = "0"
+      register "ide1_80pin_cable" = "0"
+      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_hi" = "0x1d"
+      device pci f.0 on end			# IDE
+      device pci 10.0 on end			# UHCI
+      device pci 10.1 on end			# UHCI
+      device pci 10.2 on end			# UHCI
+      device pci 10.3 on end			# UHCI
+      device pci 10.4 on end			# EHCI
+      device pci 11.0 on			# Southbridge LPC
+        chip superio/winbond/w83697hf		# Super I/O
+          device pnp 2e.0 off			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on			# Parallel Port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.2 on			# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.3 on			# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 off end		# Consumer IR
+          device pnp 2e.7 off end		# Game port, GPIO 1
+          device pnp 2e.8 off end		# MIDI port, GPIO 5
+          device pnp 2e.9 off end		# GPIO 2-4
+          device pnp 2e.a off end		# ACPI
+          device pnp 2e.b on			# HWM
+            io 0x60 = 0x290
+          end
+        end
+      end
+      device pci 11.5 on end			# AC'97 audio
+      device pci 12.0 on end			# Ethernet
+    end
+  end
+  device cpu_cluster 0 on			# APIC cluster
+    chip cpu/via/c7			# VIA C7
+      device lapic 0 on end			# APIC
+    end
+  end
+end
diff --git a/src/mainboard/winnet/g170/irq_tables.c b/src/mainboard/winnet/g170/irq_tables.c
new file mode 100644
index 0000000000..15263cc817
--- /dev/null
+++ b/src/mainboard/winnet/g170/irq_tables.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Interrupt router bus */
+	(0x11 << 3) | 0x0,	/* Interrupt router device */
+	0x828,			/* IRQs devoted exclusively to PCI usage */
+	0x1106,			/* Vendor */
+	0x596,			/* Device */
+	0,			/* Miniport data */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x3e,			/* Checksum */
+	{
+		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x08 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0},
+		{0x00,(0x09 << 3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0},
+		{0x00,(0x0a << 3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0},
+		{0x00,(0x0b << 3)|0x0, {{0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0x0def8}}, 0x4, 0x0},
+		{0x00,(0x0c << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x5, 0x0},
+		{0x00,(0x11 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x0f << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x01 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x10 << 3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x0, 0x0},
+		{0x00,(0x12 << 3)|0x0, {{0x01, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/winnet/g170/romstage.c b/src/mainboard/winnet/g170/romstage.c
new file mode 100644
index 0000000000..9ac02d033e
--- /dev/null
+++ b/src/mainboard/winnet/g170/romstage.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include <northbridge/via/cn700/raminit.h>
+#include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
+#include <delay.h>
+#include <lib.h>
+#include <spd.h>
+#include <southbridge/via/vt8237r/vt8237r.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83697hf/w83697hf.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
+
+int spd_read_byte(unsigned device, unsigned address)
+{
+	return smbus_read_byte(device, address);
+}
+
+static void enable_mainboard_devices(void)
+{
+	pci_devfn_t dev;
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+	if (dev == PCI_DEV_INVALID)
+		die("Southbridge not found!!!\n");
+
+	/* bit = 0 means enable function (per CX700 datasheet)
+	 *   5 16.1 USB 2
+	 *   4 16.0 USB 1
+	 *   3 15.0 SATA and PATA
+	 *   2 16.2 USB 3
+	 *   1 16.4 USB EHCI
+	 */
+	pci_write_config8(dev, 0x50, 0x80);
+
+	/* bit = 1 means enable internal function (per CX700 datasheet)
+	 *   3 Internal RTC
+	 *   2 Internal PS2 Mouse
+	 *   1 Internal KBC Configuration
+	 *   0 Internal Keyboard Controller
+	 */
+	pci_write_config8(dev, 0x51, 0x1d);
+}
+
+static const struct mem_controller ctrl = {
+	.d0f0 = 0x0000,
+	.d0f2 = 0x2000,
+	.d0f3 = 0x3000,
+	.d0f4 = 0x4000,
+	.d0f7 = 0x7000,
+	.d1f0 = 0x8000,
+	.channel0 = { DIMM0 },
+};
+
+void main(unsigned long bist)
+{
+	/* Enable multifunction for northbridge. */
+	pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
+
+	w83697hf_set_clksel_48(SERIAL_DEV);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
+
+	enable_smbus();
+	smbus_fixup(ctrl.channel0, ARRAY_SIZE(ctrl.channel0));
+
+	/* Halt if there was a built-in self test failure. */
+	report_bist_failure(bist);
+
+	enable_mainboard_devices();
+
+	ddr_ram_setup(&ctrl);
+}