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Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.
Remove the setup from model_15_init.c because this is duplicated
functionality.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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AMD's fixed MTRRs have RdDram and WrDram bits that route memory
accesses to DRAM vs. MMIO. These are typically hidden for normal
operation by clearing SYS_CFG[19] (MtrrFixDramModEn). According to
BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at
reset, should be set for configuration during POST, then cleared for
normal operation.
Attempting to modify the RdDram and WrDram settings without unhiding
them causes a General Protection Fault. Add functions to enable and
disable MtrrFixDramModEn. Unhide/hide as necessary when copying or
writing the fixed MTRRs.
Finally, modify sipi_vector.S to enable the bits prior to writing
the fixed MTRRs and disable when complete.
This functionality is compiled out on non-AMD platforms.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I6175ce3d3ef739c4f503db826036ffe8feff9ddc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ia0293a0ec85c752686750dadb9730a159fd0c073
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The board does no support eMMC so no need to configure it.
Change-Id: If29009a09f39484b1da16fb650b4f9cbee2a6d19
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The board does not have memory down, only 2 DDR4 Slots.
Change-Id: I70eda83fbce7a707da170c7e555ed1a6dc6b1f4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I213ea13078fdc28489eb4572a084146df333a31d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I1c42519dbe848b0bbcafa7f923d862ba7c9d8ed5
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I6fc1f8393ce3f5ba6f52edad7cf8efa5524d2704
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Use the correct conversion specifier `z` for `size_t` to fix the error
below.
```
error: format '%lx' expects argument of type 'long unsigned int', but \
argument 4 has type 'size_t {aka unsigned int}' [-Werror=format=]
```
Found-by: gcc (Debian 7.3.0-3) 7.3.0
Change-Id: I05d3b6c9eec0ebf77cdb9e9928037e837f87ea03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SMBIOS structure type 17 is not being generated because memory info is
not being stored to cbmem. This has to happen after AGESA AmdInitLate
has run, but before SMBIOS is generated. There's a need to convert
format between AGESA generated info, and what is required in cbmem.
Create a procedure that transfers information between AGESA and cbmem,
and call it from agesawrapper_post_device() after AmdLateInit is called.
BUG=b:65403853
TEST=build and run kahlee, verify if SMBIOS structure type 17 is being
generated, and if associated strings are what should be expected.
Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable the micro-controller interrupt line as a real IRQ.
BUG=b:71986991
BRANCH=none
TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the
number of interrupts incrementing and the MKBP event happening.
Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GPIO pin definition had been updated to match Cannonlake PCH-LP EDS,
hence the ACPI dsdt table will include those changes as well.
BUG=None
TEST=Build coreboot image, flah coreboot image into DUT, and target
system can boot up into OS.
Change-Id: I958e0cb71b4e656bec9bfe2d12076b577b57629b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Switch to use common version of PCR asl.
BUG=NONE
TEST=Boot up into chrome OS properly on cannonlake rvp platform.
Change-Id: I4975704434d4743bcc0fb6062115da349166c3a6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Add group information for each gpio community and use it to
calculate offset of a pad within its group. Original implementation
assumed that the number of gpios in each group is same but that lead to
a bug for cnl since numbers differ for each group.
BUG=b:69616750
TEST=Need to test again on SKL,CNL,APL,GLK
Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22571
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Using common PCR asl for skylake/kabylake platform.
BUG=None
TEST=None
Change-Id: I99ec7c878adaea439108553c0fac9d5abe1bc248
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Access to PCH Private Configuration Space Register can be addressed via
SBERG_BAR, the method is generic across several generations of Intel
SOC.
BUG=None
TEST=None
Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Fill the missing GPIO pin definitions, includeing community 3.
Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22482
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turns out the write-protect GPIO polarity for Scarlet is different than
for Kevin/Gru, and nobody ever told us. Also, it must not be configured
with an internal pull-up or we'll not read the correct value. This patch
fixes both issues.
BRANCH=scarlet
BUG=b:73356326
TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the
right value in all cases.
Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This change enables DPTF and configures the policy. DPTF parameters were
provided by internal power team.
BUG=b:67877437
BRANCH=master
TEST=emerge-nautilus coreboot
Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23731
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Read cse file was not getting cached and taking about 500ms on every boot.
Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the missing *r* of the possessive pronoun *your*.
Change-Id: I2b520f398a904eb8e4412835d90bde1ee0b504b7
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/23758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Procedures acpi_device_scope() and acpi_device_name() can under certain
conditions return NULL. Check the return before using them.
This fixes CID 1385944
BUG=b:73331544
TEST=Build kahlee.
Change-Id: Ifcdf905100d22a1d828394f8685641eb432bb836
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23760
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Procedure mrc_cache_get_current() returns -1 for error, 0 for pass. Do
check the return in procedure get_s3nv_info.
This fixes CID 1385943
BUG=b:73333332
TEST=Build kahlee
Change-Id: I0f6a58380a38d13120e997dcd966423d3c2af091
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add octopus board using GLK soc. Copied base code from mainboard/intel/glkrvp.
TODO: Fix as per octopus schematic.
Change-Id: Ic8c25b3fafbfef31b8b3b802acb3bc53ee7146b6
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23685
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Show mainboard version in the console log so that one can easily see it.
Change-Id: I33bae8b340fce13c0cbe525521828929038b069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The I/O expander on the mc_bdx1 is used to get the hardware version of
the mainboard. This patch enables the chip driver for the I/O expander.
Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The chip PCA9538 is a 8 bit I/O expander connected to the systems I2C
bus. Add a chip driver to support this chip.
Beside the pure chip driver two interface functions are provided to read
the state of the pins and write output values to the pins.
As the slave address of this chip is hardware configurable the function
pca9538_get_dev() is used to get the right slave address. This function
needs to be implemented in mainboard code if one needs to use the
interface functions to read and write I/O state.
Change-Id: Ic856123b4f4c8b721928ee3a2a4bb37833ea4b20
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This format (one hex digit, followed by 'b', followed by binary digits)
is arguably useful, but also confusing. Use the more common format
instead.
Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fixes: b8dc63bdfe ("ic2/designware: Move Intel i2c logic to shared driver")
Change-Id: Ic521a2d60b403b322ae583bb2c26da6019bf0ab0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23714
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Cannonlake FSP header to revision 7.x.25.31. Following changes
had been made:
1. Add PeciSxRest option.
2. Add Thermal Velocity Boost option.
3. Add VR power deliver design option.
4. Match MrcChannelSts.
TEST=NONE
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I32e976eacf39d2cd75f8288c86d1de1a54c194c6
Reviewed-on: https://review.coreboot.org/23677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add missing license and include guard and remove unneeded include.
BUG=b:72121803
TEST=compiles
Change-Id: Ic359ed262086596a98131669f8eecd531857187a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23721
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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LAPIC setup is required to set virtualwire mode for legacy interrupts.
This was omitted when stoneyridge was changed to use the common mp_init.
BUG=b:72351388
TEST=Verify keyboard now works in SeaBIOS
Change-Id: I648d8b5b5a3744a5781446c7cb72934a071f9a72
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Original SPD provided by the vendor had bytes after 254 shifted by 16
bytes. This change fixes the SPD data based on the latest details
received from the vendor.
BUG=b:72749394
TEST=Verified that the device with this memory part boots to OS fine.
Also, mosys is able to dump the right memory information.
Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This adds a struct for registers along with some bits from ATF to
the generic PL011 driver. It also adds a naive implementation of
uart_tx_flush() which was previously stubbed out.
Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I89cf4b996405af616f54cf2d9fabd4e258352b03
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23036
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are now a few architectural extensions available for ARMv8, some
of which introduce instructions or other features that may be useful.
This allows the user to select an extension implemented on their SoC
which will set the -march option passed into the compiler.
Change-Id: Ifca50dad98aab130ac04df455bac2cfb65abf82e
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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BUG=b:69011806, b:72179988
BRANCH=master
TEST=Verify touchscreen on meowth works with this change.
Change-Id: Iad3f0b77a02552266435e523fdbb74b14ada101a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/23551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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TEST=Run powerd_dbus_suspend and resume with button press
BUG=b:69614064
Change-Id: I0a5a610590b599b96dd0def211c4aa31c7a538ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22732
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add/update the romstage and ramstage paths to check for S3 resume
and call the appropriate AGESA functions.
TEST=Suspend/Resume Kahlee with full S3 patch stack
BUG=b:69614064
Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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AMD support in coreboot has typically not used the AmdS3FinalRestore()
Entry Point. Add a call to it immediately prior to resuming to the OS.
BUG=b:69614064
TEST=Check console log for execution
Change-Id: Iadc4438d8cda9766002f6edade3c7b00b23b98b4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add new functions that can execute InitRtb, InitResume, LateResume,
and FinalResume.
Note that the name AmdInitRtb supersedes the deprecated AmdS3Save.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The Arch2008 spec describes an AmdS3FinalRestore Entry Point that
coreboot has been missing. Add the helper function that can call
into the blob to execute this.
BUG=b:69614064
Change-Id: Ic72feb0406cd1d0d5c23e391c2464e12c9e10007
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The AGESA spec states that "Failure to release a structure can cause
undesired outcomes."
Uncomment the one in AmdInitLate(). The function only dealocates the
structure used for the AGESA entry point, and not the internal data
used by coreboot.
Release the structure in AmdInitEnv(). This appears to have been an
omission years ago when duplicating agesawrapper.c for every mainboard
was still common.
BUG=b:70671742
TEST=Build and boot Kahlee, inspect console log
Change-Id: Ib1ff94ec2acdc845c5e4b4ed7088061cfc0c55f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22888
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add functions that the wrapper will call to get and save the S3 data.
The wrapper requires two types of data saved:
* Non-volatile: Information that is the minimum required for bringing
the DRAM controller back online. This change uses the common
mrc_cache driver to manage the storage
* Volatile: May be stored in DRAM; information required to complete
the system restoration process.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Commit 07fe618 [chromeec: Add support for reading second battery info]
added a mutex as part of the ACPI code to determine battery statuses.
Windows is extremely picky about ACPI code, and attempting to acquire
a level 1 mutex without first having acquired a level 0 mutex causes
Windows to hang on boot. Since there's no reason to use a level 1
mutex here, change it to level 0.
Test: Boot Windows on device with ChromeEC without hanging
Change-Id: Icfb0817cfe0c49eb4527a12b507362939a6d32c6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Fine tune 14" BigDaddy USB#2 2.0 strength:
PERPORTPETXISET: 7
PERPORTTXISET: 1
IUSBTXEMPHASISEN: 3
PERPORTTXPEHALF: 0
this value could have USB#2 2.0 EA/function pass.
BUG=b:72922816
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/23649
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In order to reduce BOM cost and board area for imaging solution, the
sensor requires a 19.2/24MHz reference clock from PCH. In addition to
that, having PCH to supply the sensor reference clock will prevent
dependency on CPU power management and also avoid level shifter cost.
Pch iSCLK is only required for CNP-LP with the camera sensor on the
platform.
BUG=None
TEST=Boot up into OS and read back PCH iSCLK programming through
iotools.
Change-Id: I28c97a75f2a7f5122a20c8b8f0f2671037a7eca6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23367
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Previously, we were seeing device boot into the recovery screen with
error code 0x5a. This was root caused to the SATA GPIOs (specifically
DEVSLP) not being initialized early enough, causing the SATA 1 link
detection to time out and the device to reboot into recovery with
0x5a instead of booting into the OS as usual.
BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then type reboot from
the OS.
Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
acpi_header_t
This change makes the Nautilus platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:68686020
TEST=Build, booted nautilus board. Verified kernel reads new strings.
Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/23648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Previously ECT was disabled in commit 22401, on D0 stepping system and
FSP version 7.x.20.52, disabling ECT will cause memory training failure
and the system is stuck at post code 00D5h.
BUG=b.72473063
TEST=Apply patch and build coreboot image, flash into meowth P0 system
with D0 stepping silicon installed, system can pass memory training and
boot up into OS.
Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This change makes Nami platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:70646770
TEST=Verify kernel reads new strings.
Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://review.coreboot.org/23670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add an entry to the grunt devicetree defining the ADAU7002 PDM-to-I2S
converter.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: I90b59ec64f4b841932db42b8a8970ed924283613
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The ADAU7002 is a family of Stereo PDM-to-I2S/TDM conversion ICs from
Analog Devices. On some boards they are a used to convert a PDM audio
data stream from a DMIC to an I2S signal.
Add a driver for populating ACPI table entries for this part.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: I2b64c8e1cbc0a68984482a7d496f8c4498cb6cbe
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23659
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
|
|
Remove manually written asl entries for grunt's DA7219 and MAX98357A
audio codecs, and replace them with equivalent devicetree entries.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: Ia658c54a28a5363aabb4c50478adaca1f46d166a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
Allow specifying the DA7219 interrupt pin as either an Interrupt or
GpioInt.
BUG=b:72121803
TEST=(with whole patch series) Grunt Kernel discovers DA7219 on i2c0
Change-Id: I2d26731bf4c0ad590dad2c5d26c252371f415f9a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
outl takes value then port.
BUG=b:72130849
Test=None
Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
For system without secondary battery, current DSDT will report warning
during build time. Add a conditional check to make sure only battery
index 0 can return success.
TEST=Build pass.
Change-Id: Iae12c5d1aa749948ef4025c8b5e60c97e1b747a5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
As per FSP 2.0 specification and FSP SOC integration guide, its not expected
that SMBIOS Memory Information GUID will be same for all platform. Hence
fsp_find_smbios_memory_info() function inside common/driver code is not
generic one.
Removing this function and making use of fsp_find_extension_hob_by_guid()
to find SMBIOS Memory Info GUID from platform code as needed.
Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add option to have customized DLL setting for EMMC interface to make
EMMC able to run at HS400 speed.
BUG=None
Change-Id: I38bc022d8c05dd1fbd03dc26aa6f33cd249e8248
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add support for KBL RVP8 board
* Add KBL RVP8 support in Konfig.
* Add KBL RVP8 config option in make menuconfig.
* Add descriptor and ME binary paths for RVP8 in Kconfig.
* Add RVP8 board name Kconfig.name.
* Add devicetree.cb for RVP8 in the variants path.
* Add gpio.h for RVP8 in variants/include/variant path.
TEST= Build and boot RVP8.
Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23383
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
This patch revises AC/DC loadlines from VRTT reports.
+----------------+-------+-------+-------+-------+
| Domain/Setting | SA | IA | GTUS | GTS |
+----------------+-------+-------+-------+-------+
| AcLoadline | 11 | 2.4 | 3.1 | 3.1 |
| DcLoadline | 10 | 2.46 | 3.1 | 3.1 |
+----------------+-------+-------+-------+-------+
BUG=b:72351128 b:72129954
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage & ensure the settings
are passed to FSP.
Change-Id: Ib8aeb82973c42723d7b623967f8085c8f1d926eb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
* Add Memory Channel Status Enum for Channel detection.
* Align > 80 characters per line.
* Add hob_size == 0 check.
Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch ensures to have Type 17 SMBIOS table for CannonLake Platform.
TEST=Enable to get correct SMBIOS DIMM type information as per
SMBIOS spec 3.1
Change-Id: I611f9f3fc0e07f026610b7a61bc3599523e4f262
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are
estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4
(71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) +
ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W.
BUG=b:71594855
BRANCH=None
TEST=Make sure correct pmax value is being passed into fsp
Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23633
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
|
|
* micbias_lvl -> micbias-lvl
* mic_amp_in_sel -> mic-amp-in-sel
BUG=b:71875600
TEST=Checked in kernel the values are set
Change-Id: Ife7e8cdd835cc256cd8265593a94df84a510cebb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/23603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.
BUG=b:64207749
TEST=Build gardenia.
Change-Id: I24a71490777b101b069175460f3715ec3ff78240
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Create a generic function that reports an unsuccessful call to
AmdCreateStruct().
Change-Id: I2654b4f21de5a2621086142681181a687be2c8e3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
present, data is valid.
Change-Id: I869bf08341b83f359066709e1e9c03af99482b2c
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/23599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
We share the same shared memory fields for both batteries. When
the host wants to switch battery to read out, it will:
- Set BTID (EC_ACPI_MEM_BATTERY_INDEX) to the required index
- Wait for BITX (EC_MEMMAP_BATT_INDEX) to have the required value
- Then fetch the data
BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
present, data is valid.
Change-Id: Ib06176e6ab4c45a899259f0917e6292121865ed6
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/23598
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Improve the file with:
* C99 inializations for structures
* reorder include files for aesthetics
* remove extraneous whitespace
* remove a stale comment
* make variable naming consistent
* make function arguments consistent
This change clears up all remaining checkpatch issues with the wrapper
with the exception of errors created with AMD definitions, e.g.
ERROR: need consistent spacing around '*' (ctx:WxV)
#32: FILE: src/soc/amd/common/block/pi/agesawrapper.c:32:
void __attribute__((weak)) SetFchMidParams(FCH_INTERFACE *params) {}
BUG=b:62240746
TEST=Build and boot Kahlee
Change-Id: I40985e0cf50df6aa4d830937e7f6b6e7908f72fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add a function to allow an external region to be located in TSEG.
Select the option to use memory outside of cbmem. Increase the size
reserved in TSEG.
Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Leverage the stage_cache mechanism to store a non-specific type
of data. This is not interesting when the location for the cache
is in cbmem. However it will be more useful when an external
location is used, e.g. when the cache is in TSEG, locked from user
modification.
Change-Id: Iaf0b25ebe14c176bbd24fc8942f902f627ca8e6f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
CNP-PCH
This patch ensures soc/sata.c correctly translates pci config offset 0x92
Bit 0-2 [SATA Port x Present (SPDx)]
0 = Port x is enabled.
1 = Port x is disabled.
Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
SATA PCH configuration space registers bit mapping is different
for various SOCs hence common API between SPT-PCH and CNL-PCH causing
issue.
Add new Kconfig option to address this delta between different PCH.
Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to
match the latest schematic changes).
Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is
removed from deep_sx_config as well.
BUG=b:72697650
TEST=Verified:
1. Wake-on-wifi works.
2. Device is able to enter G3 without WAKE# pin causing unwanted wakes
from deep S5.
Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In TPM 2.0 case, if the factory initialization is interrupted after
defining, say, the kernel tpm nvram space but before writing to this
space, the following will happen upon reboot when the factory
initialization will be re-attempted. Writing to this space will be
skipped, and coreboot will finish the factory initialization with
this space remained unwritten. At a later stage, when the rollback
logic will attempt to check the version in the kernel space, it will
fail (TPM2.0 returns an error when reading from unwritten spaces),
and the system will go into recovery with no way out (since the
kernel space will never be written).
This change fixes that by always writing to the kernel, MRC hash and
firmware spaces during factory initialization, even if the space
already existed by that time.
BUG=b:71884828
TEST=delete, define, but not write to the kernel space; trigger
factory initialization; coreboot should fill the kernel
space and continue booting.
Change-Id: I48d8bb4f9fc0e5276e6ec81247b3b6768ec9fa3b
Signed-off-by: Andrey Pronin <apronin@google.com>
Reviewed-on: https://review.coreboot.org/23456
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This patch stores the correct capabilities for EMMC media which in turn
sets the correct timing data for HS400 mode.
Without this code change, EMMC CMD13 is failing at the end of HS400 mode
switching.
BUG=none
BRANCH=none
TEST=Build and boot Soraka
Change-Id: I3f00c9eace7cc136d86a1e07f040fbfc09e0e02e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23541
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch changes the sequence of post_cpus_init() function of mp_init
to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal
boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path.
Also, the fast_spi_cache_bios_region() call inside post_cpus_init()
function is left out, since caching the SPI Bios region is not required
now at this stage.
BUG=none
BRANCH=none
TEST=Build and boot in Soraka (KBL), executed stability tests on multiple
systems.
Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H.
Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23382
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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'Optimizing' MMCONF_BASE_ADDRESS for the native codepath prevents the
use of fallback/normal with both the native raminit and the mrc.bin.
Using the same MMCONF_BASE_ADDRESS as the mrc.bin codepath means that
128MB less is available to devices using the native raminit. Most
devices reserve 2048M for non memory resources below 4G, which in most
cases is more than adequate. Devices with only 1024M (and that don't
already use the mrc.bin) are:
* lenovo/x220
* lenovo/x230
* lenovo/x131e
* lenovo/x1_carbon_gen1
Those could fail to allocate PCI resources, but on at least x220 with
a somewhat default configuration (USB3 expresscard, Wireless PCIe
card) it still boots fine, so one should not expect many problems from
this change.
Change-Id: I1d0648fe36c88bd9279ac19e5c710055327599fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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With the new extra detachable UI elements, we're running out of space in
Scarlet's RO CBFS. Thankfully, the GBB is still massively
overdimensioned, so we can steal another half MB from there.
This patch changes the FMAP for some boards that have already had
production firmware releases. However, all the new changes are to the RO
parts of the FMAP, so there shouldn't be a way this could cause a
problem for updates.
Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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ACPI_NHLT happens to be selected twice.
BRANCH=none
BUG=none
TEST=generated fizz .config does not change
Change-Id: Ic525ee07015deb88fff4c15cad9dbbeada8a4479
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/23601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This driver uses an fmap region for the MRC cache instead of a CBFS
file which makes it easier to manage if one wants to write protect
it.
Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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I2C bus rise/fall times were measured as follows. Signals were generated
with:
- bus 0: manual i2c driver in depthcharge
- bus 2,3: i2cdetect -r <bus_number>
and then measured manually with an oscilloscope.
BUG=b:72442912
Change-Id: I291e144249271ec34a93417398e54e68b8e21e23
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This not hooked up anywhere.
Change-Id: I95a2d14aea6f1a6013edf1bcb88bb35de88cba4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23458
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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PARALLEL_CPU_INIT pertains to initialize_cpus() in
src/cpu/x86/lapic/lapic_cpu_init.c
which haswell does not use as it uses PARALLEL_MP init.
Change-Id: I46b6f72e8e372b8c8564243ece7aed3a9371c621
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove #if statement and replace it with if(IS_ENABLED(...)) per coreboot
recommendations.
BUG=b:62200858
TEST=Build kahlee.
Change-Id: I268b228706a625e1415c4f24e808261c279ba41e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.
BUG=b:64207749
TEST=Build kahlee.
Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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After adding NHLT and max98373 amp support, cnlrvp fails to boot
with error: out of memory (free_mem_ptr >= free_mem_end_ptr).
Increase HEAP_SIZE from 0x4000 to 0x8000.
BUG=None
TEST= emerge-cnlrvp coreboot nhlt-blobs chromeos-bootimage coreboot-private-files-cnlrvp
and verify cnlrvp boots to kernel.
Change-Id: Icb0f3c626b784d73e417e5722b3b4da29ab5acce
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Fix coding style
Change-Id: I1b6913f9fe97e42836a6698645d0d380ceecec0d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23523
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add `cmos.default` to get rid of four seconds in romstage. Choose 8 MB
for size for video RAM.
Order the entries like in `cmos.layout`.
Change-Id: If2dcc266f6f061807401b62647124ce96e9a3802
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/23468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Enable HotPlug for the PCIe root port that the WiFi device
is on so the OS can re-train the link without needing a reboot
if it goes down unexpectedly at runtime.
BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in
linux that it is identified as a HotPlug capable root port.
Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a variable to fill out the FSP UPD variable for PCIe HotPlug,
which allows a mainboard to enable HotPlug on individual root ports.
BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux
that it is identified as a HotPlug capable root port.
Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize non-early i2c buses in ramstage.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I634a7a823cc393243841dbd55e52abe3f0e72c5a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Provide a method for initializing i2c buses that are not marked as
early_init in the device tree. These i2c buses can be enabled in a
mainboard's ramstage, for example.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I6e49b0de9116138ba102377d283e22d7b50d7dca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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According to doc #543977 Power Architecture Guide, PsysPmax is the
maximum platform power. It maps to the full-scale of Psys signal.
This patch adds a "psys_pmax" member in chip information which allows
boards to set up maximum platform power.
BUG=b:71594855
BRANCH=None
TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz
chromeos-mrc coreboot chromeos-bootimage" & ensure correct
PsysPmax value is passed to FSP-S through UPD. Verfied on
KBL-R and KBL-U SKUs.
Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid
brownouts. According to Intel doc #560604, page 74, the max time
window is 64ms (code=6) and the min duty cycle we can set is 4%.
BUG=b:71594855
BRANCH=None
TEST=Boot to OS and check MSRs using iotools for expected values
Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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On EVT, the USB and MIPI cameras share the same power source. As a result,
when the MIPI camera driver turns off the camera once probed, USB camera will
be disconnected. To make USB camera work on EVT devices, we will need a hack in
coreboot to leave the camera power always-on.
BUG=b:72839352
TEST: Verified the MIPI and USB camera function on DUT board
TODO: This power issue will be fixed on DVT build. Will revert this patch
once confirmed power sources for MIPI and USB camera could be supplied
individually.
Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/23546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andy Yeh
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This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails,
it falls back to GPIO pins.
BUG=b:70294260
BRANCH=none
TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz.
Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23548
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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