diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-01-31 23:11:08 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-06 15:21:19 +0000 |
| commit | 9cf7a469b6a7ce878fb3c0f78b79c7dcea071308 (patch) | |
| tree | f75f755e6a2196ae2bcb9f2448c1c24b02566864 /src | |
| parent | 75f5d9991deba9c73e021a93800915ee8c042ab9 (diff) | |
mainboard/broadcom/blast: Remove unnecessary braces {}
Fix coding style
Change-Id: I1b6913f9fe97e42836a6698645d0d380ceecec0d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23523
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/broadcom/blast/mptable.c | 29 |
1 files changed, 10 insertions, 19 deletions
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index 2417c965f7..854e255f8c 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) { device_t dev = 0; struct resource *res; - for(i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -63,9 +63,8 @@ static void *smp_write_config_table(void *v) //USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i = 0; i < 3; i++) { + for (i = 0; i < 3; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // - } @@ -85,51 +84,43 @@ static void *smp_write_config_table(void *v) } //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4 << 2)|i, apicid_bcm5785[1], 2 + (0+i)%4); // - } //pci slot (on bcm5785) - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4 << 2)|i, apicid_bcm5785[1], i%2); // - } //onboard ati smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5 << 2)|0, apicid_bcm5785[1], 0x1); //PCI-X on bcm5780 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4 << 2)|i, apicid_bcm5785[1], 6 + (0+i)%4); // - } - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5 << 2)|i, apicid_bcm5785[1], 6 + (1+i)%4); // - } //onboard Broadcom - for(i = 0; i < 2; i++) { + for (i = 0; i < 2; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4 << 2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); // - } // First PCI-E x8 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0 << 2)|i, apicid_bcm5785[1], 0xe); // - } // Second PCI-E x8 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0 << 2)|i, apicid_bcm5785[1], 0xc); // - } // Third PCI-E x1 - for(i = 0; i < 4; i++) { + for (i = 0; i < 4; i++) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0 << 2)|i, apicid_bcm5785[1], 0xd); // - } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); |